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1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-2 */3/*4 *5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.6 * All Rights Reserved.7 *8 * Permission is hereby granted, free of charge, to any person obtaining a9 * copy of this software and associated documentation files (the10 * "Software"), to deal in the Software without restriction, including11 * without limitation the rights to use, copy, modify, merge, publish,12 * distribute, sub license, and/or sell copies of the Software, and to13 * permit persons to whom the Software is furnished to do so, subject to14 * the following conditions:15 *16 * The above copyright notice and this permission notice (including the17 * next paragraph) shall be included in all copies or substantial portions18 * of the Software.19 *20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.27 *28 */29 30#include <linux/acpi.h>31#include <linux/device.h>32#include <linux/module.h>33#include <linux/oom.h>34#include <linux/pci.h>35#include <linux/pm.h>36#include <linux/pm_runtime.h>37#include <linux/slab.h>38#include <linux/string_helpers.h>39#include <linux/vga_switcheroo.h>40#include <linux/vt.h>41 42#include <drm/drm_aperture.h>43#include <drm/drm_atomic_helper.h>44#include <drm/drm_ioctl.h>45#include <drm/drm_managed.h>46#include <drm/drm_probe_helper.h>47 48#include "display/intel_acpi.h"49#include "display/intel_bw.h"50#include "display/intel_cdclk.h"51#include "display/intel_display_driver.h"52#include "display/intel_display.h"53#include "display/intel_dmc.h"54#include "display/intel_dp.h"55#include "display/intel_dpt.h"56#include "display/intel_encoder.h"57#include "display/intel_fbdev.h"58#include "display/intel_hotplug.h"59#include "display/intel_overlay.h"60#include "display/intel_pch_refclk.h"61#include "display/intel_pps.h"62#include "display/intel_sprite.h"63#include "display/skl_watermark.h"64 65#include "gem/i915_gem_context.h"66#include "gem/i915_gem_create.h"67#include "gem/i915_gem_dmabuf.h"68#include "gem/i915_gem_ioctls.h"69#include "gem/i915_gem_mman.h"70#include "gem/i915_gem_pm.h"71#include "gt/intel_gt.h"72#include "gt/intel_gt_pm.h"73#include "gt/intel_gt_print.h"74#include "gt/intel_rc6.h"75 76#include "pxp/intel_pxp.h"77#include "pxp/intel_pxp_debugfs.h"78#include "pxp/intel_pxp_pm.h"79 80#include "soc/intel_dram.h"81#include "soc/intel_gmch.h"82 83#include "i915_debugfs.h"84#include "i915_driver.h"85#include "i915_drm_client.h"86#include "i915_drv.h"87#include "i915_file_private.h"88#include "i915_getparam.h"89#include "i915_hwmon.h"90#include "i915_ioc32.h"91#include "i915_ioctl.h"92#include "i915_irq.h"93#include "i915_memcpy.h"94#include "i915_perf.h"95#include "i915_query.h"96#include "i915_suspend.h"97#include "i915_switcheroo.h"98#include "i915_sysfs.h"99#include "i915_utils.h"100#include "i915_vgpu.h"101#include "intel_clock_gating.h"102#include "intel_gvt.h"103#include "intel_memory_region.h"104#include "intel_pci_config.h"105#include "intel_pcode.h"106#include "intel_region_ttm.h"107#include "vlv_suspend.h"108 109static const struct drm_driver i915_drm_driver;110 111static int i915_workqueues_init(struct drm_i915_private *dev_priv)112{113 /*114 * The i915 workqueue is primarily used for batched retirement of115 * requests (and thus managing bo) once the task has been completed116 * by the GPU. i915_retire_requests() is called directly when we117 * need high-priority retirement, such as waiting for an explicit118 * bo.119 *120 * It is also used for periodic low-priority events, such as121 * idle-timers and recording error state.122 *123 * All tasks on the workqueue are expected to acquire the dev mutex124 * so there is no point in running more than one instance of the125 * workqueue at any time. Use an ordered one.126 */127 dev_priv->wq = alloc_ordered_workqueue("i915", 0);128 if (dev_priv->wq == NULL)129 goto out_err;130 131 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);132 if (dev_priv->display.hotplug.dp_wq == NULL)133 goto out_free_wq;134 135 /*136 * The unordered i915 workqueue should be used for all work137 * scheduling that do not require running in order, which used138 * to be scheduled on the system_wq before moving to a driver139 * instance due deprecation of flush_scheduled_work().140 */141 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);142 if (dev_priv->unordered_wq == NULL)143 goto out_free_dp_wq;144 145 return 0;146 147out_free_dp_wq:148 destroy_workqueue(dev_priv->display.hotplug.dp_wq);149out_free_wq:150 destroy_workqueue(dev_priv->wq);151out_err:152 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");153 154 return -ENOMEM;155}156 157static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)158{159 destroy_workqueue(dev_priv->unordered_wq);160 destroy_workqueue(dev_priv->display.hotplug.dp_wq);161 destroy_workqueue(dev_priv->wq);162}163 164/*165 * We don't keep the workarounds for pre-production hardware, so we expect our166 * driver to fail on these machines in one way or another. A little warning on167 * dmesg may help both the user and the bug triagers.168 *169 * Our policy for removing pre-production workarounds is to keep the170 * current gen workarounds as a guide to the bring-up of the next gen171 * (workarounds have a habit of persisting!). Anything older than that172 * should be removed along with the complications they introduce.173 */174static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)175{176 bool pre = false;177 178 pre |= IS_HASWELL_EARLY_SDV(dev_priv);179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;186 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;187 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;188 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;189 190 if (pre) {191 drm_err(&dev_priv->drm, "This is a pre-production stepping. "192 "It may not be fully functional.\n");193 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);194 }195}196 197static void sanitize_gpu(struct drm_i915_private *i915)198{199 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {200 struct intel_gt *gt;201 unsigned int i;202 203 for_each_gt(gt, i915, i)204 intel_gt_reset_all_engines(gt);205 }206}207 208/**209 * i915_driver_early_probe - setup state not requiring device access210 * @dev_priv: device private211 *212 * Initialize everything that is a "SW-only" state, that is state not213 * requiring accessing the device or exposing the driver via kernel internal214 * or userspace interfaces. Example steps belonging here: lock initialization,215 * system memory allocation, setting up device specific attributes and216 * function hooks not requiring accessing the device.217 */218static int i915_driver_early_probe(struct drm_i915_private *dev_priv)219{220 int ret = 0;221 222 if (i915_inject_probe_failure(dev_priv))223 return -ENODEV;224 225 intel_device_info_runtime_init_early(dev_priv);226 227 intel_step_init(dev_priv);228 229 intel_uncore_mmio_debug_init_early(dev_priv);230 231 spin_lock_init(&dev_priv->irq_lock);232 spin_lock_init(&dev_priv->gpu_error.lock);233 234 mutex_init(&dev_priv->sb_lock);235 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);236 237 i915_memcpy_init_early(dev_priv);238 intel_runtime_pm_init_early(&dev_priv->runtime_pm);239 240 ret = i915_workqueues_init(dev_priv);241 if (ret < 0)242 return ret;243 244 ret = vlv_suspend_init(dev_priv);245 if (ret < 0)246 goto err_workqueues;247 248 ret = intel_region_ttm_device_init(dev_priv);249 if (ret)250 goto err_ttm;251 252 ret = intel_root_gt_init_early(dev_priv);253 if (ret < 0)254 goto err_rootgt;255 256 i915_gem_init_early(dev_priv);257 258 /* This must be called before any calls to HAS_PCH_* */259 intel_detect_pch(dev_priv);260 261 intel_irq_init(dev_priv);262 intel_display_driver_early_probe(dev_priv);263 intel_clock_gating_hooks_init(dev_priv);264 265 intel_detect_preproduction_hw(dev_priv);266 267 return 0;268 269err_rootgt:270 intel_region_ttm_device_fini(dev_priv);271err_ttm:272 vlv_suspend_cleanup(dev_priv);273err_workqueues:274 i915_workqueues_cleanup(dev_priv);275 return ret;276}277 278/**279 * i915_driver_late_release - cleanup the setup done in280 * i915_driver_early_probe()281 * @dev_priv: device private282 */283static void i915_driver_late_release(struct drm_i915_private *dev_priv)284{285 intel_irq_fini(dev_priv);286 intel_power_domains_cleanup(dev_priv);287 i915_gem_cleanup_early(dev_priv);288 intel_gt_driver_late_release_all(dev_priv);289 intel_region_ttm_device_fini(dev_priv);290 vlv_suspend_cleanup(dev_priv);291 i915_workqueues_cleanup(dev_priv);292 293 cpu_latency_qos_remove_request(&dev_priv->sb_qos);294 mutex_destroy(&dev_priv->sb_lock);295 296 i915_params_free(&dev_priv->params);297}298 299/**300 * i915_driver_mmio_probe - setup device MMIO301 * @dev_priv: device private302 *303 * Setup minimal device state necessary for MMIO accesses later in the304 * initialization sequence. The setup here should avoid any other device-wide305 * side effects or exposing the driver via kernel internal or user space306 * interfaces.307 */308static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)309{310 struct intel_gt *gt;311 int ret, i;312 313 if (i915_inject_probe_failure(dev_priv))314 return -ENODEV;315 316 ret = intel_gmch_bridge_setup(dev_priv);317 if (ret < 0)318 return ret;319 320 for_each_gt(gt, dev_priv, i) {321 ret = intel_uncore_init_mmio(gt->uncore);322 if (ret)323 return ret;324 325 ret = drmm_add_action_or_reset(&dev_priv->drm,326 intel_uncore_fini_mmio,327 gt->uncore);328 if (ret)329 return ret;330 }331 332 /* Try to make sure MCHBAR is enabled before poking at it */333 intel_gmch_bar_setup(dev_priv);334 intel_device_info_runtime_init(dev_priv);335 intel_display_device_info_runtime_init(dev_priv);336 337 for_each_gt(gt, dev_priv, i) {338 ret = intel_gt_init_mmio(gt);339 if (ret)340 goto err_uncore;341 }342 343 /* As early as possible, scrub existing GPU state before clobbering */344 sanitize_gpu(dev_priv);345 346 return 0;347 348err_uncore:349 intel_gmch_bar_teardown(dev_priv);350 351 return ret;352}353 354/**355 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()356 * @dev_priv: device private357 */358static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)359{360 intel_gmch_bar_teardown(dev_priv);361}362 363/**364 * i915_set_dma_info - set all relevant PCI dma info as configured for the365 * platform366 * @i915: valid i915 instance367 *368 * Set the dma max segment size, device and coherent masks. The dma mask set369 * needs to occur before i915_ggtt_probe_hw.370 *371 * A couple of platforms have special needs. Address them as well.372 *373 */374static int i915_set_dma_info(struct drm_i915_private *i915)375{376 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;377 int ret;378 379 GEM_BUG_ON(!mask_size);380 381 /*382 * We don't have a max segment size, so set it to the max so sg's383 * debugging layer doesn't complain384 */385 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);386 387 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));388 if (ret)389 goto mask_err;390 391 /* overlay on gen2 is broken and can't address above 1G */392 if (GRAPHICS_VER(i915) == 2)393 mask_size = 30;394 395 /*396 * 965GM sometimes incorrectly writes to hardware status page (HWS)397 * using 32bit addressing, overwriting memory if HWS is located398 * above 4GB.399 *400 * The documentation also mentions an issue with undefined401 * behaviour if any general state is accessed within a page above 4GB,402 * which also needs to be handled carefully.403 */404 if (IS_I965G(i915) || IS_I965GM(i915))405 mask_size = 32;406 407 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));408 if (ret)409 goto mask_err;410 411 return 0;412 413mask_err:414 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);415 return ret;416}417 418static int i915_pcode_init(struct drm_i915_private *i915)419{420 struct intel_gt *gt;421 int id, ret;422 423 for_each_gt(gt, i915, id) {424 ret = intel_pcode_init(gt->uncore);425 if (ret) {426 gt_err(gt, "intel_pcode_init failed %d\n", ret);427 return ret;428 }429 }430 431 return 0;432}433 434/**435 * i915_driver_hw_probe - setup state requiring device access436 * @dev_priv: device private437 *438 * Setup state that requires accessing the device, but doesn't require439 * exposing the driver via kernel internal or userspace interfaces.440 */441static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)442{443 struct intel_display *display = &dev_priv->display;444 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);445 int ret;446 447 if (i915_inject_probe_failure(dev_priv))448 return -ENODEV;449 450 if (HAS_PPGTT(dev_priv)) {451 if (intel_vgpu_active(dev_priv) &&452 !intel_vgpu_has_full_ppgtt(dev_priv)) {453 drm_err(&dev_priv->drm,454 "incompatible vGPU found, support for isolated ppGTT required\n");455 return -ENXIO;456 }457 }458 459 if (HAS_EXECLISTS(dev_priv)) {460 /*461 * Older GVT emulation depends upon intercepting CSB mmio,462 * which we no longer use, preferring to use the HWSP cache463 * instead.464 */465 if (intel_vgpu_active(dev_priv) &&466 !intel_vgpu_has_hwsp_emulation(dev_priv)) {467 drm_err(&dev_priv->drm,468 "old vGPU host found, support for HWSP emulation required\n");469 return -ENXIO;470 }471 }472 473 /* needs to be done before ggtt probe */474 intel_dram_edram_detect(dev_priv);475 476 ret = i915_set_dma_info(dev_priv);477 if (ret)478 return ret;479 480 ret = i915_perf_init(dev_priv);481 if (ret)482 return ret;483 484 ret = i915_ggtt_probe_hw(dev_priv);485 if (ret)486 goto err_perf;487 488 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);489 if (ret)490 goto err_ggtt;491 492 ret = i915_ggtt_init_hw(dev_priv);493 if (ret)494 goto err_ggtt;495 496 /*497 * Make sure we probe lmem before we probe stolen-lmem. The BAR size498 * might be different due to bar resizing.499 */500 ret = intel_gt_tiles_init(dev_priv);501 if (ret)502 goto err_ggtt;503 504 ret = intel_memory_regions_hw_probe(dev_priv);505 if (ret)506 goto err_ggtt;507 508 ret = i915_ggtt_enable_hw(dev_priv);509 if (ret) {510 drm_err(&dev_priv->drm, "failed to enable GGTT\n");511 goto err_mem_regions;512 }513 514 pci_set_master(pdev);515 516 /* On the 945G/GM, the chipset reports the MSI capability on the517 * integrated graphics even though the support isn't actually there518 * according to the published specs. It doesn't appear to function519 * correctly in testing on 945G.520 * This may be a side effect of MSI having been made available for PEG521 * and the registers being closely associated.522 *523 * According to chipset errata, on the 965GM, MSI interrupts may524 * be lost or delayed, and was defeatured. MSI interrupts seem to525 * get lost on g4x as well, and interrupt delivery seems to stay526 * properly dead afterwards. So we'll just disable them for all527 * pre-gen5 chipsets.528 *529 * dp aux and gmbus irq on gen4 seems to be able to generate legacy530 * interrupts even when in MSI mode. This results in spurious531 * interrupt warnings if the legacy irq no. is shared with another532 * device. The kernel then disables that interrupt source and so533 * prevents the other device from working properly.534 */535 if (GRAPHICS_VER(dev_priv) >= 5) {536 if (pci_enable_msi(pdev) < 0)537 drm_dbg(&dev_priv->drm, "can't enable MSI");538 }539 540 ret = intel_gvt_init(dev_priv);541 if (ret)542 goto err_msi;543 544 intel_opregion_setup(display);545 546 ret = i915_pcode_init(dev_priv);547 if (ret)548 goto err_opregion;549 550 /*551 * Fill the dram structure to get the system dram info. This will be552 * used for memory latency calculation.553 */554 intel_dram_detect(dev_priv);555 556 intel_bw_init_hw(dev_priv);557 558 return 0;559 560err_opregion:561 intel_opregion_cleanup(display);562err_msi:563 if (pdev->msi_enabled)564 pci_disable_msi(pdev);565err_mem_regions:566 intel_memory_regions_driver_release(dev_priv);567err_ggtt:568 i915_ggtt_driver_release(dev_priv);569 i915_gem_drain_freed_objects(dev_priv);570 i915_ggtt_driver_late_release(dev_priv);571err_perf:572 i915_perf_fini(dev_priv);573 return ret;574}575 576/**577 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()578 * @dev_priv: device private579 */580static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)581{582 struct intel_display *display = &dev_priv->display;583 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);584 585 i915_perf_fini(dev_priv);586 587 intel_opregion_cleanup(display);588 589 if (pdev->msi_enabled)590 pci_disable_msi(pdev);591}592 593/**594 * i915_driver_register - register the driver with the rest of the system595 * @dev_priv: device private596 *597 * Perform any steps necessary to make the driver available via kernel598 * internal or userspace interfaces.599 */600static void i915_driver_register(struct drm_i915_private *dev_priv)601{602 struct intel_gt *gt;603 unsigned int i;604 605 i915_gem_driver_register(dev_priv);606 i915_pmu_register(dev_priv);607 608 intel_vgpu_register(dev_priv);609 610 /* Reveal our presence to userspace */611 if (drm_dev_register(&dev_priv->drm, 0)) {612 drm_err(&dev_priv->drm,613 "Failed to register driver for userspace access!\n");614 return;615 }616 617 i915_debugfs_register(dev_priv);618 i915_setup_sysfs(dev_priv);619 620 /* Depends on sysfs having been initialized */621 i915_perf_register(dev_priv);622 623 for_each_gt(gt, dev_priv, i)624 intel_gt_driver_register(gt);625 626 intel_pxp_debugfs_register(dev_priv->pxp);627 628 i915_hwmon_register(dev_priv);629 630 intel_display_driver_register(dev_priv);631 632 intel_power_domains_enable(dev_priv);633 intel_runtime_pm_enable(&dev_priv->runtime_pm);634 635 intel_register_dsm_handler();636 637 if (i915_switcheroo_register(dev_priv))638 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");639}640 641/**642 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()643 * @dev_priv: device private644 */645static void i915_driver_unregister(struct drm_i915_private *dev_priv)646{647 struct intel_gt *gt;648 unsigned int i;649 650 i915_switcheroo_unregister(dev_priv);651 652 intel_unregister_dsm_handler();653 654 intel_runtime_pm_disable(&dev_priv->runtime_pm);655 intel_power_domains_disable(dev_priv);656 657 intel_display_driver_unregister(dev_priv);658 659 intel_pxp_fini(dev_priv);660 661 for_each_gt(gt, dev_priv, i)662 intel_gt_driver_unregister(gt);663 664 i915_hwmon_unregister(dev_priv);665 666 i915_perf_unregister(dev_priv);667 i915_pmu_unregister(dev_priv);668 669 i915_teardown_sysfs(dev_priv);670 drm_dev_unplug(&dev_priv->drm);671 672 i915_gem_driver_unregister(dev_priv);673}674 675void676i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)677{678 drm_printf(p, "iommu: %s\n",679 str_enabled_disabled(i915_vtd_active(i915)));680}681 682static void i915_welcome_messages(struct drm_i915_private *dev_priv)683{684 if (drm_debug_enabled(DRM_UT_DRIVER)) {685 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER,686 "device info:");687 struct intel_gt *gt;688 unsigned int i;689 690 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",691 INTEL_DEVID(dev_priv),692 INTEL_REVID(dev_priv),693 intel_platform_name(INTEL_INFO(dev_priv)->platform),694 intel_subplatform(RUNTIME_INFO(dev_priv),695 INTEL_INFO(dev_priv)->platform),696 GRAPHICS_VER(dev_priv));697 698 intel_device_info_print(INTEL_INFO(dev_priv),699 RUNTIME_INFO(dev_priv), &p);700 i915_print_iommu_status(dev_priv, &p);701 for_each_gt(gt, dev_priv, i)702 intel_gt_info_print(>->info, &p);703 }704 705 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))706 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))708 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");709 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))710 drm_info(&dev_priv->drm,711 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");712}713 714static struct drm_i915_private *715i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)716{717 const struct intel_device_info *match_info =718 (struct intel_device_info *)ent->driver_data;719 struct drm_i915_private *i915;720 721 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,722 struct drm_i915_private, drm);723 if (IS_ERR(i915))724 return i915;725 726 pci_set_drvdata(pdev, &i915->drm);727 728 /* Device parameters start as a copy of module parameters. */729 i915_params_copy(&i915->params, &i915_modparams);730 731 /* Set up device info and initial runtime info. */732 intel_device_info_driver_create(i915, pdev->device, match_info);733 734 intel_display_device_probe(i915);735 736 return i915;737}738 739/**740 * i915_driver_probe - setup chip and create an initial config741 * @pdev: PCI device742 * @ent: matching PCI ID entry743 *744 * The driver probe routine has to do several things:745 * - drive output discovery via intel_display_driver_probe()746 * - initialize the memory manager747 * - allocate initial config memory748 * - setup the DRM framebuffer with the allocated memory749 */750int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)751{752 struct drm_i915_private *i915;753 int ret;754 755 ret = pci_enable_device(pdev);756 if (ret) {757 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));758 return ret;759 }760 761 i915 = i915_driver_create(pdev, ent);762 if (IS_ERR(i915)) {763 pci_disable_device(pdev);764 return PTR_ERR(i915);765 }766 767 ret = i915_driver_early_probe(i915);768 if (ret < 0)769 goto out_pci_disable;770 771 disable_rpm_wakeref_asserts(&i915->runtime_pm);772 773 intel_vgpu_detect(i915);774 775 ret = intel_gt_probe_all(i915);776 if (ret < 0)777 goto out_runtime_pm_put;778 779 ret = i915_driver_mmio_probe(i915);780 if (ret < 0)781 goto out_runtime_pm_put;782 783 ret = i915_driver_hw_probe(i915);784 if (ret < 0)785 goto out_cleanup_mmio;786 787 ret = intel_display_driver_probe_noirq(i915);788 if (ret < 0)789 goto out_cleanup_hw;790 791 ret = intel_irq_install(i915);792 if (ret)793 goto out_cleanup_modeset;794 795 ret = intel_display_driver_probe_nogem(i915);796 if (ret)797 goto out_cleanup_irq;798 799 ret = i915_gem_init(i915);800 if (ret)801 goto out_cleanup_modeset2;802 803 ret = intel_pxp_init(i915);804 if (ret && ret != -ENODEV)805 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);806 807 ret = intel_display_driver_probe(i915);808 if (ret)809 goto out_cleanup_gem;810 811 i915_driver_register(i915);812 813 enable_rpm_wakeref_asserts(&i915->runtime_pm);814 815 i915_welcome_messages(i915);816 817 i915->do_release = true;818 819 return 0;820 821out_cleanup_gem:822 i915_gem_suspend(i915);823 i915_gem_driver_remove(i915);824 i915_gem_driver_release(i915);825out_cleanup_modeset2:826 /* FIXME clean up the error path */827 intel_display_driver_remove(i915);828 intel_irq_uninstall(i915);829 intel_display_driver_remove_noirq(i915);830 goto out_cleanup_modeset;831out_cleanup_irq:832 intel_irq_uninstall(i915);833out_cleanup_modeset:834 intel_display_driver_remove_nogem(i915);835out_cleanup_hw:836 i915_driver_hw_remove(i915);837 intel_memory_regions_driver_release(i915);838 i915_ggtt_driver_release(i915);839 i915_gem_drain_freed_objects(i915);840 i915_ggtt_driver_late_release(i915);841out_cleanup_mmio:842 i915_driver_mmio_release(i915);843out_runtime_pm_put:844 enable_rpm_wakeref_asserts(&i915->runtime_pm);845 i915_driver_late_release(i915);846out_pci_disable:847 pci_disable_device(pdev);848 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);849 return ret;850}851 852void i915_driver_remove(struct drm_i915_private *i915)853{854 intel_wakeref_t wakeref;855 856 wakeref = intel_runtime_pm_get(&i915->runtime_pm);857 858 i915_driver_unregister(i915);859 860 /* Flush any external code that still may be under the RCU lock */861 synchronize_rcu();862 863 i915_gem_suspend(i915);864 865 intel_gvt_driver_remove(i915);866 867 intel_display_driver_remove(i915);868 869 intel_irq_uninstall(i915);870 871 intel_display_driver_remove_noirq(i915);872 873 i915_reset_error_state(i915);874 i915_gem_driver_remove(i915);875 876 intel_display_driver_remove_nogem(i915);877 878 i915_driver_hw_remove(i915);879 880 intel_runtime_pm_put(&i915->runtime_pm, wakeref);881}882 883static void i915_driver_release(struct drm_device *dev)884{885 struct drm_i915_private *dev_priv = to_i915(dev);886 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;887 intel_wakeref_t wakeref;888 889 if (!dev_priv->do_release)890 return;891 892 wakeref = intel_runtime_pm_get(rpm);893 894 i915_gem_driver_release(dev_priv);895 896 intel_memory_regions_driver_release(dev_priv);897 i915_ggtt_driver_release(dev_priv);898 i915_gem_drain_freed_objects(dev_priv);899 i915_ggtt_driver_late_release(dev_priv);900 901 i915_driver_mmio_release(dev_priv);902 903 intel_runtime_pm_put(rpm, wakeref);904 905 intel_runtime_pm_driver_release(rpm);906 907 i915_driver_late_release(dev_priv);908 909 intel_display_device_remove(dev_priv);910}911 912static int i915_driver_open(struct drm_device *dev, struct drm_file *file)913{914 struct drm_i915_private *i915 = to_i915(dev);915 int ret;916 917 ret = i915_gem_open(i915, file);918 if (ret)919 return ret;920 921 return 0;922}923 924static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)925{926 struct drm_i915_file_private *file_priv = file->driver_priv;927 928 i915_gem_context_close(file);929 i915_drm_client_put(file_priv->client);930 931 kfree_rcu(file_priv, rcu);932 933 /* Catch up with all the deferred frees from "this" client */934 i915_gem_flush_free_objects(to_i915(dev));935}936 937void i915_driver_shutdown(struct drm_i915_private *i915)938{939 disable_rpm_wakeref_asserts(&i915->runtime_pm);940 intel_runtime_pm_disable(&i915->runtime_pm);941 intel_power_domains_disable(i915);942 943 intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true);944 if (HAS_DISPLAY(i915)) {945 drm_kms_helper_poll_disable(&i915->drm);946 intel_display_driver_disable_user_access(i915);947 948 drm_atomic_helper_shutdown(&i915->drm);949 }950 951 intel_dp_mst_suspend(i915);952 953 intel_runtime_pm_disable_interrupts(i915);954 intel_hpd_cancel_work(i915);955 956 if (HAS_DISPLAY(i915))957 intel_display_driver_suspend_access(i915);958 959 intel_encoder_suspend_all(&i915->display);960 intel_encoder_shutdown_all(&i915->display);961 962 intel_dmc_suspend(i915);963 964 i915_gem_suspend(i915);965 966 /*967 * The only requirement is to reboot with display DC states disabled,968 * for now leaving all display power wells in the INIT power domain969 * enabled.970 *971 * TODO:972 * - unify the pci_driver::shutdown sequence here with the973 * pci_driver.driver.pm.poweroff,poweroff_late sequence.974 * - unify the driver remove and system/runtime suspend sequences with975 * the above unified shutdown/poweroff sequence.976 */977 intel_power_domains_driver_remove(i915);978 enable_rpm_wakeref_asserts(&i915->runtime_pm);979 980 intel_runtime_pm_driver_last_release(&i915->runtime_pm);981}982 983static bool suspend_to_idle(struct drm_i915_private *dev_priv)984{985#if IS_ENABLED(CONFIG_ACPI_SLEEP)986 if (acpi_target_system_state() < ACPI_STATE_S3)987 return true;988#endif989 return false;990}991 992static void i915_drm_complete(struct drm_device *dev)993{994 struct drm_i915_private *i915 = to_i915(dev);995 996 intel_pxp_resume_complete(i915->pxp);997}998 999static int i915_drm_prepare(struct drm_device *dev)1000{1001 struct drm_i915_private *i915 = to_i915(dev);1002 1003 intel_pxp_suspend_prepare(i915->pxp);1004 1005 /*1006 * NB intel_display_driver_suspend() may issue new requests after we've1007 * ostensibly marked the GPU as ready-to-sleep here. We need to1008 * split out that work and pull it forward so that after point,1009 * the GPU is not woken again.1010 */1011 return i915_gem_backup_suspend(i915);1012}1013 1014static int i915_drm_suspend(struct drm_device *dev)1015{1016 struct drm_i915_private *dev_priv = to_i915(dev);1017 struct intel_display *display = &dev_priv->display;1018 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);1019 pci_power_t opregion_target_state;1020 1021 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1022 1023 /* We do a lot of poking in a lot of registers, make sure they work1024 * properly. */1025 intel_power_domains_disable(dev_priv);1026 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);1027 if (HAS_DISPLAY(dev_priv)) {1028 drm_kms_helper_poll_disable(dev);1029 intel_display_driver_disable_user_access(dev_priv);1030 }1031 1032 pci_save_state(pdev);1033 1034 intel_display_driver_suspend(dev_priv);1035 1036 intel_dp_mst_suspend(dev_priv);1037 1038 intel_runtime_pm_disable_interrupts(dev_priv);1039 intel_hpd_cancel_work(dev_priv);1040 1041 if (HAS_DISPLAY(dev_priv))1042 intel_display_driver_suspend_access(dev_priv);1043 1044 intel_encoder_suspend_all(&dev_priv->display);1045 1046 /* Must be called before GGTT is suspended. */1047 intel_dpt_suspend(dev_priv);1048 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);1049 1050 i915_save_display(dev_priv);1051 1052 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;1053 intel_opregion_suspend(display, opregion_target_state);1054 1055 dev_priv->suspend_count++;1056 1057 intel_dmc_suspend(dev_priv);1058 1059 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1060 1061 i915_gem_drain_freed_objects(dev_priv);1062 1063 return 0;1064}1065 1066static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)1067{1068 struct drm_i915_private *dev_priv = to_i915(dev);1069 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);1070 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;1071 struct intel_gt *gt;1072 int ret, i;1073 bool s2idle = !hibernation && suspend_to_idle(dev_priv);1074 1075 disable_rpm_wakeref_asserts(rpm);1076 1077 intel_pxp_suspend(dev_priv->pxp);1078 1079 i915_gem_suspend_late(dev_priv);1080 1081 for_each_gt(gt, dev_priv, i)1082 intel_uncore_suspend(gt->uncore);1083 1084 intel_power_domains_suspend(dev_priv, s2idle);1085 1086 intel_display_power_suspend_late(dev_priv);1087 1088 ret = vlv_suspend_complete(dev_priv);1089 if (ret) {1090 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);1091 intel_power_domains_resume(dev_priv);1092 1093 goto out;1094 }1095 1096 pci_disable_device(pdev);1097 /*1098 * During hibernation on some platforms the BIOS may try to access1099 * the device even though it's already in D3 and hang the machine. So1100 * leave the device in D0 on those platforms and hope the BIOS will1101 * power down the device properly. The issue was seen on multiple old1102 * GENs with different BIOS vendors, so having an explicit blacklist1103 * is inpractical; apply the workaround on everything pre GEN6. The1104 * platforms where the issue was seen:1105 * Lenovo Thinkpad X301, X61s, X60, T60, X411106 * Fujitsu FSC S71101107 * Acer Aspire 1830T1108 */1109 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))1110 pci_set_power_state(pdev, PCI_D3hot);1111 1112out:1113 enable_rpm_wakeref_asserts(rpm);1114 if (!dev_priv->uncore.user_forcewake_count)1115 intel_runtime_pm_driver_release(rpm);1116 1117 return ret;1118}1119 1120int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,1121 pm_message_t state)1122{1123 int error;1124 1125 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&1126 state.event != PM_EVENT_FREEZE))1127 return -EINVAL;1128 1129 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1130 return 0;1131 1132 error = i915_drm_suspend(&i915->drm);1133 if (error)1134 return error;1135 1136 return i915_drm_suspend_late(&i915->drm, false);1137}1138 1139static int i915_drm_resume(struct drm_device *dev)1140{1141 struct drm_i915_private *dev_priv = to_i915(dev);1142 struct intel_display *display = &dev_priv->display;1143 struct intel_gt *gt;1144 int ret, i;1145 1146 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1147 1148 ret = i915_pcode_init(dev_priv);1149 if (ret)1150 return ret;1151 1152 sanitize_gpu(dev_priv);1153 1154 ret = i915_ggtt_enable_hw(dev_priv);1155 if (ret)1156 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");1157 1158 i915_ggtt_resume(to_gt(dev_priv)->ggtt);1159 1160 for_each_gt(gt, dev_priv, i)1161 if (GRAPHICS_VER(gt->i915) >= 8)1162 setup_private_pat(gt);1163 1164 /* Must be called after GGTT is resumed. */1165 intel_dpt_resume(dev_priv);1166 1167 intel_dmc_resume(dev_priv);1168 1169 i915_restore_display(dev_priv);1170 intel_pps_unlock_regs_wa(display);1171 1172 intel_init_pch_refclk(dev_priv);1173 1174 /*1175 * Interrupts have to be enabled before any batches are run. If not the1176 * GPU will hang. i915_gem_init_hw() will initiate batches to1177 * update/restore the context.1178 *1179 * drm_mode_config_reset() needs AUX interrupts.1180 *1181 * Modeset enabling in intel_display_driver_init_hw() also needs working1182 * interrupts.1183 */1184 intel_runtime_pm_enable_interrupts(dev_priv);1185 1186 if (HAS_DISPLAY(dev_priv))1187 drm_mode_config_reset(dev);1188 1189 i915_gem_resume(dev_priv);1190 1191 intel_display_driver_init_hw(dev_priv);1192 1193 intel_clock_gating_init(dev_priv);1194 1195 if (HAS_DISPLAY(dev_priv))1196 intel_display_driver_resume_access(dev_priv);1197 1198 intel_hpd_init(dev_priv);1199 1200 /* MST sideband requires HPD interrupts enabled */1201 intel_dp_mst_resume(dev_priv);1202 intel_display_driver_resume(dev_priv);1203 1204 if (HAS_DISPLAY(dev_priv)) {1205 intel_display_driver_enable_user_access(dev_priv);1206 drm_kms_helper_poll_enable(dev);1207 }1208 intel_hpd_poll_disable(dev_priv);1209 1210 intel_opregion_resume(display);1211 1212 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);1213 1214 intel_power_domains_enable(dev_priv);1215 1216 intel_gvt_resume(dev_priv);1217 1218 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1219 1220 return 0;1221}1222 1223static int i915_drm_resume_early(struct drm_device *dev)1224{1225 struct drm_i915_private *dev_priv = to_i915(dev);1226 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);1227 struct intel_gt *gt;1228 int ret, i;1229 1230 /*1231 * We have a resume ordering issue with the snd-hda driver also1232 * requiring our device to be power up. Due to the lack of a1233 * parent/child relationship we currently solve this with an early1234 * resume hook.1235 *1236 * FIXME: This should be solved with a special hdmi sink device or1237 * similar so that power domains can be employed.1238 */1239 1240 /*1241 * Note that we need to set the power state explicitly, since we1242 * powered off the device during freeze and the PCI core won't power1243 * it back up for us during thaw. Powering off the device during1244 * freeze is not a hard requirement though, and during the1245 * suspend/resume phases the PCI core makes sure we get here with the1246 * device powered on. So in case we change our freeze logic and keep1247 * the device powered we can also remove the following set power state1248 * call.1249 */1250 ret = pci_set_power_state(pdev, PCI_D0);1251 if (ret) {1252 drm_err(&dev_priv->drm,1253 "failed to set PCI D0 power state (%d)\n", ret);1254 return ret;1255 }1256 1257 /*1258 * Note that pci_enable_device() first enables any parent bridge1259 * device and only then sets the power state for this device. The1260 * bridge enabling is a nop though, since bridge devices are resumed1261 * first. The order of enabling power and enabling the device is1262 * imposed by the PCI core as described above, so here we preserve the1263 * same order for the freeze/thaw phases.1264 *1265 * TODO: eventually we should remove pci_disable_device() /1266 * pci_enable_enable_device() from suspend/resume. Due to how they1267 * depend on the device enable refcount we can't anyway depend on them1268 * disabling/enabling the device.1269 */1270 if (pci_enable_device(pdev))1271 return -EIO;1272 1273 pci_set_master(pdev);1274 1275 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1276 1277 ret = vlv_resume_prepare(dev_priv, false);1278 if (ret)1279 drm_err(&dev_priv->drm,1280 "Resume prepare failed: %d, continuing anyway\n", ret);1281 1282 for_each_gt(gt, dev_priv, i)1283 intel_gt_resume_early(gt);1284 1285 intel_display_power_resume_early(dev_priv);1286 1287 intel_power_domains_resume(dev_priv);1288 1289 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);1290 1291 return ret;1292}1293 1294int i915_driver_resume_switcheroo(struct drm_i915_private *i915)1295{1296 int ret;1297 1298 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1299 return 0;1300 1301 ret = i915_drm_resume_early(&i915->drm);1302 if (ret)1303 return ret;1304 1305 return i915_drm_resume(&i915->drm);1306}1307 1308static int i915_pm_prepare(struct device *kdev)1309{1310 struct drm_i915_private *i915 = kdev_to_i915(kdev);1311 1312 if (!i915) {1313 dev_err(kdev, "DRM not initialized, aborting suspend.\n");1314 return -ENODEV;1315 }1316 1317 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1318 return 0;1319 1320 return i915_drm_prepare(&i915->drm);1321}1322 1323static int i915_pm_suspend(struct device *kdev)1324{1325 struct drm_i915_private *i915 = kdev_to_i915(kdev);1326 1327 if (!i915) {1328 dev_err(kdev, "DRM not initialized, aborting suspend.\n");1329 return -ENODEV;1330 }1331 1332 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1333 return 0;1334 1335 return i915_drm_suspend(&i915->drm);1336}1337 1338static int i915_pm_suspend_late(struct device *kdev)1339{1340 struct drm_i915_private *i915 = kdev_to_i915(kdev);1341 1342 /*1343 * We have a suspend ordering issue with the snd-hda driver also1344 * requiring our device to be power up. Due to the lack of a1345 * parent/child relationship we currently solve this with an late1346 * suspend hook.1347 *1348 * FIXME: This should be solved with a special hdmi sink device or1349 * similar so that power domains can be employed.1350 */1351 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1352 return 0;1353 1354 return i915_drm_suspend_late(&i915->drm, false);1355}1356 1357static int i915_pm_poweroff_late(struct device *kdev)1358{1359 struct drm_i915_private *i915 = kdev_to_i915(kdev);1360 1361 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1362 return 0;1363 1364 return i915_drm_suspend_late(&i915->drm, true);1365}1366 1367static int i915_pm_resume_early(struct device *kdev)1368{1369 struct drm_i915_private *i915 = kdev_to_i915(kdev);1370 1371 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1372 return 0;1373 1374 return i915_drm_resume_early(&i915->drm);1375}1376 1377static int i915_pm_resume(struct device *kdev)1378{1379 struct drm_i915_private *i915 = kdev_to_i915(kdev);1380 1381 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1382 return 0;1383 1384 return i915_drm_resume(&i915->drm);1385}1386 1387static void i915_pm_complete(struct device *kdev)1388{1389 struct drm_i915_private *i915 = kdev_to_i915(kdev);1390 1391 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)1392 return;1393 1394 i915_drm_complete(&i915->drm);1395}1396 1397/* freeze: before creating the hibernation_image */1398static int i915_pm_freeze(struct device *kdev)1399{1400 struct drm_i915_private *i915 = kdev_to_i915(kdev);1401 int ret;1402 1403 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {1404 ret = i915_drm_suspend(&i915->drm);1405 if (ret)1406 return ret;1407 }1408 1409 ret = i915_gem_freeze(i915);1410 if (ret)1411 return ret;1412 1413 return 0;1414}1415 1416static int i915_pm_freeze_late(struct device *kdev)1417{1418 struct drm_i915_private *i915 = kdev_to_i915(kdev);1419 int ret;1420 1421 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {1422 ret = i915_drm_suspend_late(&i915->drm, true);1423 if (ret)1424 return ret;1425 }1426 1427 ret = i915_gem_freeze_late(i915);1428 if (ret)1429 return ret;1430 1431 return 0;1432}1433 1434/* thaw: called after creating the hibernation image, but before turning off. */1435static int i915_pm_thaw_early(struct device *kdev)1436{1437 return i915_pm_resume_early(kdev);1438}1439 1440static int i915_pm_thaw(struct device *kdev)1441{1442 return i915_pm_resume(kdev);1443}1444 1445/* restore: called after loading the hibernation image. */1446static int i915_pm_restore_early(struct device *kdev)1447{1448 return i915_pm_resume_early(kdev);1449}1450 1451static int i915_pm_restore(struct device *kdev)1452{1453 return i915_pm_resume(kdev);1454}1455 1456static int intel_runtime_suspend(struct device *kdev)1457{1458 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);1459 struct intel_display *display = &dev_priv->display;1460 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;1461 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);1462 struct pci_dev *root_pdev;1463 struct intel_gt *gt;1464 int ret, i;1465 1466 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))1467 return -ENODEV;1468 1469 drm_dbg(&dev_priv->drm, "Suspending device\n");1470 1471 disable_rpm_wakeref_asserts(rpm);1472 1473 /*1474 * We are safe here against re-faults, since the fault handler takes1475 * an RPM reference.1476 */1477 i915_gem_runtime_suspend(dev_priv);1478 1479 intel_pxp_runtime_suspend(dev_priv->pxp);1480 1481 for_each_gt(gt, dev_priv, i)1482 intel_gt_runtime_suspend(gt);1483 1484 intel_runtime_pm_disable_interrupts(dev_priv);1485 1486 for_each_gt(gt, dev_priv, i)1487 intel_uncore_suspend(gt->uncore);1488 1489 intel_display_power_suspend(dev_priv);1490 1491 ret = vlv_suspend_complete(dev_priv);1492 if (ret) {1493 drm_err(&dev_priv->drm,1494 "Runtime suspend failed, disabling it (%d)\n", ret);1495 intel_uncore_runtime_resume(&dev_priv->uncore);1496 1497 intel_runtime_pm_enable_interrupts(dev_priv);1498 1499 for_each_gt(gt, dev_priv, i)1500 intel_gt_runtime_resume(gt);1501 1502 enable_rpm_wakeref_asserts(rpm);1503 1504 return ret;1505 }1506 1507 enable_rpm_wakeref_asserts(rpm);1508 intel_runtime_pm_driver_release(rpm);1509 1510 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))1511 drm_err(&dev_priv->drm,1512 "Unclaimed access detected prior to suspending\n");1513 1514 /*1515 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX1516 * This should be totally removed when we handle the pci states properly1517 * on runtime PM.1518 */1519 root_pdev = pcie_find_root_port(pdev);1520 if (root_pdev)1521 pci_d3cold_disable(root_pdev);1522 1523 /*1524 * FIXME: We really should find a document that references the arguments1525 * used below!1526 */1527 if (IS_BROADWELL(dev_priv)) {1528 /*1529 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop1530 * being detected, and the call we do at intel_runtime_resume()1531 * won't be able to restore them. Since PCI_D3hot matches the1532 * actual specification and appears to be working, use it.1533 */1534 intel_opregion_notify_adapter(display, PCI_D3hot);1535 } else {1536 /*1537 * current versions of firmware which depend on this opregion1538 * notification have repurposed the D1 definition to mean1539 * "runtime suspended" vs. what you would normally expect (D3)1540 * to distinguish it from notifications that might be sent via1541 * the suspend path.1542 */1543 intel_opregion_notify_adapter(display, PCI_D1);1544 }1545 1546 assert_forcewakes_inactive(&dev_priv->uncore);1547 1548 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))1549 intel_hpd_poll_enable(dev_priv);1550 1551 drm_dbg(&dev_priv->drm, "Device suspended\n");1552 return 0;1553}1554 1555static int intel_runtime_resume(struct device *kdev)1556{1557 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);1558 struct intel_display *display = &dev_priv->display;1559 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;1560 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);1561 struct pci_dev *root_pdev;1562 struct intel_gt *gt;1563 int ret, i;1564 1565 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))1566 return -ENODEV;1567 1568 drm_dbg(&dev_priv->drm, "Resuming device\n");1569 1570 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));1571 disable_rpm_wakeref_asserts(rpm);1572 1573 intel_opregion_notify_adapter(display, PCI_D0);1574 1575 root_pdev = pcie_find_root_port(pdev);1576 if (root_pdev)1577 pci_d3cold_enable(root_pdev);1578 1579 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))1580 drm_dbg(&dev_priv->drm,1581 "Unclaimed access during suspend, bios?\n");1582 1583 intel_display_power_resume(dev_priv);1584 1585 ret = vlv_resume_prepare(dev_priv, true);1586 1587 for_each_gt(gt, dev_priv, i)1588 intel_uncore_runtime_resume(gt->uncore);1589 1590 intel_runtime_pm_enable_interrupts(dev_priv);1591 1592 /*1593 * No point of rolling back things in case of an error, as the best1594 * we can do is to hope that things will still work (and disable RPM).1595 */1596 for_each_gt(gt, dev_priv, i)1597 intel_gt_runtime_resume(gt);1598 1599 intel_pxp_runtime_resume(dev_priv->pxp);1600 1601 /*1602 * On VLV/CHV display interrupts are part of the display1603 * power well, so hpd is reinitialized from there. For1604 * everyone else do it here.1605 */1606 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {1607 intel_hpd_init(dev_priv);1608 intel_hpd_poll_disable(dev_priv);1609 }1610 1611 skl_watermark_ipc_update(dev_priv);1612 1613 enable_rpm_wakeref_asserts(rpm);1614 1615 if (ret)1616 drm_err(&dev_priv->drm,1617 "Runtime resume failed, disabling it (%d)\n", ret);1618 else1619 drm_dbg(&dev_priv->drm, "Device resumed\n");1620 1621 return ret;1622}1623 1624const struct dev_pm_ops i915_pm_ops = {1625 /*1626 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,1627 * PMSG_RESUME]1628 */1629 .prepare = i915_pm_prepare,1630 .suspend = i915_pm_suspend,1631 .suspend_late = i915_pm_suspend_late,1632 .resume_early = i915_pm_resume_early,1633 .resume = i915_pm_resume,1634 .complete = i915_pm_complete,1635 1636 /*1637 * S4 event handlers1638 * @freeze, @freeze_late : called (1) before creating the1639 * hibernation image [PMSG_FREEZE] and1640 * (2) after rebooting, before restoring1641 * the image [PMSG_QUIESCE]1642 * @thaw, @thaw_early : called (1) after creating the hibernation1643 * image, before writing it [PMSG_THAW]1644 * and (2) after failing to create or1645 * restore the image [PMSG_RECOVER]1646 * @poweroff, @poweroff_late: called after writing the hibernation1647 * image, before rebooting [PMSG_HIBERNATE]1648 * @restore, @restore_early : called after rebooting and restoring the1649 * hibernation image [PMSG_RESTORE]1650 */1651 .freeze = i915_pm_freeze,1652 .freeze_late = i915_pm_freeze_late,1653 .thaw_early = i915_pm_thaw_early,1654 .thaw = i915_pm_thaw,1655 .poweroff = i915_pm_suspend,1656 .poweroff_late = i915_pm_poweroff_late,1657 .restore_early = i915_pm_restore_early,1658 .restore = i915_pm_restore,1659 1660 /* S0ix (via runtime suspend) event handlers */1661 .runtime_suspend = intel_runtime_suspend,1662 .runtime_resume = intel_runtime_resume,1663};1664 1665static const struct file_operations i915_driver_fops = {1666 .owner = THIS_MODULE,1667 .open = drm_open,1668 .release = drm_release_noglobal,1669 .unlocked_ioctl = drm_ioctl,1670 .mmap = i915_gem_mmap,1671 .poll = drm_poll,1672 .read = drm_read,1673 .compat_ioctl = i915_ioc32_compat_ioctl,1674 .llseek = noop_llseek,1675#ifdef CONFIG_PROC_FS1676 .show_fdinfo = drm_show_fdinfo,1677#endif1678 .fop_flags = FOP_UNSIGNED_OFFSET,1679};1680 1681static int1682i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,1683 struct drm_file *file)1684{1685 return -ENODEV;1686}1687 1688static const struct drm_ioctl_desc i915_ioctls[] = {1689 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1690 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),1691 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),1692 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),1693 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),1694 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),1695 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),1696 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1697 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),1698 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),1699 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1700 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),1701 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1702 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1703 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),1704 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),1705 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1706 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1707 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),1708 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),1709 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),1710 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),1711 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),1712 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),1713 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),1714 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),1715 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1716 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),1717 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),1718 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),1719 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),1720 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),1721 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),1722 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),1723 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),1724 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),1725 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),1726 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),1727 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),1728 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),1729 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),1730 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),1731 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),1732 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),1733 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),1734 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),1735 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),1736 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),1737 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),1738 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),1739 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),1740 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),1741 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),1742 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),1743 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),1744 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),1745 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),1746 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),1747 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),1748};1749 1750/*1751 * Interface history:1752 *1753 * 1.1: Original.1754 * 1.2: Add Power Management1755 * 1.3: Add vblank support1756 * 1.4: Fix cmdbuffer path, add heap destroy1757 * 1.5: Add vblank pipe configuration1758 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank1759 * - Support vertical blank on secondary display pipe1760 */1761#define DRIVER_MAJOR 11762#define DRIVER_MINOR 61763#define DRIVER_PATCHLEVEL 01764 1765static const struct drm_driver i915_drm_driver = {1766 /* Don't use MTRRs here; the Xserver or userspace app should1767 * deal with them for Intel hardware.1768 */1769 .driver_features =1770 DRIVER_GEM |1771 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |1772 DRIVER_SYNCOBJ_TIMELINE,1773 .release = i915_driver_release,1774 .open = i915_driver_open,1775 .postclose = i915_driver_postclose,1776 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),1777 1778 .gem_prime_import = i915_gem_prime_import,1779 1780 .dumb_create = i915_gem_dumb_create,1781 .dumb_map_offset = i915_gem_dumb_mmap_offset,1782 1783 .ioctls = i915_ioctls,1784 .num_ioctls = ARRAY_SIZE(i915_ioctls),1785 .fops = &i915_driver_fops,1786 .name = DRIVER_NAME,1787 .desc = DRIVER_DESC,1788 .date = DRIVER_DATE,1789 .major = DRIVER_MAJOR,1790 .minor = DRIVER_MINOR,1791 .patchlevel = DRIVER_PATCHLEVEL,1792};1793