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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-2 */3/*4 *5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.6 * All Rights Reserved.7 *8 * Permission is hereby granted, free of charge, to any person obtaining a9 * copy of this software and associated documentation files (the10 * "Software"), to deal in the Software without restriction, including11 * without limitation the rights to use, copy, modify, merge, publish,12 * distribute, sub license, and/or sell copies of the Software, and to13 * permit persons to whom the Software is furnished to do so, subject to14 * the following conditions:15 *16 * The above copyright notice and this permission notice (including the17 * next paragraph) shall be included in all copies or substantial portions18 * of the Software.19 *20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.27 *28 */29 30#ifndef _I915_DRV_H_31#define _I915_DRV_H_32 33#include <uapi/drm/i915_drm.h>34 35#include <linux/pm_qos.h>36 37#include <drm/ttm/ttm_device.h>38 39#include "display/intel_display_limits.h"40#include "display/intel_display_core.h"41 42#include "gem/i915_gem_context_types.h"43#include "gem/i915_gem_shrinker.h"44#include "gem/i915_gem_stolen.h"45 46#include "gt/intel_engine.h"47#include "gt/intel_gt_types.h"48#include "gt/intel_region_lmem.h"49#include "gt/intel_workarounds.h"50#include "gt/uc/intel_uc.h"51 52#include "soc/intel_pch.h"53 54#include "i915_drm_client.h"55#include "i915_gem.h"56#include "i915_gpu_error.h"57#include "i915_params.h"58#include "i915_perf_types.h"59#include "i915_scheduler.h"60#include "i915_utils.h"61#include "intel_device_info.h"62#include "intel_memory_region.h"63#include "intel_runtime_pm.h"64#include "intel_step.h"65#include "intel_uncore.h"66 67struct drm_i915_clock_gating_funcs;68struct vlv_s0ix_state;69struct intel_pxp;70 71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)72 73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */74struct i915_dsm {75 /*76 * The start and end of DSM which we can optionally use to create GEM77 * objects backed by stolen memory.78 *79 * Note that usable_size tells us exactly how much of this we are80 * actually allowed to use, given that some portion of it is in fact81 * reserved for use by hardware functions.82 */83 struct resource stolen;84 85 /*86 * Reserved portion of DSM.87 */88 struct resource reserved;89 90 /*91 * Total size minus reserved ranges.92 *93 * DSM is segmented in hardware with different portions offlimits to94 * certain functions.95 *96 * The drm_mm is initialised to the total accessible range, as found97 * from the PCI config. On Broadwell+, this is further restricted to98 * avoid the first page! The upper end of DSM is reserved for hardware99 * functions and similarly removed from the accessible range.100 */101 resource_size_t usable_size;102};103 104struct i915_suspend_saved_registers {105 u32 saveDSPARB;106 u32 saveSWF0[16];107 u32 saveSWF1[16];108 u32 saveSWF3[3];109 u16 saveGCDGMBUS;110};111 112#define MAX_L3_SLICES 2113struct intel_l3_parity {114 u32 *remap_info[MAX_L3_SLICES];115 struct work_struct error_work;116 int which_slice;117};118 119struct i915_gem_mm {120 /*121 * Shortcut for the stolen region. This points to either122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't124 * support stolen.125 */126 struct intel_memory_region *stolen_region;127 /** Memory allocator for GTT stolen memory */128 struct drm_mm stolen;129 /** Protects the usage of the GTT stolen memory allocator. This is130 * always the inner lock when overlapping with struct_mutex. */131 struct mutex stolen_lock;132 133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */134 spinlock_t obj_lock;135 136 /**137 * List of objects which are purgeable.138 */139 struct list_head purge_list;140 141 /**142 * List of objects which have allocated pages and are shrinkable.143 */144 struct list_head shrink_list;145 146 /**147 * List of objects which are pending destruction.148 */149 struct llist_head free_list;150 struct work_struct free_work;151 /**152 * Count of objects pending destructions. Used to skip needlessly153 * waiting on an RCU barrier if no objects are waiting to be freed.154 */155 atomic_t free_count;156 157 /**158 * tmpfs instance used for shmem backed objects159 */160 struct vfsmount *gemfs;161 162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];163 164 struct notifier_block oom_notifier;165 struct notifier_block vmap_notifier;166 struct shrinker *shrinker;167 168 /* shrinker accounting, also useful for userland debugging */169 u64 shrink_memory;170 u32 shrink_count;171};172 173struct i915_virtual_gpu {174 struct mutex lock; /* serialises sending of g2v_notify command pkts */175 bool active;176 u32 caps;177 u32 *initial_mmio;178 u8 *initial_cfg_space;179 struct list_head entry;180};181 182struct i915_selftest_stash {183 atomic_t counter;184 struct ida mock_region_instances;185};186 187struct drm_i915_private {188 struct drm_device drm;189 190 struct intel_display display;191 192 /* FIXME: Device release actions should all be moved to drmm_ */193 bool do_release;194 195 /* i915 device parameters */196 struct i915_params params;197 198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */200 struct intel_driver_caps caps;201 202 struct i915_dsm dsm;203 204 struct intel_uncore uncore;205 struct intel_uncore_mmio_debug mmio_debug;206 207 struct i915_virtual_gpu vgpu;208 209 struct intel_gvt *gvt;210 211 struct {212 struct pci_dev *pdev;213 struct resource mch_res;214 bool mchbar_need_disable;215 } gmch;216 217 /*218 * Chaining user engines happens in multiple stages, starting with a219 * simple lock-less linked list created by intel_engine_add_user(),220 * which later gets sorted and converted to an intermediate regular221 * list, just to be converted once again to its final rb tree structure222 * in intel_engines_driver_register().223 *224 * Make sure to use the right iterator helper, depending on if the code225 * in question runs before or after intel_engines_driver_register() --226 * for_each_uabi_engine() can only be used afterwards!227 */228 union {229 struct llist_head uabi_engines_llist;230 struct list_head uabi_engines_list;231 struct rb_root uabi_engines;232 };233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];234 235 /* protects the irq masks */236 spinlock_t irq_lock;237 238 /* Sideband mailbox protection */239 struct mutex sb_lock;240 struct pm_qos_request sb_qos;241 242 /** Cached value of IMR to avoid reads in updating the bitfield */243 u32 irq_mask;244 245 bool preserve_bios_swizzle;246 247 unsigned int fsb_freq, mem_freq, is_ddr3;248 249 unsigned int hpll_freq;250 unsigned int czclk_freq;251 252 /**253 * wq - Driver workqueue for GEM.254 *255 * NOTE: Work items scheduled here are not allowed to grab any modeset256 * locks, for otherwise the flushing done in the pageflip code will257 * result in deadlocks.258 */259 struct workqueue_struct *wq;260 261 /**262 * unordered_wq - internal workqueue for unordered work263 *264 * This workqueue should be used for all unordered work265 * scheduling within i915, which used to be scheduled on the266 * system_wq before moving to a driver instance due267 * deprecation of flush_scheduled_work().268 */269 struct workqueue_struct *unordered_wq;270 271 /* pm private clock gating functions */272 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;273 274 /* PCH chipset type */275 enum intel_pch pch_type;276 unsigned short pch_id;277 278 unsigned long gem_quirks;279 280 struct i915_gem_mm mm;281 282 struct intel_l3_parity l3_parity;283 284 /*285 * edram size in MB.286 * Cannot be determined by PCIID. You must always read a register.287 */288 u32 edram_size_mb;289 290 struct i915_gpu_error gpu_error;291 292 u32 suspend_count;293 struct i915_suspend_saved_registers regfile;294 struct vlv_s0ix_state *vlv_s0ix_state;295 296 struct dram_info {297 bool wm_lv_0_adjust_needed;298 u8 num_channels;299 bool symmetric_memory;300 enum intel_dram_type {301 INTEL_DRAM_UNKNOWN,302 INTEL_DRAM_DDR3,303 INTEL_DRAM_DDR4,304 INTEL_DRAM_LPDDR3,305 INTEL_DRAM_LPDDR4,306 INTEL_DRAM_DDR5,307 INTEL_DRAM_LPDDR5,308 INTEL_DRAM_GDDR,309 } type;310 u8 num_qgv_points;311 u8 num_psf_gv_points;312 } dram_info;313 314 struct intel_runtime_pm runtime_pm;315 316 struct i915_perf perf;317 318 struct i915_hwmon *hwmon;319 320 struct intel_gt *gt[I915_MAX_GT];321 322 struct kobject *sysfs_gt;323 324 /* Quick lookup of media GT (current platforms only have one) */325 struct intel_gt *media_gt;326 327 struct {328 struct i915_gem_contexts {329 spinlock_t lock; /* locks list */330 struct list_head list;331 } contexts;332 333 /*334 * We replace the local file with a global mappings as the335 * backing storage for the mmap is on the device and not336 * on the struct file, and we do not want to prolong the337 * lifetime of the local fd. To minimise the number of338 * anonymous inodes we create, we use a global singleton to339 * share the global mapping.340 */341 struct file *mmap_singleton;342 } gem;343 344 struct intel_pxp *pxp;345 346 bool irq_enabled;347 348 struct i915_pmu pmu;349 350 /* The TTM device structure. */351 struct ttm_device bdev;352 353 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)354 355 /*356 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch357 * will be rejected. Instead look for a better place.358 */359};360 361static inline struct drm_i915_private *to_i915(const struct drm_device *dev)362{363 return container_of(dev, struct drm_i915_private, drm);364}365 366static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)367{368 struct drm_device *drm = dev_get_drvdata(kdev);369 370 return drm ? to_i915(drm) : NULL;371}372 373static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)374{375 struct drm_device *drm = pci_get_drvdata(pdev);376 377 return drm ? to_i915(drm) : NULL;378}379 380static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)381{382 return i915->gt[0];383}384 385#define rb_to_uabi_engine(rb) \386 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)387 388#define for_each_uabi_engine(engine__, i915__) \389 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\390 (engine__); \391 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))392 393#define INTEL_INFO(i915) ((i915)->__info)394#define RUNTIME_INFO(i915) (&(i915)->__runtime)395#define DRIVER_CAPS(i915) (&(i915)->caps)396 397#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)398 399#define IP_VER(ver, rel) ((ver) << 8 | (rel))400 401#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)402#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \403 RUNTIME_INFO(i915)->graphics.ip.rel)404#define IS_GRAPHICS_VER(i915, from, until) \405 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))406 407#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)408#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \409 RUNTIME_INFO(i915)->media.ip.rel)410#define IS_MEDIA_VER(i915, from, until) \411 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))412 413#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)414 415#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)416#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)417 418#define IS_GRAPHICS_STEP(__i915, since, until) \419 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \420 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))421 422#define IS_MEDIA_STEP(__i915, since, until) \423 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \424 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))425 426static __always_inline unsigned int427__platform_mask_index(const struct intel_runtime_info *info,428 enum intel_platform p)429{430 const unsigned int pbits =431 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;432 433 /* Expand the platform_mask array if this fails. */434 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >435 pbits * ARRAY_SIZE(info->platform_mask));436 437 return p / pbits;438}439 440static __always_inline unsigned int441__platform_mask_bit(const struct intel_runtime_info *info,442 enum intel_platform p)443{444 const unsigned int pbits =445 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;446 447 return p % pbits + INTEL_SUBPLATFORM_BITS;448}449 450static inline u32451intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)452{453 const unsigned int pi = __platform_mask_index(info, p);454 455 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;456}457 458static __always_inline bool459IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)460{461 const struct intel_runtime_info *info = RUNTIME_INFO(i915);462 const unsigned int pi = __platform_mask_index(info, p);463 const unsigned int pb = __platform_mask_bit(info, p);464 465 BUILD_BUG_ON(!__builtin_constant_p(p));466 467 return info->platform_mask[pi] & BIT(pb);468}469 470static __always_inline bool471IS_SUBPLATFORM(const struct drm_i915_private *i915,472 enum intel_platform p, unsigned int s)473{474 const struct intel_runtime_info *info = RUNTIME_INFO(i915);475 const unsigned int pi = __platform_mask_index(info, p);476 const unsigned int pb = __platform_mask_bit(info, p);477 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;478 const u32 mask = info->platform_mask[pi];479 480 BUILD_BUG_ON(!__builtin_constant_p(p));481 BUILD_BUG_ON(!__builtin_constant_p(s));482 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);483 484 /* Shift and test on the MSB position so sign flag can be used. */485 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);486}487 488#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)489#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)490 491#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)492#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)493#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)494#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)495#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)496#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)497#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)498#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)499#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)500#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)501#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)502#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)503#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))504#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)505#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)506#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)507#define IS_IRONLAKE_M(i915) \508 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))509#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)510#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)511#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \512 INTEL_INFO(i915)->gt == 1)513#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)514#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)515#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)516#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)517#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)518#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)519#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)520#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)521#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)522#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)523#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)524#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)525#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)526#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)527#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)528#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)529#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)530#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)531#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)532#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)533/*534 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,535 * so we need to define these even on platforms that the i915 base driver536 * doesn't support. Ensure the parameter is used in the definition to537 * avoid 'unused variable' warnings when compiling the shared display code538 * for i915.539 */540#define IS_LUNARLAKE(i915) (0 && i915)541#define IS_BATTLEMAGE(i915) (0 && i915)542 543#define IS_ARROWLAKE_H(i915) \544 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)545#define IS_ARROWLAKE_U(i915) \546 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)547#define IS_ARROWLAKE_S(i915) \548 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)549#define IS_DG2_G10(i915) \550 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)551#define IS_DG2_G11(i915) \552 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)553#define IS_DG2_G12(i915) \554 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)555#define IS_RAPTORLAKE_S(i915) \556 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)557#define IS_ALDERLAKE_P_N(i915) \558 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)559#define IS_RAPTORLAKE_P(i915) \560 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)561#define IS_RAPTORLAKE_U(i915) \562 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)563#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \564 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)565#define IS_BROADWELL_ULT(i915) \566 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)567#define IS_BROADWELL_ULX(i915) \568 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)569#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \570 INTEL_INFO(i915)->gt == 3)571#define IS_HASWELL_ULT(i915) \572 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)573#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \574 INTEL_INFO(i915)->gt == 3)575#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \576 INTEL_INFO(i915)->gt == 1)577/* ULX machines are also considered ULT. */578#define IS_HASWELL_ULX(i915) \579 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)580#define IS_SKYLAKE_ULT(i915) \581 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)582#define IS_SKYLAKE_ULX(i915) \583 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)584#define IS_KABYLAKE_ULT(i915) \585 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)586#define IS_KABYLAKE_ULX(i915) \587 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)588#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \589 INTEL_INFO(i915)->gt == 2)590#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \591 INTEL_INFO(i915)->gt == 3)592#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \593 INTEL_INFO(i915)->gt == 4)594#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \595 INTEL_INFO(i915)->gt == 2)596#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \597 INTEL_INFO(i915)->gt == 3)598#define IS_COFFEELAKE_ULT(i915) \599 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)600#define IS_COFFEELAKE_ULX(i915) \601 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)602#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \603 INTEL_INFO(i915)->gt == 2)604#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \605 INTEL_INFO(i915)->gt == 3)606 607#define IS_COMETLAKE_ULT(i915) \608 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)609#define IS_COMETLAKE_ULX(i915) \610 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)611#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \612 INTEL_INFO(i915)->gt == 2)613 614#define IS_ICL_WITH_PORT_F(i915) \615 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)616 617#define IS_TIGERLAKE_UY(i915) \618 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)619 620#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)621#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))622#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))623 624#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))625#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)626 627#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \628 unsigned int first__ = (first); \629 unsigned int count__ = (count); \630 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \631})632 633#define ENGINE_INSTANCES_MASK(gt, first, count) \634 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)635 636#define RCS_MASK(gt) \637 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)638#define BCS_MASK(gt) \639 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)640#define VDBOX_MASK(gt) \641 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)642#define VEBOX_MASK(gt) \643 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)644#define CCS_MASK(gt) \645 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)646 647#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)648 649/*650 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution651 * All later gens can run the final buffer from the ppgtt652 */653#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)654 655#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)656#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)657#define HAS_EDRAM(i915) ((i915)->edram_size_mb)658#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)659#define HAS_WT(i915) HAS_EDRAM(i915)660 661#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)662 663#define HAS_LOGICAL_RING_CONTEXTS(i915) \664 (INTEL_INFO(i915)->has_logical_ring_contexts)665#define HAS_LOGICAL_RING_ELSQ(i915) \666 (INTEL_INFO(i915)->has_logical_ring_elsq)667 668#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)669 670#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)671#define HAS_PPGTT(i915) \672 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)673#define HAS_FULL_PPGTT(i915) \674 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)675 676#define HAS_PAGE_SIZES(i915, sizes) ({ \677 GEM_BUG_ON((sizes) == 0); \678 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \679})680 681#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \682 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)683 684/* WaRsDisableCoarsePowerGating:skl,cnl */685#define NEEDS_WaRsDisableCoarsePowerGating(i915) \686 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))687 688/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte689 * rows, which changed the alignment requirements and fence programming.690 */691#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \692 !(IS_I915G(i915) || IS_I915GM(i915)))693 694#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)695#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)696#define HAS_RC6pp(i915) (false) /* HW was never validated */697 698#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)699 700#define HAS_HECI_PXP(i915) \701 (INTEL_INFO(i915)->has_heci_pxp)702 703#define HAS_HECI_GSCFI(i915) \704 (INTEL_INFO(i915)->has_heci_gscfi)705 706#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))707 708#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)709#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)710 711#define HAS_OA_BPC_REPORTING(i915) \712 (INTEL_INFO(i915)->has_oa_bpc_reporting)713#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \714 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)715#define HAS_OAM(i915) \716 (INTEL_INFO(i915)->has_oam)717 718/*719 * Set this flag, when platform requires 64K GTT page sizes or larger for720 * device local memory access.721 */722#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)723 724#define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))725#define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0)726 727#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)728 729/*730 * Platform has the dedicated compression control state for each lmem surfaces731 * stored in lmem to support the 3D and media compression formats.732 */733#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)734 735#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)736 737#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)738 739#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)740 741#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)742 743#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)744 745/* DPF == dynamic parity feature */746#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)747#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \748 2 : HAS_L3_DPF(i915))749 750#define HAS_GUC_DEPRIVILEGE(i915) \751 (INTEL_INFO(i915)->has_guc_deprivilege)752 753#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)754 755#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)756 757#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)758 759#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \760 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))761 762#endif763