208 lines · c
1/*2 * SPDX-License-Identifier: MIT3 */4 5#include "gem/i915_gem_mman.h"6#include "gt/intel_engine_user.h"7 8#include "pxp/intel_pxp.h"9 10#include "i915_cmd_parser.h"11#include "i915_drv.h"12#include "i915_getparam.h"13#include "i915_perf.h"14 15int i915_getparam_ioctl(struct drm_device *dev, void *data,16 struct drm_file *file_priv)17{18 struct drm_i915_private *i915 = to_i915(dev);19 struct pci_dev *pdev = to_pci_dev(dev->dev);20 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;21 drm_i915_getparam_t *param = data;22 int value = 0;23 24 switch (param->param) {25 case I915_PARAM_IRQ_ACTIVE:26 case I915_PARAM_ALLOW_BATCHBUFFER:27 case I915_PARAM_LAST_DISPATCH:28 case I915_PARAM_HAS_EXEC_CONSTANTS:29 /* Reject all old ums/dri params. */30 return -ENODEV;31 case I915_PARAM_CHIPSET_ID:32 value = pdev->device;33 break;34 case I915_PARAM_REVISION:35 value = pdev->revision;36 break;37 case I915_PARAM_NUM_FENCES_AVAIL:38 value = to_gt(i915)->ggtt->num_fences;39 break;40 case I915_PARAM_HAS_OVERLAY:41 value = !!i915->display.overlay;42 break;43 case I915_PARAM_HAS_BSD:44 value = !!intel_engine_lookup_user(i915,45 I915_ENGINE_CLASS_VIDEO, 0);46 break;47 case I915_PARAM_HAS_BLT:48 value = !!intel_engine_lookup_user(i915,49 I915_ENGINE_CLASS_COPY, 0);50 break;51 case I915_PARAM_HAS_VEBOX:52 value = !!intel_engine_lookup_user(i915,53 I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);54 break;55 case I915_PARAM_HAS_BSD2:56 value = !!intel_engine_lookup_user(i915,57 I915_ENGINE_CLASS_VIDEO, 1);58 break;59 case I915_PARAM_HAS_LLC:60 value = HAS_LLC(i915);61 break;62 case I915_PARAM_HAS_WT:63 value = HAS_WT(i915);64 break;65 case I915_PARAM_HAS_ALIASING_PPGTT:66 value = INTEL_PPGTT(i915);67 break;68 case I915_PARAM_HAS_SEMAPHORES:69 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);70 break;71 case I915_PARAM_HAS_SECURE_BATCHES:72 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);73 break;74 case I915_PARAM_CMD_PARSER_VERSION:75 value = i915_cmd_parser_get_version(i915);76 break;77 case I915_PARAM_SUBSLICE_TOTAL:78 value = intel_sseu_subslice_total(sseu);79 if (!value)80 return -ENODEV;81 break;82 case I915_PARAM_EU_TOTAL:83 value = sseu->eu_total;84 if (!value)85 return -ENODEV;86 break;87 case I915_PARAM_HAS_GPU_RESET:88 value = i915->params.enable_hangcheck &&89 intel_has_gpu_reset(to_gt(i915));90 if (value && intel_has_reset_engine(to_gt(i915)))91 value = 2;92 break;93 case I915_PARAM_HAS_RESOURCE_STREAMER:94 value = 0;95 break;96 case I915_PARAM_HAS_POOLED_EU:97 value = HAS_POOLED_EU(i915);98 break;99 case I915_PARAM_MIN_EU_IN_POOL:100 value = sseu->min_eu_in_pool;101 break;102 case I915_PARAM_HUC_STATUS:103 /* On platform with a media GT, the HuC is on that GT */104 if (i915->media_gt)105 value = intel_huc_check_status(&i915->media_gt->uc.huc);106 else107 value = intel_huc_check_status(&to_gt(i915)->uc.huc);108 if (value < 0)109 return value;110 break;111 case I915_PARAM_PXP_STATUS:112 value = intel_pxp_get_readiness_status(i915->pxp, 0);113 if (value < 0)114 return value;115 break;116 case I915_PARAM_MMAP_GTT_VERSION:117 /* Though we've started our numbering from 1, and so class all118 * earlier versions as 0, in effect their value is undefined as119 * the ioctl will report EINVAL for the unknown param!120 */121 value = i915_gem_mmap_gtt_version();122 break;123 case I915_PARAM_HAS_SCHEDULER:124 value = i915->caps.scheduler;125 break;126 127 case I915_PARAM_MMAP_VERSION:128 /* Remember to bump this if the version changes! */129 case I915_PARAM_HAS_GEM:130 case I915_PARAM_HAS_PAGEFLIPPING:131 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */132 case I915_PARAM_HAS_RELAXED_FENCING:133 case I915_PARAM_HAS_COHERENT_RINGS:134 case I915_PARAM_HAS_RELAXED_DELTA:135 case I915_PARAM_HAS_GEN7_SOL_RESET:136 case I915_PARAM_HAS_WAIT_TIMEOUT:137 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:138 case I915_PARAM_HAS_PINNED_BATCHES:139 case I915_PARAM_HAS_EXEC_NO_RELOC:140 case I915_PARAM_HAS_EXEC_HANDLE_LUT:141 case I915_PARAM_HAS_COHERENT_PHYS_GTT:142 case I915_PARAM_HAS_EXEC_SOFTPIN:143 case I915_PARAM_HAS_EXEC_ASYNC:144 case I915_PARAM_HAS_EXEC_FENCE:145 case I915_PARAM_HAS_EXEC_CAPTURE:146 case I915_PARAM_HAS_EXEC_BATCH_FIRST:147 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:148 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:149 case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:150 case I915_PARAM_HAS_USERPTR_PROBE:151 /* For the time being all of these are always true;152 * if some supported hardware does not have one of these153 * features this value needs to be provided from154 * INTEL_INFO(), a feature macro, or similar.155 */156 value = 1;157 break;158 case I915_PARAM_HAS_CONTEXT_FREQ_HINT:159 if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))160 value = 1;161 else162 value = -EINVAL;163 break;164 case I915_PARAM_HAS_CONTEXT_ISOLATION:165 value = intel_engines_has_context_isolation(i915);166 break;167 case I915_PARAM_SLICE_MASK:168 /* Not supported from Xe_HP onward; use topology queries */169 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))170 return -EINVAL;171 172 value = sseu->slice_mask;173 if (!value)174 return -ENODEV;175 break;176 case I915_PARAM_SUBSLICE_MASK:177 /* Not supported from Xe_HP onward; use topology queries */178 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))179 return -EINVAL;180 181 /* Only copy bits from the first slice */182 value = intel_sseu_get_hsw_subslices(sseu, 0);183 if (!value)184 return -ENODEV;185 break;186 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:187 value = to_gt(i915)->clock_frequency;188 break;189 case I915_PARAM_MMAP_GTT_COHERENT:190 value = INTEL_INFO(i915)->has_coherent_ggtt;191 break;192 case I915_PARAM_PERF_REVISION:193 value = i915_perf_ioctl_version(i915);194 break;195 case I915_PARAM_OA_TIMESTAMP_FREQUENCY:196 value = i915_perf_oa_timestamp_frequency(i915);197 break;198 default:199 drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param);200 return -EINVAL;201 }202 203 if (put_user(value, param->value))204 return -EFAULT;205 206 return 0;207}208