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1/*2 * Copyright (c) 2008 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS21 * IN THE SOFTWARE.22 *23 * Authors:24 * Eric Anholt <eric@anholt.net>25 * Keith Packard <keithp@keithp.com>26 * Mika Kuoppala <mika.kuoppala@intel.com>27 *28 */29 30#include <linux/ascii85.h>31#include <linux/debugfs.h>32#include <linux/highmem.h>33#include <linux/nmi.h>34#include <linux/pagevec.h>35#include <linux/scatterlist.h>36#include <linux/string_helpers.h>37#include <linux/utsname.h>38#include <linux/zlib.h>39 40#include <drm/drm_cache.h>41#include <drm/drm_print.h>42 43#include "display/intel_dmc.h"44#include "display/intel_overlay.h"45 46#include "gem/i915_gem_context.h"47#include "gem/i915_gem_lmem.h"48#include "gt/intel_engine_regs.h"49#include "gt/intel_gt.h"50#include "gt/intel_gt_mcr.h"51#include "gt/intel_gt_pm.h"52#include "gt/intel_gt_regs.h"53#include "gt/uc/intel_guc_capture.h"54 55#include "i915_driver.h"56#include "i915_drv.h"57#include "i915_gpu_error.h"58#include "i915_memcpy.h"59#include "i915_reg.h"60#include "i915_scatterlist.h"61#include "i915_sysfs.h"62#include "i915_utils.h"63 64#define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)65#define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)66 67static void __sg_set_buf(struct scatterlist *sg,68 void *addr, unsigned int len, loff_t it)69{70 sg->page_link = (unsigned long)virt_to_page(addr);71 sg->offset = offset_in_page(addr);72 sg->length = len;73 sg->dma_address = it;74}75 76static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)77{78 if (!len)79 return false;80 81 if (e->bytes + len + 1 <= e->size)82 return true;83 84 if (e->bytes) {85 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);86 e->iter += e->bytes;87 e->buf = NULL;88 e->bytes = 0;89 }90 91 if (e->cur == e->end) {92 struct scatterlist *sgl;93 94 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);95 if (!sgl) {96 e->err = -ENOMEM;97 return false;98 }99 100 if (e->cur) {101 e->cur->offset = 0;102 e->cur->length = 0;103 e->cur->page_link =104 (unsigned long)sgl | SG_CHAIN;105 } else {106 e->sgl = sgl;107 }108 109 e->cur = sgl;110 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;111 }112 113 e->size = ALIGN(len + 1, SZ_64K);114 e->buf = kmalloc(e->size, ALLOW_FAIL);115 if (!e->buf) {116 e->size = PAGE_ALIGN(len + 1);117 e->buf = kmalloc(e->size, GFP_KERNEL);118 }119 if (!e->buf) {120 e->err = -ENOMEM;121 return false;122 }123 124 return true;125}126 127__printf(2, 0)128static void i915_error_vprintf(struct drm_i915_error_state_buf *e,129 const char *fmt, va_list args)130{131 va_list ap;132 int len;133 134 if (e->err)135 return;136 137 va_copy(ap, args);138 len = vsnprintf(NULL, 0, fmt, ap);139 va_end(ap);140 if (len <= 0) {141 e->err = len;142 return;143 }144 145 if (!__i915_error_grow(e, len))146 return;147 148 GEM_BUG_ON(e->bytes >= e->size);149 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);150 if (len < 0) {151 e->err = len;152 return;153 }154 e->bytes += len;155}156 157static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)158{159 unsigned len;160 161 if (e->err || !str)162 return;163 164 len = strlen(str);165 if (!__i915_error_grow(e, len))166 return;167 168 GEM_BUG_ON(e->bytes + len > e->size);169 memcpy(e->buf + e->bytes, str, len);170 e->bytes += len;171}172 173#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)174#define err_puts(e, s) i915_error_puts(e, s)175 176static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)177{178 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);179}180 181static inline struct drm_printer182i915_error_printer(struct drm_i915_error_state_buf *e)183{184 struct drm_printer p = {185 .printfn = __i915_printfn_error,186 .arg = e,187 };188 return p;189}190 191/* single threaded page allocator with a reserved stash for emergencies */192static void pool_fini(struct folio_batch *fbatch)193{194 folio_batch_release(fbatch);195}196 197static int pool_refill(struct folio_batch *fbatch, gfp_t gfp)198{199 while (folio_batch_space(fbatch)) {200 struct folio *folio;201 202 folio = folio_alloc(gfp, 0);203 if (!folio)204 return -ENOMEM;205 206 folio_batch_add(fbatch, folio);207 }208 209 return 0;210}211 212static int pool_init(struct folio_batch *fbatch, gfp_t gfp)213{214 int err;215 216 folio_batch_init(fbatch);217 218 err = pool_refill(fbatch, gfp);219 if (err)220 pool_fini(fbatch);221 222 return err;223}224 225static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp)226{227 struct folio *folio;228 229 folio = folio_alloc(gfp, 0);230 if (!folio && folio_batch_count(fbatch))231 folio = fbatch->folios[--fbatch->nr];232 233 return folio ? folio_address(folio) : NULL;234}235 236static void pool_free(struct folio_batch *fbatch, void *addr)237{238 struct folio *folio = virt_to_folio(addr);239 240 if (folio_batch_space(fbatch))241 folio_batch_add(fbatch, folio);242 else243 folio_put(folio);244}245 246#ifdef CONFIG_DRM_I915_COMPRESS_ERROR247 248struct i915_vma_compress {249 struct folio_batch pool;250 struct z_stream_s zstream;251 void *tmp;252};253 254static bool compress_init(struct i915_vma_compress *c)255{256 struct z_stream_s *zstream = &c->zstream;257 258 if (pool_init(&c->pool, ALLOW_FAIL))259 return false;260 261 zstream->workspace =262 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),263 ALLOW_FAIL);264 if (!zstream->workspace) {265 pool_fini(&c->pool);266 return false;267 }268 269 c->tmp = NULL;270 if (i915_has_memcpy_from_wc())271 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);272 273 return true;274}275 276static bool compress_start(struct i915_vma_compress *c)277{278 struct z_stream_s *zstream = &c->zstream;279 void *workspace = zstream->workspace;280 281 memset(zstream, 0, sizeof(*zstream));282 zstream->workspace = workspace;283 284 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;285}286 287static void *compress_next_page(struct i915_vma_compress *c,288 struct i915_vma_coredump *dst)289{290 void *page_addr;291 struct page *page;292 293 page_addr = pool_alloc(&c->pool, ALLOW_FAIL);294 if (!page_addr)295 return ERR_PTR(-ENOMEM);296 297 page = virt_to_page(page_addr);298 list_add_tail(&page->lru, &dst->page_list);299 return page_addr;300}301 302static int compress_page(struct i915_vma_compress *c,303 void *src,304 struct i915_vma_coredump *dst,305 bool wc)306{307 struct z_stream_s *zstream = &c->zstream;308 309 zstream->next_in = src;310 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))311 zstream->next_in = c->tmp;312 zstream->avail_in = PAGE_SIZE;313 314 do {315 if (zstream->avail_out == 0) {316 zstream->next_out = compress_next_page(c, dst);317 if (IS_ERR(zstream->next_out))318 return PTR_ERR(zstream->next_out);319 320 zstream->avail_out = PAGE_SIZE;321 }322 323 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)324 return -EIO;325 326 cond_resched();327 } while (zstream->avail_in);328 329 /* Fallback to uncompressed if we increase size? */330 if (0 && zstream->total_out > zstream->total_in)331 return -E2BIG;332 333 return 0;334}335 336static int compress_flush(struct i915_vma_compress *c,337 struct i915_vma_coredump *dst)338{339 struct z_stream_s *zstream = &c->zstream;340 341 do {342 switch (zlib_deflate(zstream, Z_FINISH)) {343 case Z_OK: /* more space requested */344 zstream->next_out = compress_next_page(c, dst);345 if (IS_ERR(zstream->next_out))346 return PTR_ERR(zstream->next_out);347 348 zstream->avail_out = PAGE_SIZE;349 break;350 351 case Z_STREAM_END:352 goto end;353 354 default: /* any error */355 return -EIO;356 }357 } while (1);358 359end:360 memset(zstream->next_out, 0, zstream->avail_out);361 dst->unused = zstream->avail_out;362 return 0;363}364 365static void compress_finish(struct i915_vma_compress *c)366{367 zlib_deflateEnd(&c->zstream);368}369 370static void compress_fini(struct i915_vma_compress *c)371{372 kfree(c->zstream.workspace);373 if (c->tmp)374 pool_free(&c->pool, c->tmp);375 pool_fini(&c->pool);376}377 378static void err_compression_marker(struct drm_i915_error_state_buf *m)379{380 err_puts(m, ":");381}382 383#else384 385struct i915_vma_compress {386 struct folio_batch pool;387};388 389static bool compress_init(struct i915_vma_compress *c)390{391 return pool_init(&c->pool, ALLOW_FAIL) == 0;392}393 394static bool compress_start(struct i915_vma_compress *c)395{396 return true;397}398 399static int compress_page(struct i915_vma_compress *c,400 void *src,401 struct i915_vma_coredump *dst,402 bool wc)403{404 void *ptr;405 406 ptr = pool_alloc(&c->pool, ALLOW_FAIL);407 if (!ptr)408 return -ENOMEM;409 410 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))411 memcpy(ptr, src, PAGE_SIZE);412 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list);413 cond_resched();414 415 return 0;416}417 418static int compress_flush(struct i915_vma_compress *c,419 struct i915_vma_coredump *dst)420{421 return 0;422}423 424static void compress_finish(struct i915_vma_compress *c)425{426}427 428static void compress_fini(struct i915_vma_compress *c)429{430 pool_fini(&c->pool);431}432 433static void err_compression_marker(struct drm_i915_error_state_buf *m)434{435 err_puts(m, "~");436}437 438#endif439 440static void error_print_instdone(struct drm_i915_error_state_buf *m,441 const struct intel_engine_coredump *ee)442{443 int slice;444 int subslice;445 int iter;446 447 err_printf(m, " INSTDONE: 0x%08x\n",448 ee->instdone.instdone);449 450 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)451 return;452 453 err_printf(m, " SC_INSTDONE: 0x%08x\n",454 ee->instdone.slice_common);455 456 if (GRAPHICS_VER(m->i915) <= 6)457 return;458 459 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)460 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",461 slice, subslice,462 ee->instdone.sampler[slice][subslice]);463 464 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)465 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",466 slice, subslice,467 ee->instdone.row[slice][subslice]);468 469 if (GRAPHICS_VER(m->i915) < 12)470 return;471 472 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {473 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)474 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",475 slice, subslice,476 ee->instdone.geom_svg[slice][subslice]);477 }478 479 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",480 ee->instdone.slice_common_extra[0]);481 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",482 ee->instdone.slice_common_extra[1]);483}484 485static void error_print_request(struct drm_i915_error_state_buf *m,486 const char *prefix,487 const struct i915_request_coredump *erq)488{489 if (!erq->seqno)490 return;491 492 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",493 prefix, erq->pid, erq->context, erq->seqno,494 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,495 &erq->flags) ? "!" : "",496 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,497 &erq->flags) ? "+" : "",498 erq->sched_attr.priority,499 erq->head, erq->tail);500}501 502static void error_print_context(struct drm_i915_error_state_buf *m,503 const char *header,504 const struct i915_gem_context_coredump *ctx)505{506 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",507 header, ctx->comm, ctx->pid, ctx->sched_attr.priority,508 ctx->guilty, ctx->active,509 ctx->total_runtime, ctx->avg_runtime);510 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno);511}512 513static struct i915_vma_coredump *514__find_vma(struct i915_vma_coredump *vma, const char *name)515{516 while (vma) {517 if (strcmp(vma->name, name) == 0)518 return vma;519 vma = vma->next;520 }521 522 return NULL;523}524 525static struct i915_vma_coredump *526intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)527{528 return __find_vma(ee->vma, "batch");529}530 531static void error_print_engine(struct drm_i915_error_state_buf *m,532 const struct intel_engine_coredump *ee)533{534 struct i915_vma_coredump *batch;535 int n;536 537 err_printf(m, "%s command stream:\n", ee->engine->name);538 err_printf(m, " CCID: 0x%08x\n", ee->ccid);539 err_printf(m, " START: 0x%08x\n", ee->start);540 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);541 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",542 ee->tail, ee->rq_post, ee->rq_tail);543 err_printf(m, " CTL: 0x%08x\n", ee->ctl);544 err_printf(m, " MODE: 0x%08x\n", ee->mode);545 err_printf(m, " HWS: 0x%08x\n", ee->hws);546 err_printf(m, " ACTHD: 0x%08x %08x\n",547 (u32)(ee->acthd>>32), (u32)ee->acthd);548 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);549 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);550 err_printf(m, " ESR: 0x%08x\n", ee->esr);551 552 error_print_instdone(m, ee);553 554 batch = intel_gpu_error_find_batch(ee);555 if (batch) {556 u64 start = batch->gtt_offset;557 u64 end = start + batch->gtt_size;558 559 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",560 upper_32_bits(start), lower_32_bits(start),561 upper_32_bits(end), lower_32_bits(end));562 }563 if (GRAPHICS_VER(m->i915) >= 4) {564 err_printf(m, " BBADDR: 0x%08x_%08x\n",565 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);566 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);567 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);568 }569 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);570 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),571 lower_32_bits(ee->faddr));572 if (GRAPHICS_VER(m->i915) >= 6) {573 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);574 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);575 }576 if (GRAPHICS_VER(m->i915) >= 11) {577 err_printf(m, " NOPID: 0x%08x\n", ee->nopid);578 err_printf(m, " EXCC: 0x%08x\n", ee->excc);579 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl);580 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop);581 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);582 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);583 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);584 }585 if (HAS_PPGTT(m->i915)) {586 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);587 588 if (GRAPHICS_VER(m->i915) >= 8) {589 int i;590 for (i = 0; i < 4; i++)591 err_printf(m, " PDP%d: 0x%016llx\n",592 i, ee->vm_info.pdp[i]);593 } else {594 err_printf(m, " PP_DIR_BASE: 0x%08x\n",595 ee->vm_info.pp_dir_base);596 }597 }598 599 for (n = 0; n < ee->num_ports; n++) {600 err_printf(m, " ELSP[%d]:", n);601 error_print_request(m, " ", &ee->execlist[n]);602 }603}604 605void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)606{607 va_list args;608 609 va_start(args, f);610 i915_error_vprintf(e, f, args);611 va_end(args);612}613 614static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,615 const struct intel_engine_cs *engine,616 const struct i915_vma_coredump *vma)617{618 char out[ASCII85_BUFSZ];619 struct page *page;620 621 if (!vma)622 return;623 624 err_printf(m, "%s --- %s = 0x%08x %08x\n",625 engine ? engine->name : "global", vma->name,626 upper_32_bits(vma->gtt_offset),627 lower_32_bits(vma->gtt_offset));628 629 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)630 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);631 632 err_compression_marker(m);633 list_for_each_entry(page, &vma->page_list, lru) {634 int i, len;635 const u32 *addr = page_address(page);636 637 len = PAGE_SIZE;638 if (page == list_last_entry(&vma->page_list, typeof(*page), lru))639 len -= vma->unused;640 len = ascii85_encode_len(len);641 642 for (i = 0; i < len; i++)643 err_puts(m, ascii85_encode(addr[i], out));644 }645 err_puts(m, "\n");646}647 648static void err_print_capabilities(struct drm_i915_error_state_buf *m,649 struct i915_gpu_coredump *error)650{651 struct drm_printer p = i915_error_printer(m);652 653 intel_device_info_print(&error->device_info, &error->runtime_info, &p);654 intel_display_device_info_print(&error->display_device_info,655 &error->display_runtime_info, &p);656 intel_driver_caps_print(&error->driver_caps, &p);657}658 659static void err_print_params(struct drm_i915_error_state_buf *m,660 const struct i915_params *params)661{662 struct drm_printer p = i915_error_printer(m);663 struct intel_display *display = &m->i915->display;664 665 i915_params_dump(params, &p);666 intel_display_params_dump(display, &p);667}668 669static void err_print_pciid(struct drm_i915_error_state_buf *m,670 struct drm_i915_private *i915)671{672 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);673 674 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);675 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);676 err_printf(m, "PCI Subsystem: %04x:%04x\n",677 pdev->subsystem_vendor,678 pdev->subsystem_device);679}680 681static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,682 const char *name,683 const struct intel_ctb_coredump *ctb)684{685 if (!ctb->size)686 return;687 688 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",689 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,690 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size);691}692 693static void err_print_uc(struct drm_i915_error_state_buf *m,694 const struct intel_uc_coredump *error_uc)695{696 struct drm_printer p = i915_error_printer(m);697 698 intel_uc_fw_dump(&error_uc->guc_fw, &p);699 intel_uc_fw_dump(&error_uc->huc_fw, &p);700 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);701 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);702 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);703 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);704 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);705 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);706}707 708static void err_free_sgl(struct scatterlist *sgl)709{710 while (sgl) {711 struct scatterlist *sg;712 713 for (sg = sgl; !sg_is_chain(sg); sg++) {714 kfree(sg_virt(sg));715 if (sg_is_last(sg))716 break;717 }718 719 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);720 free_page((unsigned long)sgl);721 sgl = sg;722 }723}724 725static void err_print_gt_info(struct drm_i915_error_state_buf *m,726 struct intel_gt_coredump *gt)727{728 struct drm_printer p = i915_error_printer(m);729 730 intel_gt_info_print(>->info, &p);731 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p);732}733 734static void err_print_gt_display(struct drm_i915_error_state_buf *m,735 struct intel_gt_coredump *gt)736{737 err_printf(m, "IER: 0x%08x\n", gt->ier);738 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);739}740 741static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,742 struct intel_gt_coredump *gt)743{744 int i;745 746 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));747 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",748 gt->clock_frequency, gt->clock_period_ns);749 err_printf(m, "EIR: 0x%08x\n", gt->eir);750 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);751 752 for (i = 0; i < gt->ngtier; i++)753 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);754}755 756static void err_print_gt_global(struct drm_i915_error_state_buf *m,757 struct intel_gt_coredump *gt)758{759 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);760 761 if (IS_GRAPHICS_VER(m->i915, 6, 11)) {762 err_printf(m, "ERROR: 0x%08x\n", gt->error);763 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);764 }765 766 if (GRAPHICS_VER(m->i915) >= 8)767 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",768 gt->fault_data1, gt->fault_data0);769 770 if (GRAPHICS_VER(m->i915) == 7)771 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);772 773 if (IS_GRAPHICS_VER(m->i915, 8, 11))774 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);775 776 if (GRAPHICS_VER(m->i915) == 12)777 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);778 779 if (GRAPHICS_VER(m->i915) >= 12) {780 int i;781 782 for (i = 0; i < I915_MAX_SFC; i++) {783 /*784 * SFC_DONE resides in the VD forcewake domain, so it785 * only exists if the corresponding VCS engine is786 * present.787 */788 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||789 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))790 continue;791 792 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i,793 gt->sfc_done[i]);794 }795 796 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done);797 }798}799 800static void err_print_gt_fences(struct drm_i915_error_state_buf *m,801 struct intel_gt_coredump *gt)802{803 int i;804 805 for (i = 0; i < gt->nfence; i++)806 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);807}808 809static void err_print_gt_engines(struct drm_i915_error_state_buf *m,810 struct intel_gt_coredump *gt)811{812 const struct intel_engine_coredump *ee;813 814 for (ee = gt->engine; ee; ee = ee->next) {815 const struct i915_vma_coredump *vma;816 817 if (gt->uc && gt->uc->guc.is_guc_capture) {818 if (ee->guc_capture_node)819 intel_guc_capture_print_engine_node(m, ee);820 else821 err_printf(m, " Missing GuC capture node for %s\n",822 ee->engine->name);823 } else {824 error_print_engine(m, ee);825 }826 827 err_printf(m, " hung: %u\n", ee->hung);828 err_printf(m, " engine reset count: %u\n", ee->reset_count);829 error_print_context(m, " Active context: ", &ee->context);830 831 for (vma = ee->vma; vma; vma = vma->next)832 intel_gpu_error_print_vma(m, ee->engine, vma);833 }834 835}836 837static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,838 struct i915_gpu_coredump *error)839{840 struct drm_printer p = i915_error_printer(m);841 const struct intel_engine_coredump *ee;842 struct timespec64 ts;843 844 if (*error->error_msg)845 err_printf(m, "%s\n", error->error_msg);846 err_printf(m, "Kernel: %s %s\n",847 init_utsname()->release,848 init_utsname()->machine);849 err_printf(m, "Driver: %s\n", DRIVER_DATE);850 ts = ktime_to_timespec64(error->time);851 err_printf(m, "Time: %lld s %ld us\n",852 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);853 ts = ktime_to_timespec64(error->boottime);854 err_printf(m, "Boottime: %lld s %ld us\n",855 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);856 ts = ktime_to_timespec64(error->uptime);857 err_printf(m, "Uptime: %lld s %ld us\n",858 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);859 err_printf(m, "Capture: %lu jiffies; %d ms ago\n",860 error->capture, jiffies_to_msecs(jiffies - error->capture));861 862 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)863 err_printf(m, "Active process (on ring %s): %s [%d]\n",864 ee->engine->name,865 ee->context.comm,866 ee->context.pid);867 868 err_printf(m, "Reset count: %u\n", error->reset_count);869 err_printf(m, "Suspend count: %u\n", error->suspend_count);870 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));871 err_printf(m, "Subplatform: 0x%x\n",872 intel_subplatform(&error->runtime_info,873 error->device_info.platform));874 err_print_pciid(m, m->i915);875 876 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);877 878 intel_dmc_print_error_state(&p, m->i915);879 880 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));881 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));882 883 if (error->gt) {884 bool print_guc_capture = false;885 886 if (error->gt->uc && error->gt->uc->guc.is_guc_capture)887 print_guc_capture = true;888 889 err_print_gt_display(m, error->gt);890 err_print_gt_global_nonguc(m, error->gt);891 err_print_gt_fences(m, error->gt);892 893 /*894 * GuC dumped global, eng-class and eng-instance registers together895 * as part of engine state dump so we print in err_print_gt_engines896 */897 if (!print_guc_capture)898 err_print_gt_global(m, error->gt);899 900 err_print_gt_engines(m, error->gt);901 902 if (error->gt->uc)903 err_print_uc(m, error->gt->uc);904 905 err_print_gt_info(m, error->gt);906 }907 908 if (error->overlay)909 intel_overlay_print_error_state(&p, error->overlay);910 911 err_print_capabilities(m, error);912 err_print_params(m, &error->params);913}914 915static int err_print_to_sgl(struct i915_gpu_coredump *error)916{917 struct drm_i915_error_state_buf m;918 919 if (IS_ERR(error))920 return PTR_ERR(error);921 922 if (READ_ONCE(error->sgl))923 return 0;924 925 memset(&m, 0, sizeof(m));926 m.i915 = error->i915;927 928 __err_print_to_sgl(&m, error);929 930 if (m.buf) {931 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);932 m.bytes = 0;933 m.buf = NULL;934 }935 if (m.cur) {936 GEM_BUG_ON(m.end < m.cur);937 sg_mark_end(m.cur - 1);938 }939 GEM_BUG_ON(m.sgl && !m.cur);940 941 if (m.err) {942 err_free_sgl(m.sgl);943 return m.err;944 }945 946 if (cmpxchg(&error->sgl, NULL, m.sgl))947 err_free_sgl(m.sgl);948 949 return 0;950}951 952ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,953 char *buf, loff_t off, size_t rem)954{955 struct scatterlist *sg;956 size_t count;957 loff_t pos;958 int err;959 960 if (!error || !rem)961 return 0;962 963 err = err_print_to_sgl(error);964 if (err)965 return err;966 967 sg = READ_ONCE(error->fit);968 if (!sg || off < sg->dma_address)969 sg = error->sgl;970 if (!sg)971 return 0;972 973 pos = sg->dma_address;974 count = 0;975 do {976 size_t len, start;977 978 if (sg_is_chain(sg)) {979 sg = sg_chain_ptr(sg);980 GEM_BUG_ON(sg_is_chain(sg));981 }982 983 len = sg->length;984 if (pos + len <= off) {985 pos += len;986 continue;987 }988 989 start = sg->offset;990 if (pos < off) {991 GEM_BUG_ON(off - pos > len);992 len -= off - pos;993 start += off - pos;994 pos = off;995 }996 997 len = min(len, rem);998 GEM_BUG_ON(!len || len > sg->length);999 1000 memcpy(buf, page_address(sg_page(sg)) + start, len);1001 1002 count += len;1003 pos += len;1004 1005 buf += len;1006 rem -= len;1007 if (!rem) {1008 WRITE_ONCE(error->fit, sg);1009 break;1010 }1011 } while (!sg_is_last(sg++));1012 1013 return count;1014}1015 1016static void i915_vma_coredump_free(struct i915_vma_coredump *vma)1017{1018 while (vma) {1019 struct i915_vma_coredump *next = vma->next;1020 struct page *page, *n;1021 1022 list_for_each_entry_safe(page, n, &vma->page_list, lru) {1023 list_del_init(&page->lru);1024 __free_page(page);1025 }1026 1027 kfree(vma);1028 vma = next;1029 }1030}1031 1032static void cleanup_params(struct i915_gpu_coredump *error)1033{1034 i915_params_free(&error->params);1035 intel_display_params_free(&error->display_params);1036}1037 1038static void cleanup_uc(struct intel_uc_coredump *uc)1039{1040 kfree(uc->guc_fw.file_selected.path);1041 kfree(uc->huc_fw.file_selected.path);1042 kfree(uc->guc_fw.file_wanted.path);1043 kfree(uc->huc_fw.file_wanted.path);1044 i915_vma_coredump_free(uc->guc.vma_log);1045 i915_vma_coredump_free(uc->guc.vma_ctb);1046 1047 kfree(uc);1048}1049 1050static void cleanup_gt(struct intel_gt_coredump *gt)1051{1052 while (gt->engine) {1053 struct intel_engine_coredump *ee = gt->engine;1054 1055 gt->engine = ee->next;1056 1057 i915_vma_coredump_free(ee->vma);1058 intel_guc_capture_free_node(ee);1059 kfree(ee);1060 }1061 1062 if (gt->uc)1063 cleanup_uc(gt->uc);1064 1065 kfree(gt);1066}1067 1068void __i915_gpu_coredump_free(struct kref *error_ref)1069{1070 struct i915_gpu_coredump *error =1071 container_of(error_ref, typeof(*error), ref);1072 1073 while (error->gt) {1074 struct intel_gt_coredump *gt = error->gt;1075 1076 error->gt = gt->next;1077 cleanup_gt(gt);1078 }1079 1080 kfree(error->overlay);1081 1082 cleanup_params(error);1083 1084 err_free_sgl(error->sgl);1085 kfree(error);1086}1087 1088static struct i915_vma_coredump *1089i915_vma_coredump_create(const struct intel_gt *gt,1090 const struct i915_vma_resource *vma_res,1091 struct i915_vma_compress *compress,1092 const char *name)1093 1094{1095 struct i915_ggtt *ggtt = gt->ggtt;1096 const u64 slot = ggtt->error_capture.start;1097 struct i915_vma_coredump *dst;1098 struct sgt_iter iter;1099 int ret;1100 1101 might_sleep();1102 1103 if (!vma_res || !vma_res->bi.pages || !compress)1104 return NULL;1105 1106 dst = kmalloc(sizeof(*dst), ALLOW_FAIL);1107 if (!dst)1108 return NULL;1109 1110 if (!compress_start(compress)) {1111 kfree(dst);1112 return NULL;1113 }1114 1115 INIT_LIST_HEAD(&dst->page_list);1116 strcpy(dst->name, name);1117 dst->next = NULL;1118 1119 dst->gtt_offset = vma_res->start;1120 dst->gtt_size = vma_res->node_size;1121 dst->gtt_page_sizes = vma_res->page_sizes_gtt;1122 dst->unused = 0;1123 1124 ret = -EINVAL;1125 if (drm_mm_node_allocated(&ggtt->error_capture)) {1126 void __iomem *s;1127 dma_addr_t dma;1128 1129 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {1130 mutex_lock(&ggtt->error_mutex);1131 if (ggtt->vm.raw_insert_page)1132 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,1133 i915_gem_get_pat_index(gt->i915,1134 I915_CACHE_NONE),1135 0);1136 else1137 ggtt->vm.insert_page(&ggtt->vm, dma, slot,1138 i915_gem_get_pat_index(gt->i915,1139 I915_CACHE_NONE),1140 0);1141 mb();1142 1143 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);1144 ret = compress_page(compress,1145 (void __force *)s, dst,1146 true);1147 io_mapping_unmap(s);1148 1149 mb();1150 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);1151 mutex_unlock(&ggtt->error_mutex);1152 if (ret)1153 break;1154 }1155 } else if (vma_res->bi.lmem) {1156 struct intel_memory_region *mem = vma_res->mr;1157 dma_addr_t dma;1158 1159 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {1160 dma_addr_t offset = dma - mem->region.start;1161 void __iomem *s;1162 1163 if (offset + PAGE_SIZE > resource_size(&mem->io)) {1164 ret = -EINVAL;1165 break;1166 }1167 1168 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);1169 ret = compress_page(compress,1170 (void __force *)s, dst,1171 true);1172 io_mapping_unmap(s);1173 if (ret)1174 break;1175 }1176 } else {1177 struct page *page;1178 1179 for_each_sgt_page(page, iter, vma_res->bi.pages) {1180 void *s;1181 1182 drm_clflush_pages(&page, 1);1183 1184 s = kmap_local_page(page);1185 ret = compress_page(compress, s, dst, false);1186 kunmap_local(s);1187 1188 drm_clflush_pages(&page, 1);1189 1190 if (ret)1191 break;1192 }1193 }1194 1195 if (ret || compress_flush(compress, dst)) {1196 struct page *page, *n;1197 1198 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) {1199 list_del_init(&page->lru);1200 pool_free(&compress->pool, page_address(page));1201 }1202 1203 kfree(dst);1204 dst = NULL;1205 }1206 compress_finish(compress);1207 1208 return dst;1209}1210 1211static void gt_record_fences(struct intel_gt_coredump *gt)1212{1213 struct i915_ggtt *ggtt = gt->_gt->ggtt;1214 struct intel_uncore *uncore = gt->_gt->uncore;1215 int i;1216 1217 if (GRAPHICS_VER(uncore->i915) >= 6) {1218 for (i = 0; i < ggtt->num_fences; i++)1219 gt->fence[i] =1220 intel_uncore_read64(uncore,1221 FENCE_REG_GEN6_LO(i));1222 } else if (GRAPHICS_VER(uncore->i915) >= 4) {1223 for (i = 0; i < ggtt->num_fences; i++)1224 gt->fence[i] =1225 intel_uncore_read64(uncore,1226 FENCE_REG_965_LO(i));1227 } else {1228 for (i = 0; i < ggtt->num_fences; i++)1229 gt->fence[i] =1230 intel_uncore_read(uncore, FENCE_REG(i));1231 }1232 gt->nfence = i;1233}1234 1235static void engine_record_registers(struct intel_engine_coredump *ee)1236{1237 const struct intel_engine_cs *engine = ee->engine;1238 struct drm_i915_private *i915 = engine->i915;1239 1240 if (GRAPHICS_VER(i915) >= 6) {1241 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);1242 1243 /*1244 * For the media GT, this ring fault register is not replicated,1245 * so don't do multicast/replicated register read/write1246 * operation on it.1247 */1248 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)1249 ee->fault_reg = intel_uncore_read(engine->uncore,1250 XELPMP_RING_FAULT_REG);1251 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))1252 ee->fault_reg = intel_gt_mcr_read_any(engine->gt,1253 XEHP_RING_FAULT_REG);1254 else if (GRAPHICS_VER(i915) >= 12)1255 ee->fault_reg = intel_uncore_read(engine->uncore,1256 GEN12_RING_FAULT_REG);1257 else if (GRAPHICS_VER(i915) >= 8)1258 ee->fault_reg = intel_uncore_read(engine->uncore,1259 GEN8_RING_FAULT_REG);1260 else1261 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);1262 }1263 1264 if (GRAPHICS_VER(i915) >= 4) {1265 ee->esr = ENGINE_READ(engine, RING_ESR);1266 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);1267 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);1268 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);1269 ee->instps = ENGINE_READ(engine, RING_INSTPS);1270 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);1271 ee->ccid = ENGINE_READ(engine, CCID);1272 if (GRAPHICS_VER(i915) >= 8) {1273 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;1274 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;1275 }1276 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);1277 } else {1278 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);1279 ee->ipeir = ENGINE_READ(engine, IPEIR);1280 ee->ipehr = ENGINE_READ(engine, IPEHR);1281 }1282 1283 if (GRAPHICS_VER(i915) >= 11) {1284 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);1285 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);1286 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);1287 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);1288 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);1289 ee->nopid = ENGINE_READ(engine, RING_NOPID);1290 ee->excc = ENGINE_READ(engine, RING_EXCC);1291 }1292 1293 intel_engine_get_instdone(engine, &ee->instdone);1294 1295 ee->instpm = ENGINE_READ(engine, RING_INSTPM);1296 ee->acthd = intel_engine_get_active_head(engine);1297 ee->start = ENGINE_READ(engine, RING_START);1298 ee->head = ENGINE_READ(engine, RING_HEAD);1299 ee->tail = ENGINE_READ(engine, RING_TAIL);1300 ee->ctl = ENGINE_READ(engine, RING_CTL);1301 if (GRAPHICS_VER(i915) > 2)1302 ee->mode = ENGINE_READ(engine, RING_MI_MODE);1303 1304 if (!HWS_NEEDS_PHYSICAL(i915)) {1305 i915_reg_t mmio;1306 1307 if (GRAPHICS_VER(i915) == 7) {1308 switch (engine->id) {1309 default:1310 MISSING_CASE(engine->id);1311 fallthrough;1312 case RCS0:1313 mmio = RENDER_HWS_PGA_GEN7;1314 break;1315 case BCS0:1316 mmio = BLT_HWS_PGA_GEN7;1317 break;1318 case VCS0:1319 mmio = BSD_HWS_PGA_GEN7;1320 break;1321 case VECS0:1322 mmio = VEBOX_HWS_PGA_GEN7;1323 break;1324 }1325 } else if (GRAPHICS_VER(engine->i915) == 6) {1326 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);1327 } else {1328 /* XXX: gen8 returns to sanity */1329 mmio = RING_HWS_PGA(engine->mmio_base);1330 }1331 1332 ee->hws = intel_uncore_read(engine->uncore, mmio);1333 }1334 1335 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);1336 1337 if (HAS_PPGTT(i915)) {1338 int i;1339 1340 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);1341 1342 if (GRAPHICS_VER(i915) == 6) {1343 ee->vm_info.pp_dir_base =1344 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);1345 } else if (GRAPHICS_VER(i915) == 7) {1346 ee->vm_info.pp_dir_base =1347 ENGINE_READ(engine, RING_PP_DIR_BASE);1348 } else if (GRAPHICS_VER(i915) >= 8) {1349 u32 base = engine->mmio_base;1350 1351 for (i = 0; i < 4; i++) {1352 ee->vm_info.pdp[i] =1353 intel_uncore_read(engine->uncore,1354 GEN8_RING_PDP_UDW(base, i));1355 ee->vm_info.pdp[i] <<= 32;1356 ee->vm_info.pdp[i] |=1357 intel_uncore_read(engine->uncore,1358 GEN8_RING_PDP_LDW(base, i));1359 }1360 }1361 }1362}1363 1364static void record_request(const struct i915_request *request,1365 struct i915_request_coredump *erq)1366{1367 erq->flags = request->fence.flags;1368 erq->context = request->fence.context;1369 erq->seqno = request->fence.seqno;1370 erq->sched_attr = request->sched.attr;1371 erq->head = request->head;1372 erq->tail = request->tail;1373 1374 erq->pid = 0;1375 rcu_read_lock();1376 if (!intel_context_is_closed(request->context)) {1377 const struct i915_gem_context *ctx;1378 1379 ctx = rcu_dereference(request->context->gem_context);1380 if (ctx)1381 erq->pid = pid_nr(ctx->pid);1382 }1383 rcu_read_unlock();1384}1385 1386static void engine_record_execlists(struct intel_engine_coredump *ee)1387{1388 const struct intel_engine_execlists * const el = &ee->engine->execlists;1389 struct i915_request * const *port = el->active;1390 unsigned int n = 0;1391 1392 while (*port)1393 record_request(*port++, &ee->execlist[n++]);1394 1395 ee->num_ports = n;1396}1397 1398static bool record_context(struct i915_gem_context_coredump *e,1399 struct intel_context *ce)1400{1401 struct i915_gem_context *ctx;1402 struct task_struct *task;1403 bool simulated;1404 1405 rcu_read_lock();1406 ctx = rcu_dereference(ce->gem_context);1407 if (ctx && !kref_get_unless_zero(&ctx->ref))1408 ctx = NULL;1409 rcu_read_unlock();1410 if (!ctx)1411 return true;1412 1413 rcu_read_lock();1414 task = pid_task(ctx->pid, PIDTYPE_PID);1415 if (task) {1416 strcpy(e->comm, task->comm);1417 e->pid = task->pid;1418 }1419 rcu_read_unlock();1420 1421 e->sched_attr = ctx->sched;1422 e->guilty = atomic_read(&ctx->guilty_count);1423 e->active = atomic_read(&ctx->active_count);1424 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ?1425 *ce->timeline->hwsp_seqno : ~0U;1426 1427 e->total_runtime = intel_context_get_total_runtime_ns(ce);1428 e->avg_runtime = intel_context_get_avg_runtime_ns(ce);1429 1430 simulated = i915_gem_context_no_error_capture(ctx);1431 1432 i915_gem_context_put(ctx);1433 return simulated;1434}1435 1436struct intel_engine_capture_vma {1437 struct intel_engine_capture_vma *next;1438 struct i915_vma_resource *vma_res;1439 char name[16];1440 bool lockdep_cookie;1441};1442 1443static struct intel_engine_capture_vma *1444capture_vma_snapshot(struct intel_engine_capture_vma *next,1445 struct i915_vma_resource *vma_res,1446 gfp_t gfp, const char *name)1447{1448 struct intel_engine_capture_vma *c;1449 1450 if (!vma_res)1451 return next;1452 1453 c = kmalloc(sizeof(*c), gfp);1454 if (!c)1455 return next;1456 1457 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) {1458 kfree(c);1459 return next;1460 }1461 1462 strcpy(c->name, name);1463 c->vma_res = i915_vma_resource_get(vma_res);1464 1465 c->next = next;1466 return c;1467}1468 1469static struct intel_engine_capture_vma *1470capture_vma(struct intel_engine_capture_vma *next,1471 struct i915_vma *vma,1472 const char *name,1473 gfp_t gfp)1474{1475 if (!vma)1476 return next;1477 1478 /*1479 * If the vma isn't pinned, then the vma should be snapshotted1480 * to a struct i915_vma_snapshot at command submission time.1481 * Not here.1482 */1483 if (GEM_WARN_ON(!i915_vma_is_pinned(vma)))1484 return next;1485 1486 next = capture_vma_snapshot(next, vma->resource, gfp, name);1487 1488 return next;1489}1490 1491static struct intel_engine_capture_vma *1492capture_user(struct intel_engine_capture_vma *capture,1493 const struct i915_request *rq,1494 gfp_t gfp)1495{1496 struct i915_capture_list *c;1497 1498 for (c = rq->capture_list; c; c = c->next)1499 capture = capture_vma_snapshot(capture, c->vma_res, gfp,1500 "user");1501 1502 return capture;1503}1504 1505static void add_vma(struct intel_engine_coredump *ee,1506 struct i915_vma_coredump *vma)1507{1508 if (vma) {1509 vma->next = ee->vma;1510 ee->vma = vma;1511 }1512}1513 1514static struct i915_vma_coredump *1515create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,1516 const char *name, struct i915_vma_compress *compress)1517{1518 struct i915_vma_coredump *ret = NULL;1519 struct i915_vma_resource *vma_res;1520 bool lockdep_cookie;1521 1522 if (!vma)1523 return NULL;1524 1525 vma_res = vma->resource;1526 1527 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) {1528 ret = i915_vma_coredump_create(gt, vma_res, compress, name);1529 i915_vma_resource_unhold(vma_res, lockdep_cookie);1530 }1531 1532 return ret;1533}1534 1535static void add_vma_coredump(struct intel_engine_coredump *ee,1536 const struct intel_gt *gt,1537 struct i915_vma *vma,1538 const char *name,1539 struct i915_vma_compress *compress)1540{1541 add_vma(ee, create_vma_coredump(gt, vma, name, compress));1542}1543 1544struct intel_engine_coredump *1545intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)1546{1547 struct intel_engine_coredump *ee;1548 1549 ee = kzalloc(sizeof(*ee), gfp);1550 if (!ee)1551 return NULL;1552 1553 ee->engine = engine;1554 1555 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) {1556 engine_record_registers(ee);1557 engine_record_execlists(ee);1558 }1559 1560 return ee;1561}1562 1563static struct intel_engine_capture_vma *1564engine_coredump_add_context(struct intel_engine_coredump *ee,1565 struct intel_context *ce,1566 gfp_t gfp)1567{1568 struct intel_engine_capture_vma *vma = NULL;1569 1570 ee->simulated |= record_context(&ee->context, ce);1571 if (ee->simulated)1572 return NULL;1573 1574 /*1575 * We need to copy these to an anonymous buffer1576 * as the simplest method to avoid being overwritten1577 * by userspace.1578 */1579 vma = capture_vma(vma, ce->ring->vma, "ring", gfp);1580 vma = capture_vma(vma, ce->state, "HW context", gfp);1581 1582 return vma;1583}1584 1585struct intel_engine_capture_vma *1586intel_engine_coredump_add_request(struct intel_engine_coredump *ee,1587 struct i915_request *rq,1588 gfp_t gfp)1589{1590 struct intel_engine_capture_vma *vma;1591 1592 vma = engine_coredump_add_context(ee, rq->context, gfp);1593 if (!vma)1594 return NULL;1595 1596 /*1597 * We need to copy these to an anonymous buffer1598 * as the simplest method to avoid being overwritten1599 * by userspace.1600 */1601 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");1602 vma = capture_user(vma, rq, gfp);1603 1604 ee->rq_head = rq->head;1605 ee->rq_post = rq->postfix;1606 ee->rq_tail = rq->tail;1607 1608 return vma;1609}1610 1611void1612intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,1613 struct intel_engine_capture_vma *capture,1614 struct i915_vma_compress *compress)1615{1616 const struct intel_engine_cs *engine = ee->engine;1617 1618 while (capture) {1619 struct intel_engine_capture_vma *this = capture;1620 struct i915_vma_resource *vma_res = this->vma_res;1621 1622 add_vma(ee,1623 i915_vma_coredump_create(engine->gt, vma_res,1624 compress, this->name));1625 1626 i915_vma_resource_unhold(vma_res, this->lockdep_cookie);1627 i915_vma_resource_put(vma_res);1628 1629 capture = this->next;1630 kfree(this);1631 }1632 1633 add_vma_coredump(ee, engine->gt, engine->status_page.vma,1634 "HW Status", compress);1635 1636 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,1637 "WA context", compress);1638}1639 1640static struct intel_engine_coredump *1641capture_engine(struct intel_engine_cs *engine,1642 struct i915_vma_compress *compress,1643 u32 dump_flags)1644{1645 struct intel_engine_capture_vma *capture = NULL;1646 struct intel_engine_coredump *ee;1647 struct intel_context *ce = NULL;1648 struct i915_request *rq = NULL;1649 1650 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);1651 if (!ee)1652 return NULL;1653 1654 intel_engine_get_hung_entity(engine, &ce, &rq);1655 if (rq && !i915_request_started(rq))1656 drm_info(&engine->gt->i915->drm, "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n",1657 engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id);1658 1659 if (rq) {1660 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);1661 i915_request_put(rq);1662 } else if (ce) {1663 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL);1664 }1665 1666 if (capture) {1667 intel_engine_coredump_add_vma(ee, capture, compress);1668 1669 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)1670 intel_guc_capture_get_matching_node(engine->gt, ee, ce);1671 } else {1672 kfree(ee);1673 ee = NULL;1674 }1675 1676 return ee;1677}1678 1679static void1680gt_record_engines(struct intel_gt_coredump *gt,1681 intel_engine_mask_t engine_mask,1682 struct i915_vma_compress *compress,1683 u32 dump_flags)1684{1685 struct intel_engine_cs *engine;1686 enum intel_engine_id id;1687 1688 for_each_engine(engine, gt->_gt, id) {1689 struct intel_engine_coredump *ee;1690 1691 /* Refill our page pool before entering atomic section */1692 pool_refill(&compress->pool, ALLOW_FAIL);1693 1694 ee = capture_engine(engine, compress, dump_flags);1695 if (!ee)1696 continue;1697 1698 ee->hung = engine->mask & engine_mask;1699 1700 gt->simulated |= ee->simulated;1701 if (ee->simulated) {1702 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)1703 intel_guc_capture_free_node(ee);1704 kfree(ee);1705 continue;1706 }1707 1708 ee->next = gt->engine;1709 gt->engine = ee;1710 }1711}1712 1713static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,1714 const struct intel_guc_ct_buffer *ctb,1715 const void *blob_ptr, struct intel_guc *guc)1716{1717 if (!ctb || !ctb->desc)1718 return;1719 1720 saved->raw_status = ctb->desc->status;1721 saved->raw_head = ctb->desc->head;1722 saved->raw_tail = ctb->desc->tail;1723 saved->head = ctb->head;1724 saved->tail = ctb->tail;1725 saved->size = ctb->size;1726 saved->desc_offset = ((void *)ctb->desc) - blob_ptr;1727 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;1728}1729 1730static struct intel_uc_coredump *1731gt_record_uc(struct intel_gt_coredump *gt,1732 struct i915_vma_compress *compress)1733{1734 const struct intel_uc *uc = >->_gt->uc;1735 struct intel_uc_coredump *error_uc;1736 1737 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);1738 if (!error_uc)1739 return NULL;1740 1741 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));1742 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));1743 1744 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL);1745 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL);1746 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL);1747 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL);1748 1749 /*1750 * Save the GuC log and include a timestamp reference for converting the1751 * log times to system times (in conjunction with the error->boottime and1752 * gt->clock_frequency fields saved elsewhere).1753 */1754 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);1755 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,1756 "GuC log buffer", compress);1757 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,1758 "GuC CT buffer", compress);1759 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;1760 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send,1761 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);1762 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv,1763 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);1764 1765 return error_uc;1766}1767 1768/* Capture display registers. */1769static void gt_record_display_regs(struct intel_gt_coredump *gt)1770{1771 struct intel_uncore *uncore = gt->_gt->uncore;1772 struct drm_i915_private *i915 = uncore->i915;1773 1774 if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)1775 gt->derrmr = intel_uncore_read(uncore, DERRMR);1776 1777 if (GRAPHICS_VER(i915) >= 8)1778 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);1779 else if (IS_VALLEYVIEW(i915))1780 gt->ier = intel_uncore_read(uncore, VLV_IER);1781 else if (HAS_PCH_SPLIT(i915))1782 gt->ier = intel_uncore_read(uncore, DEIER);1783 else if (GRAPHICS_VER(i915) == 2)1784 gt->ier = intel_uncore_read16(uncore, GEN2_IER);1785 else1786 gt->ier = intel_uncore_read(uncore, GEN2_IER);1787}1788 1789/* Capture all other registers that GuC doesn't capture. */1790static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)1791{1792 struct intel_uncore *uncore = gt->_gt->uncore;1793 struct drm_i915_private *i915 = uncore->i915;1794 int i;1795 1796 if (IS_VALLEYVIEW(i915)) {1797 gt->gtier[0] = intel_uncore_read(uncore, GTIER);1798 gt->ngtier = 1;1799 } else if (GRAPHICS_VER(i915) >= 11) {1800 gt->gtier[0] =1801 intel_uncore_read(uncore,1802 GEN11_RENDER_COPY_INTR_ENABLE);1803 gt->gtier[1] =1804 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);1805 gt->gtier[2] =1806 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);1807 gt->gtier[3] =1808 intel_uncore_read(uncore,1809 GEN11_GPM_WGBOXPERF_INTR_ENABLE);1810 gt->gtier[4] =1811 intel_uncore_read(uncore,1812 GEN11_CRYPTO_RSVD_INTR_ENABLE);1813 gt->gtier[5] =1814 intel_uncore_read(uncore,1815 GEN11_GUNIT_CSME_INTR_ENABLE);1816 gt->ngtier = 6;1817 } else if (GRAPHICS_VER(i915) >= 8) {1818 for (i = 0; i < 4; i++)1819 gt->gtier[i] =1820 intel_uncore_read(uncore, GEN8_GT_IER(i));1821 gt->ngtier = 4;1822 } else if (HAS_PCH_SPLIT(i915)) {1823 gt->gtier[0] = intel_uncore_read(uncore, GTIER);1824 gt->ngtier = 1;1825 }1826 1827 gt->eir = intel_uncore_read(uncore, EIR);1828 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);1829}1830 1831/*1832 * Capture all registers that relate to workload submission.1833 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us1834 */1835static void gt_record_global_regs(struct intel_gt_coredump *gt)1836{1837 struct intel_uncore *uncore = gt->_gt->uncore;1838 struct drm_i915_private *i915 = uncore->i915;1839 int i;1840 1841 /*1842 * General organization1843 * 1. Registers specific to a single generation1844 * 2. Registers which belong to multiple generations1845 * 3. Feature specific registers.1846 * 4. Everything else1847 * Please try to follow the order.1848 */1849 1850 /* 1: Registers specific to a single generation */1851 if (IS_VALLEYVIEW(i915))1852 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);1853 1854 if (GRAPHICS_VER(i915) == 7)1855 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);1856 1857 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {1858 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,1859 XEHP_FAULT_TLB_DATA0);1860 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,1861 XEHP_FAULT_TLB_DATA1);1862 } else if (GRAPHICS_VER(i915) >= 12) {1863 gt->fault_data0 = intel_uncore_read(uncore,1864 GEN12_FAULT_TLB_DATA0);1865 gt->fault_data1 = intel_uncore_read(uncore,1866 GEN12_FAULT_TLB_DATA1);1867 } else if (GRAPHICS_VER(i915) >= 8) {1868 gt->fault_data0 = intel_uncore_read(uncore,1869 GEN8_FAULT_TLB_DATA0);1870 gt->fault_data1 = intel_uncore_read(uncore,1871 GEN8_FAULT_TLB_DATA1);1872 }1873 1874 if (GRAPHICS_VER(i915) == 6) {1875 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);1876 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);1877 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);1878 }1879 1880 /* 2: Registers which belong to multiple generations */1881 if (GRAPHICS_VER(i915) >= 7)1882 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);1883 1884 if (GRAPHICS_VER(i915) >= 6) {1885 if (GRAPHICS_VER(i915) < 12) {1886 gt->error = intel_uncore_read(uncore, ERROR_GEN6);1887 gt->done_reg = intel_uncore_read(uncore, DONE_REG);1888 }1889 }1890 1891 /* 3: Feature specific registers */1892 if (IS_GRAPHICS_VER(i915, 6, 7)) {1893 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);1894 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);1895 }1896 1897 if (IS_GRAPHICS_VER(i915, 8, 11))1898 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);1899 1900 if (GRAPHICS_VER(i915) == 12)1901 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);1902 1903 if (GRAPHICS_VER(i915) >= 12) {1904 for (i = 0; i < I915_MAX_SFC; i++) {1905 /*1906 * SFC_DONE resides in the VD forcewake domain, so it1907 * only exists if the corresponding VCS engine is1908 * present.1909 */1910 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||1911 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))1912 continue;1913 1914 gt->sfc_done[i] =1915 intel_uncore_read(uncore, GEN12_SFC_DONE(i));1916 }1917 1918 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);1919 }1920}1921 1922static void gt_record_info(struct intel_gt_coredump *gt)1923{1924 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));1925 gt->clock_frequency = gt->_gt->clock_frequency;1926 gt->clock_period_ns = gt->_gt->clock_period_ns;1927}1928 1929/*1930 * Generate a semi-unique error code. The code is not meant to have meaning, The1931 * code's only purpose is to try to prevent false duplicated bug reports by1932 * grossly estimating a GPU error state.1933 *1934 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine1935 * the hang if we could strip the GTT offset information from it.1936 *1937 * It's only a small step better than a random number in its current form.1938 */1939static u32 generate_ecode(const struct intel_engine_coredump *ee)1940{1941 /*1942 * IPEHR would be an ideal way to detect errors, as it's the gross1943 * measure of "the command that hung." However, has some very common1944 * synchronization commands which almost always appear in the case1945 * strictly a client bug. Use instdone to differentiate those some.1946 */1947 return ee ? ee->ipehr ^ ee->instdone.instdone : 0;1948}1949 1950static const char *error_msg(struct i915_gpu_coredump *error)1951{1952 struct intel_engine_coredump *first = NULL;1953 unsigned int hung_classes = 0;1954 struct intel_gt_coredump *gt;1955 int len;1956 1957 for (gt = error->gt; gt; gt = gt->next) {1958 struct intel_engine_coredump *cs;1959 1960 for (cs = gt->engine; cs; cs = cs->next) {1961 if (cs->hung) {1962 hung_classes |= BIT(cs->engine->uabi_class);1963 if (!first)1964 first = cs;1965 }1966 }1967 }1968 1969 len = scnprintf(error->error_msg, sizeof(error->error_msg),1970 "GPU HANG: ecode %d:%x:%08x",1971 GRAPHICS_VER(error->i915), hung_classes,1972 generate_ecode(first));1973 if (first && first->context.pid) {1974 /* Just show the first executing process, more is confusing */1975 len += scnprintf(error->error_msg + len,1976 sizeof(error->error_msg) - len,1977 ", in %s [%d]",1978 first->context.comm, first->context.pid);1979 }1980 1981 return error->error_msg;1982}1983 1984static void capture_gen(struct i915_gpu_coredump *error)1985{1986 struct drm_i915_private *i915 = error->i915;1987 1988 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);1989 error->suspended = pm_runtime_suspended(i915->drm.dev);1990 1991 error->iommu = i915_vtd_active(i915);1992 error->reset_count = i915_reset_count(&i915->gpu_error);1993 error->suspend_count = i915->suspend_count;1994 1995 i915_params_copy(&error->params, &i915->params);1996 intel_display_params_copy(&error->display_params);1997 memcpy(&error->device_info,1998 INTEL_INFO(i915),1999 sizeof(error->device_info));2000 memcpy(&error->runtime_info,2001 RUNTIME_INFO(i915),2002 sizeof(error->runtime_info));2003 memcpy(&error->display_device_info, DISPLAY_INFO(i915),2004 sizeof(error->display_device_info));2005 memcpy(&error->display_runtime_info, DISPLAY_RUNTIME_INFO(i915),2006 sizeof(error->display_runtime_info));2007 error->driver_caps = i915->caps;2008}2009 2010struct i915_gpu_coredump *2011i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)2012{2013 struct i915_gpu_coredump *error;2014 2015 if (!i915->params.error_capture)2016 return NULL;2017 2018 error = kzalloc(sizeof(*error), gfp);2019 if (!error)2020 return NULL;2021 2022 kref_init(&error->ref);2023 error->i915 = i915;2024 2025 error->time = ktime_get_real();2026 error->boottime = ktime_get_boottime();2027 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time);2028 error->capture = jiffies;2029 2030 capture_gen(error);2031 2032 return error;2033}2034 2035#define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))2036 2037struct intel_gt_coredump *2038intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)2039{2040 struct intel_gt_coredump *gc;2041 2042 gc = kzalloc(sizeof(*gc), gfp);2043 if (!gc)2044 return NULL;2045 2046 gc->_gt = gt;2047 gc->awake = intel_gt_pm_is_awake(gt);2048 2049 gt_record_display_regs(gc);2050 gt_record_global_nonguc_regs(gc);2051 2052 /*2053 * GuC dumps global, eng-class and eng-instance registers2054 * (that can change as part of engine state during execution)2055 * before an engine is reset due to a hung context.2056 * GuC captures and reports all three groups of registers2057 * together as a single set before the engine is reset.2058 * Thus, if GuC triggered the context reset we retrieve2059 * the register values as part of gt_record_engines.2060 */2061 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE))2062 gt_record_global_regs(gc);2063 2064 gt_record_fences(gc);2065 2066 return gc;2067}2068 2069struct i915_vma_compress *2070i915_vma_capture_prepare(struct intel_gt_coredump *gt)2071{2072 struct i915_vma_compress *compress;2073 2074 compress = kmalloc(sizeof(*compress), ALLOW_FAIL);2075 if (!compress)2076 return NULL;2077 2078 if (!compress_init(compress)) {2079 kfree(compress);2080 return NULL;2081 }2082 2083 return compress;2084}2085 2086void i915_vma_capture_finish(struct intel_gt_coredump *gt,2087 struct i915_vma_compress *compress)2088{2089 if (!compress)2090 return;2091 2092 compress_fini(compress);2093 kfree(compress);2094}2095 2096static struct i915_gpu_coredump *2097__i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)2098{2099 struct drm_i915_private *i915 = gt->i915;2100 struct i915_gpu_coredump *error;2101 2102 /* Check if GPU capture has been disabled */2103 error = READ_ONCE(i915->gpu_error.first_error);2104 if (IS_ERR(error))2105 return error;2106 2107 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);2108 if (!error)2109 return ERR_PTR(-ENOMEM);2110 2111 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);2112 if (error->gt) {2113 struct i915_vma_compress *compress;2114 2115 compress = i915_vma_capture_prepare(error->gt);2116 if (!compress) {2117 kfree(error->gt);2118 kfree(error);2119 return ERR_PTR(-ENOMEM);2120 }2121 2122 if (INTEL_INFO(i915)->has_gt_uc) {2123 error->gt->uc = gt_record_uc(error->gt, compress);2124 if (error->gt->uc) {2125 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)2126 error->gt->uc->guc.is_guc_capture = true;2127 else2128 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);2129 }2130 }2131 2132 gt_record_info(error->gt);2133 gt_record_engines(error->gt, engine_mask, compress, dump_flags);2134 2135 2136 i915_vma_capture_finish(error->gt, compress);2137 2138 error->simulated |= error->gt->simulated;2139 }2140 2141 error->overlay = intel_overlay_capture_error_state(i915);2142 2143 return error;2144}2145 2146static struct i915_gpu_coredump *2147i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)2148{2149 static DEFINE_MUTEX(capture_mutex);2150 int ret = mutex_lock_interruptible(&capture_mutex);2151 struct i915_gpu_coredump *dump;2152 2153 if (ret)2154 return ERR_PTR(ret);2155 2156 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);2157 mutex_unlock(&capture_mutex);2158 2159 return dump;2160}2161 2162void i915_error_state_store(struct i915_gpu_coredump *error)2163{2164 struct drm_i915_private *i915;2165 static bool warned;2166 2167 if (IS_ERR_OR_NULL(error))2168 return;2169 2170 i915 = error->i915;2171 drm_info(&i915->drm, "%s\n", error_msg(error));2172 2173 if (error->simulated ||2174 cmpxchg(&i915->gpu_error.first_error, NULL, error))2175 return;2176 2177 i915_gpu_coredump_get(error);2178 2179 if (!xchg(&warned, true) &&2180 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {2181 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");2182 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");2183 pr_info("Please see https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html for details.\n");2184 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");2185 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");2186 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",2187 i915->drm.primary->index);2188 }2189}2190 2191/**2192 * i915_capture_error_state - capture an error record for later analysis2193 * @gt: intel_gt which originated the hang2194 * @engine_mask: hung engines2195 * @dump_flags: dump flags2196 *2197 * Should be called when an error is detected (either a hang or an error2198 * interrupt) to capture error state from the time of the error. Fills2199 * out a structure which becomes available in debugfs for user level tools2200 * to pick up.2201 */2202void i915_capture_error_state(struct intel_gt *gt,2203 intel_engine_mask_t engine_mask, u32 dump_flags)2204{2205 struct i915_gpu_coredump *error;2206 2207 error = i915_gpu_coredump(gt, engine_mask, dump_flags);2208 if (IS_ERR(error)) {2209 cmpxchg(>->i915->gpu_error.first_error, NULL, error);2210 return;2211 }2212 2213 i915_error_state_store(error);2214 i915_gpu_coredump_put(error);2215}2216 2217static struct i915_gpu_coredump *2218i915_first_error_state(struct drm_i915_private *i915)2219{2220 struct i915_gpu_coredump *error;2221 2222 spin_lock_irq(&i915->gpu_error.lock);2223 error = i915->gpu_error.first_error;2224 if (!IS_ERR_OR_NULL(error))2225 i915_gpu_coredump_get(error);2226 spin_unlock_irq(&i915->gpu_error.lock);2227 2228 return error;2229}2230 2231void i915_reset_error_state(struct drm_i915_private *i915)2232{2233 struct i915_gpu_coredump *error;2234 2235 spin_lock_irq(&i915->gpu_error.lock);2236 error = i915->gpu_error.first_error;2237 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */2238 i915->gpu_error.first_error = NULL;2239 spin_unlock_irq(&i915->gpu_error.lock);2240 2241 if (!IS_ERR_OR_NULL(error))2242 i915_gpu_coredump_put(error);2243}2244 2245void i915_disable_error_state(struct drm_i915_private *i915, int err)2246{2247 spin_lock_irq(&i915->gpu_error.lock);2248 if (!i915->gpu_error.first_error)2249 i915->gpu_error.first_error = ERR_PTR(err);2250 spin_unlock_irq(&i915->gpu_error.lock);2251}2252 2253#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)2254void intel_klog_error_capture(struct intel_gt *gt,2255 intel_engine_mask_t engine_mask)2256{2257 static int g_count;2258 struct drm_i915_private *i915 = gt->i915;2259 struct i915_gpu_coredump *error;2260 intel_wakeref_t wakeref;2261 size_t buf_size = PAGE_SIZE * 128;2262 size_t pos_err;2263 char *buf, *ptr, *next;2264 int l_count = g_count++;2265 int line = 0;2266 2267 /* Can't allocate memory during a reset */2268 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {2269 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",2270 l_count, line++);2271 return;2272 }2273 2274 error = READ_ONCE(i915->gpu_error.first_error);2275 if (error) {2276 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n",2277 l_count, line++);2278 i915_reset_error_state(i915);2279 }2280 2281 with_intel_runtime_pm(&i915->runtime_pm, wakeref)2282 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);2283 2284 if (IS_ERR(error)) {2285 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n",2286 l_count, line++, PTR_ERR(error));2287 return;2288 }2289 2290 buf = kvmalloc(buf_size, GFP_KERNEL);2291 if (!buf) {2292 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n",2293 l_count, line++);2294 i915_gpu_coredump_put(error);2295 return;2296 }2297 2298 drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n",2299 l_count, line++, __builtin_return_address(0));2300 2301 /* Largest string length safe to print via dmesg */2302# define MAX_CHUNK 8002303 2304 pos_err = 0;2305 while (1) {2306 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1);2307 2308 if (got <= 0)2309 break;2310 2311 buf[got] = 0;2312 pos_err += got;2313 2314 ptr = buf;2315 while (got > 0) {2316 size_t count;2317 char tag[2];2318 2319 next = strnchr(ptr, got, '\n');2320 if (next) {2321 count = next - ptr;2322 *next = 0;2323 tag[0] = '>';2324 tag[1] = '<';2325 } else {2326 count = got;2327 tag[0] = '}';2328 tag[1] = '{';2329 }2330 2331 if (count > MAX_CHUNK) {2332 size_t pos;2333 char *ptr2 = ptr;2334 2335 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {2336 char chr = ptr[pos];2337 2338 ptr[pos] = 0;2339 drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n",2340 l_count, line++, ptr2);2341 ptr[pos] = chr;2342 ptr2 = ptr + pos;2343 2344 /*2345 * If spewing large amounts of data via a serial console,2346 * this can be a very slow process. So be friendly and try2347 * not to cause 'softlockup on CPU' problems.2348 */2349 cond_resched();2350 }2351 2352 if (ptr2 < (ptr + count))2353 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",2354 l_count, line++, tag[0], ptr2, tag[1]);2355 else if (tag[0] == '>')2356 drm_info(&i915->drm, "[Capture/%d.%d] ><\n",2357 l_count, line++);2358 } else {2359 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",2360 l_count, line++, tag[0], ptr, tag[1]);2361 }2362 2363 ptr = next;2364 got -= count;2365 if (next) {2366 ptr++;2367 got--;2368 }2369 2370 /* As above. */2371 cond_resched();2372 }2373 2374 if (got)2375 drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n",2376 l_count, line++, got);2377 }2378 2379 kvfree(buf);2380 2381 drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);2382}2383#endif2384 2385static ssize_t gpu_state_read(struct file *file, char __user *ubuf,2386 size_t count, loff_t *pos)2387{2388 struct i915_gpu_coredump *error;2389 ssize_t ret;2390 void *buf;2391 2392 error = file->private_data;2393 if (!error)2394 return 0;2395 2396 /* Bounce buffer required because of kernfs __user API convenience. */2397 buf = kmalloc(count, GFP_KERNEL);2398 if (!buf)2399 return -ENOMEM;2400 2401 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);2402 if (ret <= 0)2403 goto out;2404 2405 if (!copy_to_user(ubuf, buf, ret))2406 *pos += ret;2407 else2408 ret = -EFAULT;2409 2410out:2411 kfree(buf);2412 return ret;2413}2414 2415static int gpu_state_release(struct inode *inode, struct file *file)2416{2417 i915_gpu_coredump_put(file->private_data);2418 return 0;2419}2420 2421static int i915_gpu_info_open(struct inode *inode, struct file *file)2422{2423 struct drm_i915_private *i915 = inode->i_private;2424 struct i915_gpu_coredump *gpu;2425 intel_wakeref_t wakeref;2426 2427 gpu = NULL;2428 with_intel_runtime_pm(&i915->runtime_pm, wakeref)2429 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);2430 2431 if (IS_ERR(gpu))2432 return PTR_ERR(gpu);2433 2434 file->private_data = gpu;2435 return 0;2436}2437 2438static const struct file_operations i915_gpu_info_fops = {2439 .owner = THIS_MODULE,2440 .open = i915_gpu_info_open,2441 .read = gpu_state_read,2442 .llseek = default_llseek,2443 .release = gpu_state_release,2444};2445 2446static ssize_t2447i915_error_state_write(struct file *filp,2448 const char __user *ubuf,2449 size_t cnt,2450 loff_t *ppos)2451{2452 struct i915_gpu_coredump *error = filp->private_data;2453 2454 if (!error)2455 return 0;2456 2457 drm_dbg(&error->i915->drm, "Resetting error state\n");2458 i915_reset_error_state(error->i915);2459 2460 return cnt;2461}2462 2463static int i915_error_state_open(struct inode *inode, struct file *file)2464{2465 struct i915_gpu_coredump *error;2466 2467 error = i915_first_error_state(inode->i_private);2468 if (IS_ERR(error))2469 return PTR_ERR(error);2470 2471 file->private_data = error;2472 return 0;2473}2474 2475static const struct file_operations i915_error_state_fops = {2476 .owner = THIS_MODULE,2477 .open = i915_error_state_open,2478 .read = gpu_state_read,2479 .write = i915_error_state_write,2480 .llseek = default_llseek,2481 .release = gpu_state_release,2482};2483 2484void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)2485{2486 struct drm_minor *minor = i915->drm.primary;2487 2488 debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915,2489 &i915_error_state_fops);2490 debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915,2491 &i915_gpu_info_fops);2492}2493 2494static ssize_t error_state_read(struct file *filp, struct kobject *kobj,2495 struct bin_attribute *attr, char *buf,2496 loff_t off, size_t count)2497{2498 2499 struct device *kdev = kobj_to_dev(kobj);2500 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);2501 struct i915_gpu_coredump *gpu;2502 ssize_t ret = 0;2503 2504 /*2505 * FIXME: Concurrent clients triggering resets and reading + clearing2506 * dumps can cause inconsistent sysfs reads when a user calls in with a2507 * non-zero offset to complete a prior partial read but the2508 * gpu_coredump has been cleared or replaced.2509 */2510 2511 gpu = i915_first_error_state(i915);2512 if (IS_ERR(gpu)) {2513 ret = PTR_ERR(gpu);2514 } else if (gpu) {2515 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);2516 i915_gpu_coredump_put(gpu);2517 } else {2518 const char *str = "No error state collected\n";2519 size_t len = strlen(str);2520 2521 if (off < len) {2522 ret = min_t(size_t, count, len - off);2523 memcpy(buf, str + off, ret);2524 }2525 }2526 2527 return ret;2528}2529 2530static ssize_t error_state_write(struct file *file, struct kobject *kobj,2531 struct bin_attribute *attr, char *buf,2532 loff_t off, size_t count)2533{2534 struct device *kdev = kobj_to_dev(kobj);2535 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);2536 2537 drm_dbg(&dev_priv->drm, "Resetting error state\n");2538 i915_reset_error_state(dev_priv);2539 2540 return count;2541}2542 2543static const struct bin_attribute error_state_attr = {2544 .attr.name = "error",2545 .attr.mode = S_IRUSR | S_IWUSR,2546 .size = 0,2547 .read = error_state_read,2548 .write = error_state_write,2549};2550 2551void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)2552{2553 struct device *kdev = i915->drm.primary->kdev;2554 2555 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))2556 drm_err(&i915->drm, "error_state sysfs setup failed\n");2557}2558 2559void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)2560{2561 struct device *kdev = i915->drm.primary->kdev;2562 2563 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);2564}2565