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1/*2 * SPDX-License-Identifier: MIT3 *4 * Copyright © 2017-2018 Intel Corporation5 */6 7#ifndef __I915_PMU_H__8#define __I915_PMU_H__9 10#include <linux/hrtimer.h>11#include <linux/perf_event.h>12#include <linux/spinlock_types.h>13#include <uapi/drm/i915_drm.h>14 15struct drm_i915_private;16struct intel_gt;17 18/*19 * Non-engine events that we need to track enabled-disabled transition and20 * current state.21 */22enum i915_pmu_tracked_events {23 __I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,24 __I915_PMU_REQUESTED_FREQUENCY_ENABLED,25 __I915_PMU_RC6_RESIDENCY_ENABLED,26 __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */27};28 29/*30 * Slots used from the sampling timer (non-engine events) with some extras for31 * convenience.32 */33enum {34 __I915_SAMPLE_FREQ_ACT = 0,35 __I915_SAMPLE_FREQ_REQ,36 __I915_SAMPLE_RC6,37 __I915_SAMPLE_RC6_LAST_REPORTED,38 __I915_NUM_PMU_SAMPLERS39};40 41#define I915_PMU_MAX_GT 242 43/*44 * How many different events we track in the global PMU mask.45 *46 * It is also used to know to needed number of event reference counters.47 */48#define I915_PMU_MASK_BITS \49 (I915_ENGINE_SAMPLE_COUNT + \50 I915_PMU_MAX_GT * __I915_PMU_TRACKED_EVENT_COUNT)51 52#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)53 54struct i915_pmu_sample {55 u64 cur;56};57 58struct i915_pmu {59 /**60 * @cpuhp: Struct used for CPU hotplug handling.61 */62 struct {63 struct hlist_node node;64 unsigned int cpu;65 } cpuhp;66 /**67 * @base: PMU base.68 */69 struct pmu base;70 /**71 * @closed: i915 is unregistering.72 */73 bool closed;74 /**75 * @name: Name as registered with perf core.76 */77 const char *name;78 /**79 * @lock: Lock protecting enable mask and ref count handling.80 */81 spinlock_t lock;82 /**83 * @unparked: GT unparked mask.84 */85 unsigned int unparked;86 /**87 * @timer: Timer for internal i915 PMU sampling.88 */89 struct hrtimer timer;90 /**91 * @enable: Bitmask of specific enabled events.92 *93 * For some events we need to track their state and do some internal94 * house keeping.95 *96 * Each engine event sampler type and event listed in enum97 * i915_pmu_tracked_events gets a bit in this field.98 *99 * Low bits are engine samplers and other events continue from there.100 */101 u32 enable;102 103 /**104 * @timer_last:105 *106 * Timestmap of the previous timer invocation.107 */108 ktime_t timer_last;109 110 /**111 * @enable_count: Reference counts for the enabled events.112 *113 * Array indices are mapped in the same way as bits in the @enable field114 * and they are used to control sampling on/off when multiple clients115 * are using the PMU API.116 */117 unsigned int enable_count[I915_PMU_MASK_BITS];118 /**119 * @timer_enabled: Should the internal sampling timer be running.120 */121 bool timer_enabled;122 /**123 * @sample: Current and previous (raw) counters for sampling events.124 *125 * These counters are updated from the i915 PMU sampling timer.126 *127 * Only global counters are held here, while the per-engine ones are in128 * struct intel_engine_cs.129 */130 struct i915_pmu_sample sample[I915_PMU_MAX_GT][__I915_NUM_PMU_SAMPLERS];131 /**132 * @sleep_last: Last time GT parked for RC6 estimation.133 */134 ktime_t sleep_last[I915_PMU_MAX_GT];135 /**136 * @irq_count: Number of interrupts137 *138 * Intentionally unsigned long to avoid atomics or heuristics on 32bit.139 * 4e9 interrupts are a lot and postprocessing can really deal with an140 * occasional wraparound easily. It's 32bit after all.141 */142 unsigned long irq_count;143 /**144 * @events_attr_group: Device events attribute group.145 */146 struct attribute_group events_attr_group;147 /**148 * @i915_attr: Memory block holding device attributes.149 */150 void *i915_attr;151 /**152 * @pmu_attr: Memory block holding device attributes.153 */154 void *pmu_attr;155};156 157#ifdef CONFIG_PERF_EVENTS158int i915_pmu_init(void);159void i915_pmu_exit(void);160void i915_pmu_register(struct drm_i915_private *i915);161void i915_pmu_unregister(struct drm_i915_private *i915);162void i915_pmu_gt_parked(struct intel_gt *gt);163void i915_pmu_gt_unparked(struct intel_gt *gt);164#else165static inline int i915_pmu_init(void) { return 0; }166static inline void i915_pmu_exit(void) {}167static inline void i915_pmu_register(struct drm_i915_private *i915) {}168static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}169static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}170static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}171#endif172 173#endif174