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1/*2 * Copyright © 2014-2017 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS21 * IN THE SOFTWARE.22 *23 */24 25#ifndef _INTEL_DEVICE_INFO_H_26#define _INTEL_DEVICE_INFO_H_27 28#include <uapi/drm/i915_drm.h>29 30#include "intel_step.h"31 32#include "gt/intel_engine_types.h"33#include "gt/intel_context_types.h"34#include "gt/intel_sseu.h"35 36#include "gem/i915_gem_object_types.h"37 38struct drm_printer;39struct drm_i915_private;40struct intel_gt_definition;41 42/* Keep in gen based order, and chronological order within a gen */43enum intel_platform {44 INTEL_PLATFORM_UNINITIALIZED = 0,45 /* gen2 */46 INTEL_I830,47 INTEL_I845G,48 INTEL_I85X,49 INTEL_I865G,50 /* gen3 */51 INTEL_I915G,52 INTEL_I915GM,53 INTEL_I945G,54 INTEL_I945GM,55 INTEL_G33,56 INTEL_PINEVIEW,57 /* gen4 */58 INTEL_I965G,59 INTEL_I965GM,60 INTEL_G45,61 INTEL_GM45,62 /* gen5 */63 INTEL_IRONLAKE,64 /* gen6 */65 INTEL_SANDYBRIDGE,66 /* gen7 */67 INTEL_IVYBRIDGE,68 INTEL_VALLEYVIEW,69 INTEL_HASWELL,70 /* gen8 */71 INTEL_BROADWELL,72 INTEL_CHERRYVIEW,73 /* gen9 */74 INTEL_SKYLAKE,75 INTEL_BROXTON,76 INTEL_KABYLAKE,77 INTEL_GEMINILAKE,78 INTEL_COFFEELAKE,79 INTEL_COMETLAKE,80 /* gen11 */81 INTEL_ICELAKE,82 INTEL_ELKHARTLAKE,83 INTEL_JASPERLAKE,84 /* gen12 */85 INTEL_TIGERLAKE,86 INTEL_ROCKETLAKE,87 INTEL_DG1,88 INTEL_ALDERLAKE_S,89 INTEL_ALDERLAKE_P,90 INTEL_DG2,91 INTEL_METEORLAKE,92 INTEL_MAX_PLATFORMS93};94 95/*96 * Subplatform bits share the same namespace per parent platform. In other words97 * it is fine for the same bit to be used on multiple parent platforms.98 */99 100#define INTEL_SUBPLATFORM_BITS (3)101#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)102 103/* HSW/BDW/SKL/KBL/CFL */104#define INTEL_SUBPLATFORM_ULT (0)105#define INTEL_SUBPLATFORM_ULX (1)106 107/* ICL */108#define INTEL_SUBPLATFORM_PORTF (0)109 110/* TGL */111#define INTEL_SUBPLATFORM_UY (0)112 113/* DG2 */114#define INTEL_SUBPLATFORM_G10 0115#define INTEL_SUBPLATFORM_G11 1116#define INTEL_SUBPLATFORM_G12 2117 118/* ADL */119#define INTEL_SUBPLATFORM_RPL 0120 121/* ADL-P */122/*123 * As #define INTEL_SUBPLATFORM_RPL 0 will apply124 * here too, SUBPLATFORM_N will have different125 * bit set126 */127#define INTEL_SUBPLATFORM_N 1128#define INTEL_SUBPLATFORM_RPLU 2129 130/* MTL */131#define INTEL_SUBPLATFORM_ARL_H 0132#define INTEL_SUBPLATFORM_ARL_U 1133#define INTEL_SUBPLATFORM_ARL_S 2134 135enum intel_ppgtt_type {136 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,137 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,138 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,139};140 141#define DEV_INFO_FOR_EACH_FLAG(func) \142 func(is_mobile); \143 func(is_lp); \144 func(require_force_probe); \145 func(is_dgfx); \146 /* Keep has_* in alphabetical order */ \147 func(has_64bit_reloc); \148 func(has_64k_pages); \149 func(gpu_reset_clobbers_display); \150 func(has_reset_engine); \151 func(has_3d_pipeline); \152 func(has_flat_ccs); \153 func(has_global_mocs); \154 func(has_gmd_id); \155 func(has_gt_uc); \156 func(has_heci_pxp); \157 func(has_heci_gscfi); \158 func(has_guc_deprivilege); \159 func(has_guc_tlb_invalidation); \160 func(has_l3_ccs_read); \161 func(has_l3_dpf); \162 func(has_llc); \163 func(has_logical_ring_contexts); \164 func(has_logical_ring_elsq); \165 func(has_media_ratio_mode); \166 func(has_mslice_steering); \167 func(has_oa_bpc_reporting); \168 func(has_oa_slice_contrib_limits); \169 func(has_oam); \170 func(has_one_eu_per_fuse_bit); \171 func(has_pxp); \172 func(has_rc6); \173 func(has_rc6p); \174 func(has_rps); \175 func(has_runtime_pm); \176 func(has_snoop); \177 func(has_coherent_ggtt); \178 func(tuning_thread_rr_after_dep); \179 func(unfenced_needs_alignment); \180 func(hws_needs_physical);181 182struct intel_ip_version {183 u8 ver;184 u8 rel;185 u8 step;186};187 188struct intel_runtime_info {189 /*190 * Single "graphics" IP version that represents191 * render, compute and copy behavior.192 */193 struct {194 struct intel_ip_version ip;195 } graphics;196 struct {197 struct intel_ip_version ip;198 } media;199 200 /*201 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into202 * single runtime conditionals, and also to provide groundwork for203 * future per platform, or per SKU build optimizations.204 *205 * Array can be extended when necessary if the corresponding206 * BUILD_BUG_ON is hit.207 */208 u32 platform_mask[2];209 210 u16 device_id;211 212 struct intel_step_info step;213 214 unsigned int page_sizes; /* page sizes supported by the HW */215 216 enum intel_ppgtt_type ppgtt_type;217 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */218 219 bool has_pooled_eu;220};221 222struct intel_device_info {223 enum intel_platform platform;224 225 unsigned int dma_mask_size; /* available DMA address bits */226 227 const struct intel_gt_definition *extra_gt_list;228 229 u8 gt; /* GT number, 0 if undefined */230 231 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */232 u32 memory_regions; /* regions supported by the HW */233 234#define DEFINE_FLAG(name) u8 name:1235 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);236#undef DEFINE_FLAG237 238 /*239 * Initial runtime info. Do not access outside of i915_driver_create().240 */241 const struct intel_runtime_info __runtime;242 243 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];244 u32 max_pat_index;245};246 247struct intel_driver_caps {248 unsigned int scheduler;249 bool has_logical_contexts:1;250};251 252const char *intel_platform_name(enum intel_platform platform);253 254void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,255 const struct intel_device_info *match_info);256void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);257void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);258 259void intel_device_info_print(const struct intel_device_info *info,260 const struct intel_runtime_info *runtime,261 struct drm_printer *p);262 263void intel_driver_caps_print(const struct intel_driver_caps *caps,264 struct drm_printer *p);265 266#endif267