1312 lines · c
1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2020 Intel Corporation4 */5 6#include "display/bxt_dpio_phy_regs.h"7#include "display/i9xx_plane_regs.h"8#include "display/intel_audio_regs.h"9#include "display/intel_backlight_regs.h"10#include "display/intel_color_regs.h"11#include "display/intel_cursor_regs.h"12#include "display/intel_display_types.h"13#include "display/intel_dmc_regs.h"14#include "display/intel_dp_aux_regs.h"15#include "display/intel_dpio_phy.h"16#include "display/intel_fbc_regs.h"17#include "display/intel_fdi_regs.h"18#include "display/intel_lvds_regs.h"19#include "display/intel_psr_regs.h"20#include "display/intel_sprite_regs.h"21#include "display/skl_universal_plane_regs.h"22#include "display/skl_watermark_regs.h"23#include "display/vlv_dsi_pll_regs.h"24#include "gt/intel_engine_regs.h"25#include "gt/intel_gt_regs.h"26#include "gvt/reg.h"27 28#include "i915_drv.h"29#include "i915_pvinfo.h"30#include "i915_reg.h"31#include "intel_gvt.h"32#include "intel_mchbar_regs.h"33 34#define MMIO_F(reg, s) do { \35 int ret; \36 ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \37 if (ret) \38 return ret; \39} while (0)40 41#define MMIO_D(reg) MMIO_F(reg, 4)42 43#define MMIO_RING_F(prefix, s) do { \44 MMIO_F(prefix(RENDER_RING_BASE), s); \45 MMIO_F(prefix(BLT_RING_BASE), s); \46 MMIO_F(prefix(GEN6_BSD_RING_BASE), s); \47 MMIO_F(prefix(VEBOX_RING_BASE), s); \48 if (HAS_ENGINE(to_gt(iter->i915), VCS1)) \49 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s); \50} while (0)51 52#define MMIO_RING_D(prefix) \53 MMIO_RING_F(prefix, 4)54 55static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)56{57 struct drm_i915_private *dev_priv = iter->i915;58 59 MMIO_RING_D(RING_IMR);60 MMIO_D(SDEIMR);61 MMIO_D(SDEIER);62 MMIO_D(SDEIIR);63 MMIO_D(SDEISR);64 MMIO_RING_D(RING_HWSTAM);65 MMIO_D(BSD_HWS_PGA_GEN7);66 MMIO_D(BLT_HWS_PGA_GEN7);67 MMIO_D(VEBOX_HWS_PGA_GEN7);68 69#define RING_REG(base) _MMIO((base) + 0x28)70 MMIO_RING_D(RING_REG);71#undef RING_REG72 73#define RING_REG(base) _MMIO((base) + 0x134)74 MMIO_RING_D(RING_REG);75#undef RING_REG76 77#define RING_REG(base) _MMIO((base) + 0x6c)78 MMIO_RING_D(RING_REG);79#undef RING_REG80 MMIO_D(_MMIO(0x2148));81 MMIO_D(CCID(RENDER_RING_BASE));82 MMIO_D(_MMIO(0x12198));83 MMIO_D(GEN7_CXT_SIZE);84 MMIO_RING_D(RING_TAIL);85 MMIO_RING_D(RING_HEAD);86 MMIO_RING_D(RING_CTL);87 MMIO_RING_D(RING_ACTHD);88 MMIO_RING_D(RING_START);89 90 /* RING MODE */91#define RING_REG(base) _MMIO((base) + 0x29c)92 MMIO_RING_D(RING_REG);93#undef RING_REG94 95 MMIO_RING_D(RING_MI_MODE);96 MMIO_RING_D(RING_INSTPM);97 MMIO_RING_D(RING_TIMESTAMP);98 MMIO_RING_D(RING_TIMESTAMP_UDW);99 MMIO_D(GEN7_GT_MODE);100 MMIO_D(CACHE_MODE_0_GEN7);101 MMIO_D(CACHE_MODE_1);102 MMIO_D(CACHE_MODE_0);103 MMIO_D(_MMIO(0x2124));104 MMIO_D(_MMIO(0x20dc));105 MMIO_D(_3D_CHICKEN3);106 MMIO_D(_MMIO(0x2088));107 MMIO_D(FF_SLICE_CS_CHICKEN2);108 MMIO_D(_MMIO(0x2470));109 MMIO_D(GAM_ECOCHK);110 MMIO_D(GEN7_COMMON_SLICE_CHICKEN1);111 MMIO_D(COMMON_SLICE_CHICKEN2);112 MMIO_D(_MMIO(0x9030));113 MMIO_D(_MMIO(0x20a0));114 MMIO_D(_MMIO(0x2420));115 MMIO_D(_MMIO(0x2430));116 MMIO_D(_MMIO(0x2434));117 MMIO_D(_MMIO(0x2438));118 MMIO_D(_MMIO(0x243c));119 MMIO_D(_MMIO(0x7018));120 MMIO_D(HSW_HALF_SLICE_CHICKEN3);121 MMIO_D(GEN7_HALF_SLICE_CHICKEN1);122 /* display */123 MMIO_F(_MMIO(0x60220), 0x20);124 MMIO_D(_MMIO(0x602a0));125 MMIO_D(_MMIO(0x65050));126 MMIO_D(_MMIO(0x650b4));127 MMIO_D(_MMIO(0xc4040));128 MMIO_D(DERRMR);129 MMIO_D(PIPEDSL(dev_priv, PIPE_A));130 MMIO_D(PIPEDSL(dev_priv, PIPE_B));131 MMIO_D(PIPEDSL(dev_priv, PIPE_C));132 MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));133 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));134 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));135 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));136 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));137 MMIO_D(PIPESTAT(dev_priv, PIPE_A));138 MMIO_D(PIPESTAT(dev_priv, PIPE_B));139 MMIO_D(PIPESTAT(dev_priv, PIPE_C));140 MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));141 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A));142 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B));143 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C));144 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP));145 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));146 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));147 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));148 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));149 MMIO_D(CURCNTR(dev_priv, PIPE_A));150 MMIO_D(CURCNTR(dev_priv, PIPE_B));151 MMIO_D(CURCNTR(dev_priv, PIPE_C));152 MMIO_D(CURPOS(dev_priv, PIPE_A));153 MMIO_D(CURPOS(dev_priv, PIPE_B));154 MMIO_D(CURPOS(dev_priv, PIPE_C));155 MMIO_D(CURBASE(dev_priv, PIPE_A));156 MMIO_D(CURBASE(dev_priv, PIPE_B));157 MMIO_D(CURBASE(dev_priv, PIPE_C));158 MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A));159 MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_B));160 MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C));161 MMIO_D(_MMIO(0x700ac));162 MMIO_D(_MMIO(0x710ac));163 MMIO_D(_MMIO(0x720ac));164 MMIO_D(_MMIO(0x70090));165 MMIO_D(_MMIO(0x70094));166 MMIO_D(_MMIO(0x70098));167 MMIO_D(_MMIO(0x7009c));168 MMIO_D(DSPCNTR(dev_priv, PIPE_A));169 MMIO_D(DSPADDR(dev_priv, PIPE_A));170 MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));171 MMIO_D(DSPPOS(dev_priv, PIPE_A));172 MMIO_D(DSPSIZE(dev_priv, PIPE_A));173 MMIO_D(DSPSURF(dev_priv, PIPE_A));174 MMIO_D(DSPOFFSET(dev_priv, PIPE_A));175 MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));176 MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));177 MMIO_D(DSPCNTR(dev_priv, PIPE_B));178 MMIO_D(DSPADDR(dev_priv, PIPE_B));179 MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));180 MMIO_D(DSPPOS(dev_priv, PIPE_B));181 MMIO_D(DSPSIZE(dev_priv, PIPE_B));182 MMIO_D(DSPSURF(dev_priv, PIPE_B));183 MMIO_D(DSPOFFSET(dev_priv, PIPE_B));184 MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));185 MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));186 MMIO_D(DSPCNTR(dev_priv, PIPE_C));187 MMIO_D(DSPADDR(dev_priv, PIPE_C));188 MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));189 MMIO_D(DSPPOS(dev_priv, PIPE_C));190 MMIO_D(DSPSIZE(dev_priv, PIPE_C));191 MMIO_D(DSPSURF(dev_priv, PIPE_C));192 MMIO_D(DSPOFFSET(dev_priv, PIPE_C));193 MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));194 MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));195 MMIO_D(SPRCTL(PIPE_A));196 MMIO_D(SPRLINOFF(PIPE_A));197 MMIO_D(SPRSTRIDE(PIPE_A));198 MMIO_D(SPRPOS(PIPE_A));199 MMIO_D(SPRSIZE(PIPE_A));200 MMIO_D(SPRKEYVAL(PIPE_A));201 MMIO_D(SPRKEYMSK(PIPE_A));202 MMIO_D(SPRSURF(PIPE_A));203 MMIO_D(SPRKEYMAX(PIPE_A));204 MMIO_D(SPROFFSET(PIPE_A));205 MMIO_D(SPRSCALE(PIPE_A));206 MMIO_D(SPRSURFLIVE(PIPE_A));207 MMIO_D(REG_50080(PIPE_A, PLANE_SPRITE0));208 MMIO_D(SPRCTL(PIPE_B));209 MMIO_D(SPRLINOFF(PIPE_B));210 MMIO_D(SPRSTRIDE(PIPE_B));211 MMIO_D(SPRPOS(PIPE_B));212 MMIO_D(SPRSIZE(PIPE_B));213 MMIO_D(SPRKEYVAL(PIPE_B));214 MMIO_D(SPRKEYMSK(PIPE_B));215 MMIO_D(SPRSURF(PIPE_B));216 MMIO_D(SPRKEYMAX(PIPE_B));217 MMIO_D(SPROFFSET(PIPE_B));218 MMIO_D(SPRSCALE(PIPE_B));219 MMIO_D(SPRSURFLIVE(PIPE_B));220 MMIO_D(REG_50080(PIPE_B, PLANE_SPRITE0));221 MMIO_D(SPRCTL(PIPE_C));222 MMIO_D(SPRLINOFF(PIPE_C));223 MMIO_D(SPRSTRIDE(PIPE_C));224 MMIO_D(SPRPOS(PIPE_C));225 MMIO_D(SPRSIZE(PIPE_C));226 MMIO_D(SPRKEYVAL(PIPE_C));227 MMIO_D(SPRKEYMSK(PIPE_C));228 MMIO_D(SPRSURF(PIPE_C));229 MMIO_D(SPRKEYMAX(PIPE_C));230 MMIO_D(SPROFFSET(PIPE_C));231 MMIO_D(SPRSCALE(PIPE_C));232 MMIO_D(SPRSURFLIVE(PIPE_C));233 MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));234 MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));235 MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));236 MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));237 MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));238 MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));239 MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));240 MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));241 MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));242 MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));243 MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));244 MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));245 MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));246 MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));247 MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));248 MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));249 MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));250 MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));251 MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));252 MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));253 MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));254 MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));255 MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));256 MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));257 MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));258 MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));259 MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));260 MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));261 MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));262 MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));263 MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));264 MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));265 MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));266 MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));267 MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));268 MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));269 MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));270 MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));271 MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));272 MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));273 MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));274 MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));275 MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));276 MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));277 MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));278 MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));279 MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));280 MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));281 MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));282 MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));283 MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));284 MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));285 MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));286 MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));287 MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));288 MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));289 MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));290 MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));291 MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));292 MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));293 MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));294 MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));295 MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));296 MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));297 MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));298 MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));299 MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));300 MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));301 MMIO_D(PF_CTL(PIPE_A));302 MMIO_D(PF_WIN_SZ(PIPE_A));303 MMIO_D(PF_WIN_POS(PIPE_A));304 MMIO_D(PF_VSCALE(PIPE_A));305 MMIO_D(PF_HSCALE(PIPE_A));306 MMIO_D(PF_CTL(PIPE_B));307 MMIO_D(PF_WIN_SZ(PIPE_B));308 MMIO_D(PF_WIN_POS(PIPE_B));309 MMIO_D(PF_VSCALE(PIPE_B));310 MMIO_D(PF_HSCALE(PIPE_B));311 MMIO_D(PF_CTL(PIPE_C));312 MMIO_D(PF_WIN_SZ(PIPE_C));313 MMIO_D(PF_WIN_POS(PIPE_C));314 MMIO_D(PF_VSCALE(PIPE_C));315 MMIO_D(PF_HSCALE(PIPE_C));316 MMIO_D(WM0_PIPE_ILK(PIPE_A));317 MMIO_D(WM0_PIPE_ILK(PIPE_B));318 MMIO_D(WM0_PIPE_ILK(PIPE_C));319 MMIO_D(WM1_LP_ILK);320 MMIO_D(WM2_LP_ILK);321 MMIO_D(WM3_LP_ILK);322 MMIO_D(WM1S_LP_ILK);323 MMIO_D(WM2S_LP_IVB);324 MMIO_D(WM3S_LP_IVB);325 MMIO_D(BLC_PWM_CPU_CTL2);326 MMIO_D(BLC_PWM_CPU_CTL);327 MMIO_D(BLC_PWM_PCH_CTL1);328 MMIO_D(BLC_PWM_PCH_CTL2);329 MMIO_D(_MMIO(0x48268));330 MMIO_F(PCH_GMBUS0, 4 * 4);331 MMIO_F(PCH_GPIO_BASE, 6 * 4);332 MMIO_F(_MMIO(0xe4f00), 0x28);333 MMIO_D(_MMIO(_PCH_TRANSACONF));334 MMIO_D(_MMIO(_PCH_TRANSBCONF));335 MMIO_D(FDI_RX_IIR(PIPE_A));336 MMIO_D(FDI_RX_IIR(PIPE_B));337 MMIO_D(FDI_RX_IIR(PIPE_C));338 MMIO_D(FDI_RX_IMR(PIPE_A));339 MMIO_D(FDI_RX_IMR(PIPE_B));340 MMIO_D(FDI_RX_IMR(PIPE_C));341 MMIO_D(FDI_RX_CTL(PIPE_A));342 MMIO_D(FDI_RX_CTL(PIPE_B));343 MMIO_D(FDI_RX_CTL(PIPE_C));344 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A));345 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A));346 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A));347 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A));348 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A));349 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A));350 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A));351 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B));352 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B));353 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B));354 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B));355 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B));356 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B));357 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B));358 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1));359 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1));360 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2));361 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2));362 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1));363 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1));364 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2));365 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2));366 MMIO_D(TRANS_DP_CTL(PIPE_A));367 MMIO_D(TRANS_DP_CTL(PIPE_B));368 MMIO_D(TRANS_DP_CTL(PIPE_C));369 MMIO_D(TVIDEO_DIP_CTL(PIPE_A));370 MMIO_D(TVIDEO_DIP_DATA(PIPE_A));371 MMIO_D(TVIDEO_DIP_GCP(PIPE_A));372 MMIO_D(TVIDEO_DIP_CTL(PIPE_B));373 MMIO_D(TVIDEO_DIP_DATA(PIPE_B));374 MMIO_D(TVIDEO_DIP_GCP(PIPE_B));375 MMIO_D(TVIDEO_DIP_CTL(PIPE_C));376 MMIO_D(TVIDEO_DIP_DATA(PIPE_C));377 MMIO_D(TVIDEO_DIP_GCP(PIPE_C));378 MMIO_D(_MMIO(_FDI_RXA_MISC));379 MMIO_D(_MMIO(_FDI_RXB_MISC));380 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1));381 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2));382 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1));383 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2));384 MMIO_D(PCH_PP_CONTROL);385 MMIO_D(PCH_PP_DIVISOR);386 MMIO_D(PCH_PP_STATUS);387 MMIO_D(PCH_LVDS);388 MMIO_D(_MMIO(_PCH_DPLL_A));389 MMIO_D(_MMIO(_PCH_DPLL_B));390 MMIO_D(_MMIO(_PCH_FPA0));391 MMIO_D(_MMIO(_PCH_FPA1));392 MMIO_D(_MMIO(_PCH_FPB0));393 MMIO_D(_MMIO(_PCH_FPB1));394 MMIO_D(PCH_DREF_CONTROL);395 MMIO_D(PCH_RAWCLK_FREQ);396 MMIO_D(PCH_DPLL_SEL);397 MMIO_D(_MMIO(0x61208));398 MMIO_D(_MMIO(0x6120c));399 MMIO_D(PCH_PP_ON_DELAYS);400 MMIO_D(PCH_PP_OFF_DELAYS);401 MMIO_D(_MMIO(0xe651c));402 MMIO_D(_MMIO(0xe661c));403 MMIO_D(_MMIO(0xe671c));404 MMIO_D(_MMIO(0xe681c));405 MMIO_D(_MMIO(0xe6c04));406 MMIO_D(_MMIO(0xe6e1c));407 MMIO_D(PCH_PORT_HOTPLUG);408 MMIO_D(LCPLL_CTL);409 MMIO_D(FUSE_STRAP);410 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL);411 MMIO_D(DISP_ARB_CTL);412 MMIO_D(DISP_ARB_CTL2);413 MMIO_D(ILK_DISPLAY_CHICKEN1);414 MMIO_D(ILK_DISPLAY_CHICKEN2);415 MMIO_D(ILK_DSPCLK_GATE_D);416 MMIO_D(SOUTH_CHICKEN1);417 MMIO_D(SOUTH_CHICKEN2);418 MMIO_D(_MMIO(_TRANSA_CHICKEN1));419 MMIO_D(_MMIO(_TRANSB_CHICKEN1));420 MMIO_D(SOUTH_DSPCLK_GATE_D);421 MMIO_D(_MMIO(_TRANSA_CHICKEN2));422 MMIO_D(_MMIO(_TRANSB_CHICKEN2));423 MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A));424 MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A));425 MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A));426 MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A));427 MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A));428 MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A));429 MMIO_D(ILK_FBC_RT_BASE);430 MMIO_D(IPS_CTL);431 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A));432 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A));433 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A));434 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A));435 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A));436 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A));437 MMIO_D(PIPE_CSC_MODE(PIPE_A));438 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A));439 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A));440 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A));441 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A));442 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A));443 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A));444 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B));445 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B));446 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B));447 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B));448 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B));449 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B));450 MMIO_D(PIPE_CSC_MODE(PIPE_B));451 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B));452 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B));453 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B));454 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B));455 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B));456 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B));457 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C));458 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C));459 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C));460 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C));461 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C));462 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C));463 MMIO_D(PIPE_CSC_MODE(PIPE_C));464 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C));465 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C));466 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C));467 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C));468 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C));469 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C));470 MMIO_D(PREC_PAL_INDEX(PIPE_A));471 MMIO_D(PREC_PAL_DATA(PIPE_A));472 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3);473 MMIO_D(PREC_PAL_INDEX(PIPE_B));474 MMIO_D(PREC_PAL_DATA(PIPE_B));475 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3);476 MMIO_D(PREC_PAL_INDEX(PIPE_C));477 MMIO_D(PREC_PAL_DATA(PIPE_C));478 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3);479 MMIO_D(_MMIO(0x60110));480 MMIO_D(_MMIO(0x61110));481 MMIO_F(_MMIO(0x70400), 0x40);482 MMIO_F(_MMIO(0x71400), 0x40);483 MMIO_F(_MMIO(0x72400), 0x40);484 MMIO_D(WM_LINETIME(PIPE_A));485 MMIO_D(WM_LINETIME(PIPE_B));486 MMIO_D(WM_LINETIME(PIPE_C));487 MMIO_D(SPLL_CTL);488 MMIO_D(_MMIO(_WRPLL_CTL1));489 MMIO_D(_MMIO(_WRPLL_CTL2));490 MMIO_D(PORT_CLK_SEL(PORT_A));491 MMIO_D(PORT_CLK_SEL(PORT_B));492 MMIO_D(PORT_CLK_SEL(PORT_C));493 MMIO_D(PORT_CLK_SEL(PORT_D));494 MMIO_D(PORT_CLK_SEL(PORT_E));495 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A));496 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B));497 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C));498 MMIO_D(HSW_NDE_RSTWRN_OPT);499 MMIO_D(_MMIO(0x46508));500 MMIO_D(_MMIO(0x49080));501 MMIO_D(_MMIO(0x49180));502 MMIO_D(_MMIO(0x49280));503 MMIO_F(_MMIO(0x49090), 0x14);504 MMIO_F(_MMIO(0x49190), 0x14);505 MMIO_F(_MMIO(0x49290), 0x14);506 MMIO_D(GAMMA_MODE(PIPE_A));507 MMIO_D(GAMMA_MODE(PIPE_B));508 MMIO_D(GAMMA_MODE(PIPE_C));509 MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A));510 MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B));511 MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C));512 MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A));513 MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B));514 MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));515 MMIO_D(SFUSE_STRAP);516 MMIO_D(SBI_ADDR);517 MMIO_D(SBI_DATA);518 MMIO_D(SBI_CTL_STAT);519 MMIO_D(PIXCLK_GATE);520 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);521 MMIO_D(DDI_BUF_CTL(PORT_A));522 MMIO_D(DDI_BUF_CTL(PORT_B));523 MMIO_D(DDI_BUF_CTL(PORT_C));524 MMIO_D(DDI_BUF_CTL(PORT_D));525 MMIO_D(DDI_BUF_CTL(PORT_E));526 MMIO_D(DP_TP_CTL(PORT_A));527 MMIO_D(DP_TP_CTL(PORT_B));528 MMIO_D(DP_TP_CTL(PORT_C));529 MMIO_D(DP_TP_CTL(PORT_D));530 MMIO_D(DP_TP_CTL(PORT_E));531 MMIO_D(DP_TP_STATUS(PORT_A));532 MMIO_D(DP_TP_STATUS(PORT_B));533 MMIO_D(DP_TP_STATUS(PORT_C));534 MMIO_D(DP_TP_STATUS(PORT_D));535 MMIO_D(DP_TP_STATUS(PORT_E));536 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50);537 MMIO_F(_MMIO(0x64e60), 0x50);538 MMIO_F(_MMIO(0x64eC0), 0x50);539 MMIO_F(_MMIO(0x64f20), 0x50);540 MMIO_F(_MMIO(0x64f80), 0x50);541 MMIO_D(HSW_AUD_CFG(PIPE_A));542 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD);543 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A));544 MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_A));545 MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_B));546 MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_C));547 MMIO_D(_MMIO(_TRANS_DDI_FUNC_CTL_EDP));548 MMIO_D(_MMIO(_TRANSA_MSA_MISC));549 MMIO_D(_MMIO(_TRANSB_MSA_MISC));550 MMIO_D(_MMIO(_TRANSC_MSA_MISC));551 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC));552 MMIO_D(FORCEWAKE);553 MMIO_D(FORCEWAKE_ACK);554 MMIO_D(GEN6_GT_CORE_STATUS);555 MMIO_D(GEN6_GT_THREAD_STATUS_REG);556 MMIO_D(GTFIFODBG);557 MMIO_D(GTFIFOCTL);558 MMIO_D(ECOBUS);559 MMIO_D(GEN6_RC_CONTROL);560 MMIO_D(GEN6_RC_STATE);561 MMIO_D(GEN6_RPNSWREQ);562 MMIO_D(GEN6_RC_VIDEO_FREQ);563 MMIO_D(GEN6_RP_DOWN_TIMEOUT);564 MMIO_D(GEN6_RP_INTERRUPT_LIMITS);565 MMIO_D(GEN6_RPSTAT1);566 MMIO_D(GEN6_RP_CONTROL);567 MMIO_D(GEN6_RP_UP_THRESHOLD);568 MMIO_D(GEN6_RP_DOWN_THRESHOLD);569 MMIO_D(GEN6_RP_CUR_UP_EI);570 MMIO_D(GEN6_RP_CUR_UP);571 MMIO_D(GEN6_RP_PREV_UP);572 MMIO_D(GEN6_RP_CUR_DOWN_EI);573 MMIO_D(GEN6_RP_CUR_DOWN);574 MMIO_D(GEN6_RP_PREV_DOWN);575 MMIO_D(GEN6_RP_UP_EI);576 MMIO_D(GEN6_RP_DOWN_EI);577 MMIO_D(GEN6_RP_IDLE_HYSTERSIS);578 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT);579 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT);580 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT);581 MMIO_D(GEN6_RC_EVALUATION_INTERVAL);582 MMIO_D(GEN6_RC_IDLE_HYSTERSIS);583 MMIO_D(GEN6_RC_SLEEP);584 MMIO_D(GEN6_RC1e_THRESHOLD);585 MMIO_D(GEN6_RC6_THRESHOLD);586 MMIO_D(GEN6_RC6p_THRESHOLD);587 MMIO_D(GEN6_RC6pp_THRESHOLD);588 MMIO_D(GEN6_PMINTRMSK);589 590 MMIO_D(RSTDBYCTL);591 MMIO_D(GEN6_GDRST);592 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80);593 MMIO_D(CPU_VGACNTRL);594 MMIO_D(TILECTL);595 MMIO_D(GEN6_UCGCTL1);596 MMIO_D(GEN6_UCGCTL2);597 MMIO_F(_MMIO(0x4f000), 0x90);598 MMIO_D(GEN6_PCODE_DATA);599 MMIO_D(_MMIO(0x13812c));600 MMIO_D(GEN7_ERR_INT);601 MMIO_D(HSW_EDRAM_CAP);602 MMIO_D(HSW_IDICR);603 MMIO_D(GFX_FLSH_CNTL_GEN6);604 MMIO_D(_MMIO(0x3c));605 MMIO_D(_MMIO(0x860));606 MMIO_D(ECOSKPD(RENDER_RING_BASE));607 MMIO_D(_MMIO(0x121d0));608 MMIO_D(ECOSKPD(BLT_RING_BASE));609 MMIO_D(_MMIO(0x41d0));610 MMIO_D(GAC_ECO_BITS);611 MMIO_D(_MMIO(0x6200));612 MMIO_D(_MMIO(0x6204));613 MMIO_D(_MMIO(0x6208));614 MMIO_D(_MMIO(0x7118));615 MMIO_D(_MMIO(0x7180));616 MMIO_D(_MMIO(0x7408));617 MMIO_D(_MMIO(0x7c00));618 MMIO_D(GEN6_MBCTL);619 MMIO_D(_MMIO(0x911c));620 MMIO_D(_MMIO(0x9120));621 MMIO_D(GEN7_UCGCTL4);622 MMIO_D(GAB_CTL);623 MMIO_D(_MMIO(0x48800));624 MMIO_D(_MMIO(0xce044));625 MMIO_D(_MMIO(0xe6500));626 MMIO_D(_MMIO(0xe6504));627 MMIO_D(_MMIO(0xe6600));628 MMIO_D(_MMIO(0xe6604));629 MMIO_D(_MMIO(0xe6700));630 MMIO_D(_MMIO(0xe6704));631 MMIO_D(_MMIO(0xe6800));632 MMIO_D(_MMIO(0xe6804));633 MMIO_D(PCH_GMBUS4);634 MMIO_D(PCH_GMBUS5);635 MMIO_D(_MMIO(0x902c));636 MMIO_D(_MMIO(0xec008));637 MMIO_D(_MMIO(0xec00c));638 MMIO_D(_MMIO(0xec008 + 0x18));639 MMIO_D(_MMIO(0xec00c + 0x18));640 MMIO_D(_MMIO(0xec008 + 0x18 * 2));641 MMIO_D(_MMIO(0xec00c + 0x18 * 2));642 MMIO_D(_MMIO(0xec008 + 0x18 * 3));643 MMIO_D(_MMIO(0xec00c + 0x18 * 3));644 MMIO_D(_MMIO(0xec408));645 MMIO_D(_MMIO(0xec40c));646 MMIO_D(_MMIO(0xec408 + 0x18));647 MMIO_D(_MMIO(0xec40c + 0x18));648 MMIO_D(_MMIO(0xec408 + 0x18 * 2));649 MMIO_D(_MMIO(0xec40c + 0x18 * 2));650 MMIO_D(_MMIO(0xec408 + 0x18 * 3));651 MMIO_D(_MMIO(0xec40c + 0x18 * 3));652 MMIO_D(_MMIO(0xfc810));653 MMIO_D(_MMIO(0xfc81c));654 MMIO_D(_MMIO(0xfc828));655 MMIO_D(_MMIO(0xfc834));656 MMIO_D(_MMIO(0xfcc00));657 MMIO_D(_MMIO(0xfcc0c));658 MMIO_D(_MMIO(0xfcc18));659 MMIO_D(_MMIO(0xfcc24));660 MMIO_D(_MMIO(0xfd000));661 MMIO_D(_MMIO(0xfd00c));662 MMIO_D(_MMIO(0xfd018));663 MMIO_D(_MMIO(0xfd024));664 MMIO_D(_MMIO(0xfd034));665 MMIO_D(FPGA_DBG);666 MMIO_D(_MMIO(0x2054));667 MMIO_D(_MMIO(0x12054));668 MMIO_D(_MMIO(0x22054));669 MMIO_D(_MMIO(0x1a054));670 MMIO_D(_MMIO(0x44070));671 MMIO_D(_MMIO(0x2178));672 MMIO_D(_MMIO(0x217c));673 MMIO_D(_MMIO(0x12178));674 MMIO_D(_MMIO(0x1217c));675 MMIO_F(_MMIO(0x5200), 32);676 MMIO_F(_MMIO(0x5240), 32);677 MMIO_F(_MMIO(0x5280), 16);678 MMIO_D(BCS_SWCTRL);679 MMIO_F(HS_INVOCATION_COUNT, 8);680 MMIO_F(DS_INVOCATION_COUNT, 8);681 MMIO_F(IA_VERTICES_COUNT, 8);682 MMIO_F(IA_PRIMITIVES_COUNT, 8);683 MMIO_F(VS_INVOCATION_COUNT, 8);684 MMIO_F(GS_INVOCATION_COUNT, 8);685 MMIO_F(GS_PRIMITIVES_COUNT, 8);686 MMIO_F(CL_INVOCATION_COUNT, 8);687 MMIO_F(CL_PRIMITIVES_COUNT, 8);688 MMIO_F(PS_INVOCATION_COUNT, 8);689 MMIO_F(PS_DEPTH_COUNT, 8);690 MMIO_D(ARB_MODE);691 MMIO_RING_D(RING_BBADDR);692 MMIO_D(_MMIO(0x2220));693 MMIO_D(_MMIO(0x12220));694 MMIO_D(_MMIO(0x22220));695 MMIO_RING_D(RING_SYNC_1);696 MMIO_RING_D(RING_SYNC_0);697 MMIO_D(GUC_STATUS);698 699 MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000);700 MMIO_F(_MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE);701 MMIO_F(LGC_PALETTE(PIPE_A, 0), 1024);702 MMIO_F(LGC_PALETTE(PIPE_B, 0), 1024);703 MMIO_F(LGC_PALETTE(PIPE_C, 0), 1024);704 705 return 0;706}707 708static int iterate_bdw_only_mmio(struct intel_gvt_mmio_table_iter *iter)709{710 MMIO_D(HSW_PWR_WELL_CTL1);711 MMIO_D(HSW_PWR_WELL_CTL2);712 MMIO_D(HSW_PWR_WELL_CTL3);713 MMIO_D(HSW_PWR_WELL_CTL4);714 MMIO_D(HSW_PWR_WELL_CTL5);715 MMIO_D(HSW_PWR_WELL_CTL6);716 717 MMIO_D(WM_MISC);718 MMIO_D(_MMIO(_SRD_CTL_EDP));719 720 MMIO_D(_MMIO(0xb1f0));721 MMIO_D(_MMIO(0xb1c0));722 MMIO_D(_MMIO(0xb100));723 MMIO_D(_MMIO(0xb10c));724 MMIO_D(_MMIO(0xb110));725 MMIO_D(_MMIO(0x83a4));726 MMIO_D(_MMIO(0x8430));727 MMIO_D(_MMIO(0x2248));728 MMIO_D(FORCEWAKE_ACK_HSW);729 730 return 0;731}732 733static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)734{735 struct drm_i915_private *dev_priv = iter->i915;736 737 MMIO_D(GEN8_GT_IMR(0));738 MMIO_D(GEN8_GT_IER(0));739 MMIO_D(GEN8_GT_IIR(0));740 MMIO_D(GEN8_GT_ISR(0));741 MMIO_D(GEN8_GT_IMR(1));742 MMIO_D(GEN8_GT_IER(1));743 MMIO_D(GEN8_GT_IIR(1));744 MMIO_D(GEN8_GT_ISR(1));745 MMIO_D(GEN8_GT_IMR(2));746 MMIO_D(GEN8_GT_IER(2));747 MMIO_D(GEN8_GT_IIR(2));748 MMIO_D(GEN8_GT_ISR(2));749 MMIO_D(GEN8_GT_IMR(3));750 MMIO_D(GEN8_GT_IER(3));751 MMIO_D(GEN8_GT_IIR(3));752 MMIO_D(GEN8_GT_ISR(3));753 MMIO_D(GEN8_DE_PIPE_IMR(PIPE_A));754 MMIO_D(GEN8_DE_PIPE_IER(PIPE_A));755 MMIO_D(GEN8_DE_PIPE_IIR(PIPE_A));756 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A));757 MMIO_D(GEN8_DE_PIPE_IMR(PIPE_B));758 MMIO_D(GEN8_DE_PIPE_IER(PIPE_B));759 MMIO_D(GEN8_DE_PIPE_IIR(PIPE_B));760 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B));761 MMIO_D(GEN8_DE_PIPE_IMR(PIPE_C));762 MMIO_D(GEN8_DE_PIPE_IER(PIPE_C));763 MMIO_D(GEN8_DE_PIPE_IIR(PIPE_C));764 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C));765 MMIO_D(GEN8_DE_PORT_IMR);766 MMIO_D(GEN8_DE_PORT_IER);767 MMIO_D(GEN8_DE_PORT_IIR);768 MMIO_D(GEN8_DE_PORT_ISR);769 MMIO_D(GEN8_DE_MISC_IMR);770 MMIO_D(GEN8_DE_MISC_IER);771 MMIO_D(GEN8_DE_MISC_IIR);772 MMIO_D(GEN8_DE_MISC_ISR);773 MMIO_D(GEN8_PCU_IMR);774 MMIO_D(GEN8_PCU_IER);775 MMIO_D(GEN8_PCU_IIR);776 MMIO_D(GEN8_PCU_ISR);777 MMIO_D(GEN8_MASTER_IRQ);778 MMIO_RING_D(RING_ACTHD_UDW);779 780#define RING_REG(base) _MMIO((base) + 0xd0)781 MMIO_RING_D(RING_REG);782#undef RING_REG783 784#define RING_REG(base) _MMIO((base) + 0x230)785 MMIO_RING_D(RING_REG);786#undef RING_REG787 788#define RING_REG(base) _MMIO((base) + 0x234)789 MMIO_RING_F(RING_REG, 8);790#undef RING_REG791 792#define RING_REG(base) _MMIO((base) + 0x244)793 MMIO_RING_D(RING_REG);794#undef RING_REG795 796#define RING_REG(base) _MMIO((base) + 0x370)797 MMIO_RING_F(RING_REG, 48);798#undef RING_REG799 800#define RING_REG(base) _MMIO((base) + 0x3a0)801 MMIO_RING_D(RING_REG);802#undef RING_REG803 804 MMIO_D(PIPE_MISC(PIPE_A));805 MMIO_D(PIPE_MISC(PIPE_B));806 MMIO_D(PIPE_MISC(PIPE_C));807 MMIO_D(_MMIO(0x1c1d0));808 MMIO_D(GEN6_MBCUNIT_SNPCR);809 MMIO_D(GEN7_MISCCPCTL);810 MMIO_D(_MMIO(0x1c054));811 MMIO_D(GEN6_PCODE_MAILBOX);812 if (!IS_BROXTON(dev_priv))813 MMIO_D(GEN8_PRIVATE_PAT_LO);814 MMIO_D(GEN8_PRIVATE_PAT_HI);815 MMIO_D(GAMTARBMODE);816 817#define RING_REG(base) _MMIO((base) + 0x270)818 MMIO_RING_F(RING_REG, 32);819#undef RING_REG820 821 MMIO_RING_D(RING_HWS_PGA);822 MMIO_D(HDC_CHICKEN0);823 MMIO_D(CHICKEN_PIPESL_1(PIPE_A));824 MMIO_D(CHICKEN_PIPESL_1(PIPE_B));825 MMIO_D(CHICKEN_PIPESL_1(PIPE_C));826 MMIO_D(_MMIO(0x6671c));827 MMIO_D(_MMIO(0x66c00));828 MMIO_D(_MMIO(0x66c04));829 MMIO_D(HSW_GTT_CACHE_EN);830 MMIO_D(GEN8_EU_DISABLE0);831 MMIO_D(GEN8_EU_DISABLE1);832 MMIO_D(GEN8_EU_DISABLE2);833 MMIO_D(_MMIO(0xfdc));834 MMIO_D(GEN8_ROW_CHICKEN);835 MMIO_D(GEN7_ROW_CHICKEN2);836 MMIO_D(GEN8_UCGCTL6);837 MMIO_D(GEN8_L3SQCREG4);838 MMIO_D(GEN9_SCRATCH_LNCF1);839 MMIO_F(_MMIO(0x24d0), 48);840 MMIO_D(_MMIO(0x44484));841 MMIO_D(_MMIO(0x4448c));842 MMIO_D(GEN8_L3_LRA_1_GPGPU);843 MMIO_D(_MMIO(0x110000));844 MMIO_D(_MMIO(0x48400));845 MMIO_D(_MMIO(0x6e570));846 MMIO_D(_MMIO(0x65f10));847 MMIO_D(_MMIO(0xe194));848 MMIO_D(_MMIO(0xe188));849 MMIO_D(HALF_SLICE_CHICKEN2);850 MMIO_D(_MMIO(0x2580));851 MMIO_D(_MMIO(0xe220));852 MMIO_D(_MMIO(0xe230));853 MMIO_D(_MMIO(0xe240));854 MMIO_D(_MMIO(0xe260));855 MMIO_D(_MMIO(0xe270));856 MMIO_D(_MMIO(0xe280));857 MMIO_D(_MMIO(0xe2a0));858 MMIO_D(_MMIO(0xe2b0));859 MMIO_D(_MMIO(0xe2c0));860 MMIO_D(_MMIO(0x21f0));861 MMIO_D(GEN8_GAMW_ECO_DEV_RW_IA);862 MMIO_D(_MMIO(0x215c));863 MMIO_F(_MMIO(0x2290), 8);864 MMIO_D(_MMIO(0x2b00));865 MMIO_D(_MMIO(0x2360));866 MMIO_D(_MMIO(0x1c17c));867 MMIO_D(_MMIO(0x1c178));868 MMIO_D(_MMIO(0x4260));869 MMIO_D(_MMIO(0x4264));870 MMIO_D(_MMIO(0x4268));871 MMIO_D(_MMIO(0x426c));872 MMIO_D(_MMIO(0x4270));873 MMIO_D(_MMIO(0x4094));874 MMIO_D(_MMIO(0x22178));875 MMIO_D(_MMIO(0x1a178));876 MMIO_D(_MMIO(0x1a17c));877 MMIO_D(_MMIO(0x2217c));878 MMIO_D(EDP_PSR_IMR);879 MMIO_D(EDP_PSR_IIR);880 MMIO_D(_MMIO(0xe4cc));881 MMIO_D(GEN7_SC_INSTDONE);882 883 return 0;884}885 886static int iterate_pre_skl_mmio(struct intel_gvt_mmio_table_iter *iter)887{888 MMIO_D(FORCEWAKE_MT);889 890 MMIO_D(PCH_ADPA);891 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);892 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);893 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);894 895 MMIO_F(_MMIO(0x70440), 0xc);896 MMIO_F(_MMIO(0x71440), 0xc);897 MMIO_F(_MMIO(0x72440), 0xc);898 MMIO_F(_MMIO(0x7044c), 0xc);899 MMIO_F(_MMIO(0x7144c), 0xc);900 MMIO_F(_MMIO(0x7244c), 0xc);901 902 return 0;903}904 905static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)906{907 struct drm_i915_private *dev_priv = iter->i915;908 909 MMIO_D(FORCEWAKE_RENDER_GEN9);910 MMIO_D(FORCEWAKE_ACK_RENDER_GEN9);911 MMIO_D(FORCEWAKE_GT_GEN9);912 MMIO_D(FORCEWAKE_ACK_GT_GEN9);913 MMIO_D(FORCEWAKE_MEDIA_GEN9);914 MMIO_D(FORCEWAKE_ACK_MEDIA_GEN9);915 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);916 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);917 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);918 MMIO_D(HSW_PWR_WELL_CTL1);919 MMIO_D(HSW_PWR_WELL_CTL2);920 MMIO_D(DBUF_CTL_S(0));921 MMIO_D(GEN9_PG_ENABLE);922 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS);923 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS);924 MMIO_D(GEN9_GAMT_ECO_REG_RW_IA);925 MMIO_D(MMCD_MISC_CTRL);926 MMIO_D(CHICKEN_PAR1_1);927 MMIO_D(DC_STATE_EN);928 MMIO_D(DC_STATE_DEBUG);929 MMIO_D(CDCLK_CTL);930 MMIO_D(LCPLL1_CTL);931 MMIO_D(LCPLL2_CTL);932 MMIO_D(_MMIO(_DPLL1_CFGCR1));933 MMIO_D(_MMIO(_DPLL2_CFGCR1));934 MMIO_D(_MMIO(_DPLL3_CFGCR1));935 MMIO_D(_MMIO(_DPLL1_CFGCR2));936 MMIO_D(_MMIO(_DPLL2_CFGCR2));937 MMIO_D(_MMIO(_DPLL3_CFGCR2));938 MMIO_D(DPLL_CTRL1);939 MMIO_D(DPLL_CTRL2);940 MMIO_D(DPLL_STATUS);941 MMIO_D(SKL_PS_WIN_POS(PIPE_A, 0));942 MMIO_D(SKL_PS_WIN_POS(PIPE_A, 1));943 MMIO_D(SKL_PS_WIN_POS(PIPE_B, 0));944 MMIO_D(SKL_PS_WIN_POS(PIPE_B, 1));945 MMIO_D(SKL_PS_WIN_POS(PIPE_C, 0));946 MMIO_D(SKL_PS_WIN_POS(PIPE_C, 1));947 MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 0));948 MMIO_D(SKL_PS_WIN_SZ(PIPE_A, 1));949 MMIO_D(SKL_PS_WIN_SZ(PIPE_B, 0));950 MMIO_D(SKL_PS_WIN_SZ(PIPE_B, 1));951 MMIO_D(SKL_PS_WIN_SZ(PIPE_C, 0));952 MMIO_D(SKL_PS_WIN_SZ(PIPE_C, 1));953 MMIO_D(SKL_PS_CTRL(PIPE_A, 0));954 MMIO_D(SKL_PS_CTRL(PIPE_A, 1));955 MMIO_D(SKL_PS_CTRL(PIPE_B, 0));956 MMIO_D(SKL_PS_CTRL(PIPE_B, 1));957 MMIO_D(SKL_PS_CTRL(PIPE_C, 0));958 MMIO_D(SKL_PS_CTRL(PIPE_C, 1));959 MMIO_D(PLANE_BUF_CFG(PIPE_A, 0));960 MMIO_D(PLANE_BUF_CFG(PIPE_A, 1));961 MMIO_D(PLANE_BUF_CFG(PIPE_A, 2));962 MMIO_D(PLANE_BUF_CFG(PIPE_A, 3));963 MMIO_D(PLANE_BUF_CFG(PIPE_B, 0));964 MMIO_D(PLANE_BUF_CFG(PIPE_B, 1));965 MMIO_D(PLANE_BUF_CFG(PIPE_B, 2));966 MMIO_D(PLANE_BUF_CFG(PIPE_B, 3));967 MMIO_D(PLANE_BUF_CFG(PIPE_C, 0));968 MMIO_D(PLANE_BUF_CFG(PIPE_C, 1));969 MMIO_D(PLANE_BUF_CFG(PIPE_C, 2));970 MMIO_D(PLANE_BUF_CFG(PIPE_C, 3));971 MMIO_D(CUR_BUF_CFG(PIPE_A));972 MMIO_D(CUR_BUF_CFG(PIPE_B));973 MMIO_D(CUR_BUF_CFG(PIPE_C));974 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8);975 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8);976 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8);977 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8);978 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8);979 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8);980 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8);981 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8);982 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8);983 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8);984 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8);985 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8);986 MMIO_D(PLANE_WM_TRANS(PIPE_A, 0));987 MMIO_D(PLANE_WM_TRANS(PIPE_A, 1));988 MMIO_D(PLANE_WM_TRANS(PIPE_A, 2));989 MMIO_D(PLANE_WM_TRANS(PIPE_B, 0));990 MMIO_D(PLANE_WM_TRANS(PIPE_B, 1));991 MMIO_D(PLANE_WM_TRANS(PIPE_B, 2));992 MMIO_D(PLANE_WM_TRANS(PIPE_C, 0));993 MMIO_D(PLANE_WM_TRANS(PIPE_C, 1));994 MMIO_D(PLANE_WM_TRANS(PIPE_C, 2));995 MMIO_D(CUR_WM_TRANS(PIPE_A));996 MMIO_D(CUR_WM_TRANS(PIPE_B));997 MMIO_D(CUR_WM_TRANS(PIPE_C));998 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 0));999 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 1));1000 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 2));1001 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_A, 3));1002 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 0));1003 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 1));1004 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 2));1005 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 3));1006 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 0));1007 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1));1008 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2));1009 MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3));1010 MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));1011 MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));1012 MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));1013 MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));1014 MMIO_D(PLANE_AUX_DIST(PIPE_B, 0));1015 MMIO_D(PLANE_AUX_DIST(PIPE_B, 1));1016 MMIO_D(PLANE_AUX_DIST(PIPE_B, 2));1017 MMIO_D(PLANE_AUX_DIST(PIPE_B, 3));1018 MMIO_D(PLANE_AUX_DIST(PIPE_C, 0));1019 MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));1020 MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));1021 MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));1022 MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));1023 MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));1024 MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));1025 MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));1026 MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));1027 MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));1028 MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));1029 MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));1030 MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));1031 MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));1032 MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));1033 MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));1034 MMIO_D(PLANE_CTL(PIPE_A, 2));1035 MMIO_D(PLANE_CTL(PIPE_B, 2));1036 MMIO_D(PLANE_CTL(PIPE_C, 2));1037 MMIO_D(PLANE_SURF(PIPE_A, 2));1038 MMIO_D(PLANE_SURF(PIPE_B, 2));1039 MMIO_D(PLANE_SURF(PIPE_C, 2));1040 MMIO_D(DMC_SSP_BASE);1041 MMIO_D(DMC_HTP_SKL);1042 MMIO_D(DMC_LAST_WRITE);1043 MMIO_D(BDW_SCRATCH1);1044 MMIO_D(SKL_DFSM);1045 MMIO_D(DISPIO_CR_TX_BMU_CR0);1046 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8);1047 MMIO_F(GEN7_L3CNTLREG2, 0x80);1048 MMIO_D(RPM_CONFIG0);1049 MMIO_D(_MMIO(0xd08));1050 MMIO_D(RC6_LOCATION);1051 MMIO_D(GEN7_FF_SLICE_CS_CHICKEN1);1052 MMIO_D(GEN9_CS_DEBUG_MODE1);1053 /* TRTT */1054 MMIO_D(TRVATTL3PTRDW(0));1055 MMIO_D(TRVATTL3PTRDW(1));1056 MMIO_D(TRVATTL3PTRDW(2));1057 MMIO_D(TRVATTL3PTRDW(3));1058 MMIO_D(TRVADR);1059 MMIO_D(TRTTE);1060 MMIO_D(_MMIO(0x4dfc));1061 MMIO_D(_MMIO(0x46430));1062 MMIO_D(_MMIO(0x46520));1063 MMIO_D(_MMIO(0xc403c));1064 MMIO_D(GEN8_GARBCNTL);1065 MMIO_D(DMA_CTRL);1066 MMIO_D(_MMIO(0x65900));1067 MMIO_D(GEN6_STOLEN_RESERVED);1068 MMIO_D(_MMIO(0x4068));1069 MMIO_D(_MMIO(0x67054));1070 MMIO_D(_MMIO(0x6e560));1071 MMIO_D(_MMIO(0x6e554));1072 MMIO_D(_MMIO(0x2b20));1073 MMIO_D(_MMIO(0x65f00));1074 MMIO_D(_MMIO(0x65f08));1075 MMIO_D(_MMIO(0x320f0));1076 MMIO_D(_MMIO(0x70034));1077 MMIO_D(_MMIO(0x71034));1078 MMIO_D(_MMIO(0x72034));1079 MMIO_D(PLANE_KEYVAL(PIPE_A, 0));1080 MMIO_D(PLANE_KEYVAL(PIPE_B, 0));1081 MMIO_D(PLANE_KEYVAL(PIPE_C, 0));1082 MMIO_D(PLANE_KEYMAX(PIPE_A, 0));1083 MMIO_D(PLANE_KEYMAX(PIPE_B, 0));1084 MMIO_D(PLANE_KEYMAX(PIPE_C, 0));1085 MMIO_D(PLANE_KEYMSK(PIPE_A, 0));1086 MMIO_D(PLANE_KEYMSK(PIPE_B, 0));1087 MMIO_D(PLANE_KEYMSK(PIPE_C, 0));1088 MMIO_D(_MMIO(0x44500));1089#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)1090 MMIO_RING_D(CSFE_CHICKEN1_REG);1091#undef CSFE_CHICKEN1_REG1092 MMIO_D(GEN8_HDC_CHICKEN1);1093 MMIO_D(GEN9_WM_CHICKEN3);1094 1095 if (IS_KABYLAKE(dev_priv) ||1096 IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))1097 MMIO_D(GAMT_CHKN_BIT_REG);1098 if (!IS_BROXTON(dev_priv))1099 MMIO_D(GEN9_CTX_PREEMPT_REG);1100 MMIO_F(_MMIO(DMC_MMIO_START_RANGE), 0x3000);1101 return 0;1102}1103 1104static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)1105{1106 struct drm_i915_private *dev_priv = iter->i915;1107 1108 MMIO_F(_MMIO(0x80000), 0x3000);1109 MMIO_D(GEN7_SAMPLER_INSTDONE);1110 MMIO_D(GEN7_ROW_INSTDONE);1111 MMIO_D(GEN8_FAULT_TLB_DATA0);1112 MMIO_D(GEN8_FAULT_TLB_DATA1);1113 MMIO_D(ERROR_GEN6);1114 MMIO_D(DONE_REG);1115 MMIO_D(EIR);1116 MMIO_D(PGTBL_ER);1117 MMIO_D(_MMIO(0x4194));1118 MMIO_D(_MMIO(0x4294));1119 MMIO_D(_MMIO(0x4494));1120 MMIO_RING_D(RING_PSMI_CTL);1121 MMIO_RING_D(RING_DMA_FADD);1122 MMIO_RING_D(RING_DMA_FADD_UDW);1123 MMIO_RING_D(RING_IPEHR);1124 MMIO_RING_D(RING_INSTPS);1125 MMIO_RING_D(RING_BBADDR_UDW);1126 MMIO_RING_D(RING_BBSTATE);1127 MMIO_RING_D(RING_IPEIR);1128 MMIO_F(SOFT_SCRATCH(0), 16 * 4);1129 MMIO_D(BXT_P_CR_GT_DISP_PWRON);1130 MMIO_D(BXT_RP_STATE_CAP);1131 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY0));1132 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY1));1133 MMIO_D(BXT_PHY_CTL(PORT_A));1134 MMIO_D(BXT_PHY_CTL(PORT_B));1135 MMIO_D(BXT_PHY_CTL(PORT_C));1136 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A));1137 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B));1138 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_C));1139 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0));1140 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0));1141 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0));1142 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0));1143 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0));1144 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0));1145 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0));1146 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0));1147 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0));1148 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1));1149 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1));1150 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1));1151 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1));1152 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1));1153 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1));1154 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1));1155 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1));1156 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1));1157 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0));1158 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0));1159 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0));1160 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0));1161 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0));1162 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0));1163 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0));1164 MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH0, 0));1165 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0));1166 MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0));1167 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0));1168 MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH0, 0));1169 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0));1170 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0));1171 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1));1172 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2));1173 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3));1174 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0));1175 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1));1176 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2));1177 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3));1178 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6));1179 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8));1180 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9));1181 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10));1182 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1));1183 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1));1184 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1));1185 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1));1186 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1));1187 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1));1188 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1));1189 MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH1, 0));1190 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1));1191 MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0));1192 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1));1193 MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH1, 0));1194 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1));1195 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0));1196 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1));1197 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2));1198 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3));1199 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0));1200 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1));1201 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2));1202 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3));1203 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6));1204 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8));1205 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9));1206 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10));1207 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0));1208 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0));1209 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0));1210 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0));1211 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0));1212 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0));1213 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0));1214 MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY1, DPIO_CH0, 0));1215 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0));1216 MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0));1217 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0));1218 MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY1, DPIO_CH0, 0));1219 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0));1220 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0));1221 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1));1222 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2));1223 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3));1224 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0));1225 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1));1226 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2));1227 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3));1228 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6));1229 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8));1230 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9));1231 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10));1232 MMIO_D(BXT_DE_PLL_CTL);1233 MMIO_D(BXT_DE_PLL_ENABLE);1234 MMIO_D(BXT_DSI_PLL_CTL);1235 MMIO_D(BXT_DSI_PLL_ENABLE);1236 MMIO_D(GEN9_CLKGATE_DIS_0);1237 MMIO_D(GEN9_CLKGATE_DIS_4);1238 MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A));1239 MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B));1240 MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C));1241 MMIO_D(RC6_CTX_BASE);1242 MMIO_D(GEN8_PUSHBUS_CONTROL);1243 MMIO_D(GEN8_PUSHBUS_ENABLE);1244 MMIO_D(GEN8_PUSHBUS_SHIFT);1245 MMIO_D(GEN6_GFXPAUSE);1246 MMIO_D(GEN8_L3SQCREG1);1247 MMIO_D(GEN8_L3CNTLREG);1248 MMIO_D(_MMIO(0x20D8));1249 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);1250 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);1251 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);1252 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);1253 MMIO_D(GEN9_CTX_PREEMPT_REG);1254 MMIO_D(GEN8_PRIVATE_PAT_LO);1255 1256 return 0;1257}1258 1259/**1260 * intel_gvt_iterate_mmio_table - Iterate the GVT MMIO table1261 * @iter: the interator1262 *1263 * This function is called for iterating the GVT MMIO table when i915 is1264 * taking the snapshot of the HW and GVT is building MMIO tracking table.1265 */1266int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter)1267{1268 struct drm_i915_private *i915 = iter->i915;1269 int ret;1270 1271 ret = iterate_generic_mmio(iter);1272 if (ret)1273 goto err;1274 1275 if (IS_BROADWELL(i915)) {1276 ret = iterate_bdw_only_mmio(iter);1277 if (ret)1278 goto err;1279 ret = iterate_bdw_plus_mmio(iter);1280 if (ret)1281 goto err;1282 ret = iterate_pre_skl_mmio(iter);1283 if (ret)1284 goto err;1285 } else if (IS_SKYLAKE(i915) ||1286 IS_KABYLAKE(i915) ||1287 IS_COFFEELAKE(i915) ||1288 IS_COMETLAKE(i915)) {1289 ret = iterate_bdw_plus_mmio(iter);1290 if (ret)1291 goto err;1292 ret = iterate_skl_plus_mmio(iter);1293 if (ret)1294 goto err;1295 } else if (IS_BROXTON(i915)) {1296 ret = iterate_bdw_plus_mmio(iter);1297 if (ret)1298 goto err;1299 ret = iterate_skl_plus_mmio(iter);1300 if (ret)1301 goto err;1302 ret = iterate_bxt_mmio(iter);1303 if (ret)1304 goto err;1305 }1306 1307 return 0;1308err:1309 return ret;1310}1311EXPORT_SYMBOL_NS_GPL(intel_gvt_iterate_mmio_table, I915_GVT);1312