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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2019 Intel Corporation.4 */5 6#ifndef __INTEL_PCH__7#define __INTEL_PCH__8 9struct drm_i915_private;10 11/*12 * Sorted by south display engine compatibility.13 * If the new PCH comes with a south display engine that is not14 * inherited from the latest item, please do not add it to the15 * end. Instead, add it right after its "parent" PCH.16 */17enum intel_pch {18 PCH_NOP = -1, /* PCH without south display */19 PCH_NONE = 0, /* No PCH present */20 PCH_IBX, /* Ibexpeak PCH */21 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */22 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */23 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */24 PCH_CNP, /* Cannon/Comet Lake PCH */25 PCH_ICP, /* Ice Lake/Jasper Lake PCH */26 PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */27 PCH_ADP, /* Alder Lake PCH */28 29 /* Fake PCHs, functionality handled on the same PCI dev */30 PCH_DG1 = 1024,31 PCH_DG2,32 PCH_MTL,33 PCH_LNL,34};35 36#define INTEL_PCH_DEVICE_ID_MASK 0xff8037#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b0038#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c0039#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e0040#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c0041#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c0042#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c8043#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c8044#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA10045#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D0046#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA28047#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA30048#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D8049#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x028050#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x068051#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA38052#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x348053#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x388054#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B0055#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA08056#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x438057#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D8058#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A8059#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x518060#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A0061#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x548062#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x710063#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x700064#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */65 66#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)67#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)68#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)69#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)70#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)71#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)72#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)73#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)74#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)75#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)76#define HAS_PCH_LPT_LP(dev_priv) \77 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \78 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)79#define HAS_PCH_LPT_H(dev_priv) \80 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \81 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)82#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)83#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)84#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)85#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)86 87void intel_detect_pch(struct drm_i915_private *dev_priv);88 89#endif /* __INTEL_PCH__ */90