187 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */2/* Copyright (c) 2023 Imagination Technologies Ltd. */3 4#ifndef PVR_DEVICE_INFO_H5#define PVR_DEVICE_INFO_H6 7#include <linux/types.h>8 9struct pvr_device;10 11/*12 * struct pvr_device_features - Hardware feature information13 */14struct pvr_device_features {15 bool has_axi_acelite;16 bool has_cdm_control_stream_format;17 bool has_cluster_grouping;18 bool has_common_store_size_in_dwords;19 bool has_compute;20 bool has_compute_morton_capable;21 bool has_compute_overlap;22 bool has_coreid_per_os;23 bool has_dynamic_dust_power;24 bool has_ecc_rams;25 bool has_fb_cdc_v4;26 bool has_fbc_max_default_descriptors;27 bool has_fbc_max_large_descriptors;28 bool has_fbcdc;29 bool has_fbcdc_algorithm;30 bool has_fbcdc_architecture;31 bool has_gpu_multicore_support;32 bool has_gpu_virtualisation;33 bool has_gs_rta_support;34 bool has_irq_per_os;35 bool has_isp_max_tiles_in_flight;36 bool has_isp_samples_per_pixel;37 bool has_isp_zls_d24_s8_packing_ogl_mode;38 bool has_layout_mars;39 bool has_max_partitions;40 bool has_meta;41 bool has_meta_coremem_size;42 bool has_mips;43 bool has_num_clusters;44 bool has_num_isp_ipp_pipes;45 bool has_num_osids;46 bool has_num_raster_pipes;47 bool has_pbe2_in_xe;48 bool has_pbvnc_coreid_reg;49 bool has_perfbus;50 bool has_perf_counter_batch;51 bool has_phys_bus_width;52 bool has_riscv_fw_processor;53 bool has_roguexe;54 bool has_s7_top_infrastructure;55 bool has_simple_internal_parameter_format;56 bool has_simple_internal_parameter_format_v2;57 bool has_simple_parameter_format_version;58 bool has_slc_banks;59 bool has_slc_cache_line_size_bits;60 bool has_slc_size_configurable;61 bool has_slc_size_in_kilobytes;62 bool has_soc_timer;63 bool has_sys_bus_secure_reset;64 bool has_tessellation;65 bool has_tile_region_protection;66 bool has_tile_size_x;67 bool has_tile_size_y;68 bool has_tla;69 bool has_tpu_cem_datamaster_global_registers;70 bool has_tpu_dm_global_registers;71 bool has_tpu_filtering_mode_control;72 bool has_usc_min_output_registers_per_pix;73 bool has_vdm_drawindirect;74 bool has_vdm_object_level_lls;75 bool has_virtual_address_space_bits;76 bool has_watchdog_timer;77 bool has_workgroup_protection;78 bool has_xe_architecture;79 bool has_xe_memory_hierarchy;80 bool has_xe_tpu2;81 bool has_xpu_max_regbanks_addr_width;82 bool has_xpu_max_slaves;83 bool has_xpu_register_broadcast;84 bool has_xt_top_infrastructure;85 bool has_zls_subtile;86 87 u64 cdm_control_stream_format;88 u64 common_store_size_in_dwords;89 u64 ecc_rams;90 u64 fbc_max_default_descriptors;91 u64 fbc_max_large_descriptors;92 u64 fbcdc;93 u64 fbcdc_algorithm;94 u64 fbcdc_architecture;95 u64 isp_max_tiles_in_flight;96 u64 isp_samples_per_pixel;97 u64 layout_mars;98 u64 max_partitions;99 u64 meta;100 u64 meta_coremem_size;101 u64 num_clusters;102 u64 num_isp_ipp_pipes;103 u64 num_osids;104 u64 num_raster_pipes;105 u64 phys_bus_width;106 u64 simple_parameter_format_version;107 u64 slc_banks;108 u64 slc_cache_line_size_bits;109 u64 slc_size_in_kilobytes;110 u64 tile_size_x;111 u64 tile_size_y;112 u64 usc_min_output_registers_per_pix;113 u64 virtual_address_space_bits;114 u64 xe_architecture;115 u64 xpu_max_regbanks_addr_width;116 u64 xpu_max_slaves;117 u64 xpu_register_broadcast;118};119 120/*121 * struct pvr_device_quirks - Hardware quirk information122 */123struct pvr_device_quirks {124 bool has_brn44079;125 bool has_brn47217;126 bool has_brn48492;127 bool has_brn48545;128 bool has_brn49927;129 bool has_brn50767;130 bool has_brn51764;131 bool has_brn62269;132 bool has_brn63142;133 bool has_brn63553;134 bool has_brn66011;135 bool has_brn71242;136};137 138/*139 * struct pvr_device_enhancements - Hardware enhancement information140 */141struct pvr_device_enhancements {142 bool has_ern35421;143 bool has_ern38020;144 bool has_ern38748;145 bool has_ern42064;146 bool has_ern42290;147 bool has_ern42606;148 bool has_ern47025;149 bool has_ern57596;150};151 152void pvr_device_info_set_quirks(struct pvr_device *pvr_dev, const u64 *bitmask,153 u32 bitmask_len);154void pvr_device_info_set_enhancements(struct pvr_device *pvr_dev, const u64 *bitmask,155 u32 bitmask_len);156int pvr_device_info_set_features(struct pvr_device *pvr_dev, const u64 *features, u32 features_size,157 u32 feature_param_size);158 159/*160 * Meta cores161 *162 * These are the values for the 'meta' feature when the feature is present163 * (as per &struct pvr_device_features)/164 */165#define PVR_META_MTP218 (1)166#define PVR_META_MTP219 (2)167#define PVR_META_LTP218 (3)168#define PVR_META_LTP217 (4)169 170enum {171 PVR_FEATURE_CDM_USER_MODE_QUEUE,172 PVR_FEATURE_CLUSTER_GROUPING,173 PVR_FEATURE_COMPUTE_MORTON_CAPABLE,174 PVR_FEATURE_FB_CDC_V4,175 PVR_FEATURE_GPU_MULTICORE_SUPPORT,176 PVR_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE,177 PVR_FEATURE_REQUIRES_FB_CDC_ZLS_SETUP,178 PVR_FEATURE_S7_TOP_INFRASTRUCTURE,179 PVR_FEATURE_TESSELLATION,180 PVR_FEATURE_TPU_DM_GLOBAL_REGISTERS,181 PVR_FEATURE_VDM_DRAWINDIRECT,182 PVR_FEATURE_VDM_OBJECT_LEVEL_LLS,183 PVR_FEATURE_ZLS_SUBTILE,184};185 186#endif /* PVR_DEVICE_INFO_H */187