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1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */2/* Copyright (c) 2023 Imagination Technologies Ltd. */3 4/*  *** Autogenerated C -- do not edit ***  */5 6#ifndef PVR_ROGUE_CR_DEFS_H7#define PVR_ROGUE_CR_DEFS_H8 9/* clang-format off */10 11#define ROGUE_CR_DEFS_REVISION 112 13/* Register ROGUE_CR_RASTERISATION_INDIRECT */14#define ROGUE_CR_RASTERISATION_INDIRECT 0x8238U15#define ROGUE_CR_RASTERISATION_INDIRECT_MASKFULL 0x000000000000000FULL16#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U17#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U18 19/* Register ROGUE_CR_PBE_INDIRECT */20#define ROGUE_CR_PBE_INDIRECT 0x83E0U21#define ROGUE_CR_PBE_INDIRECT_MASKFULL 0x000000000000000FULL22#define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U23#define ROGUE_CR_PBE_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U24 25/* Register ROGUE_CR_PBE_PERF_INDIRECT */26#define ROGUE_CR_PBE_PERF_INDIRECT 0x83D8U27#define ROGUE_CR_PBE_PERF_INDIRECT_MASKFULL 0x000000000000000FULL28#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U29#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U30 31/* Register ROGUE_CR_TPU_PERF_INDIRECT */32#define ROGUE_CR_TPU_PERF_INDIRECT 0x83F0U33#define ROGUE_CR_TPU_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL34#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U35#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U36 37/* Register ROGUE_CR_RASTERISATION_PERF_INDIRECT */38#define ROGUE_CR_RASTERISATION_PERF_INDIRECT 0x8318U39#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_MASKFULL 0x000000000000000FULL40#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U41#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U42 43/* Register ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT */44#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT 0x8028U45#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL46#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U47#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U48 49/* Register ROGUE_CR_USC_PERF_INDIRECT */50#define ROGUE_CR_USC_PERF_INDIRECT 0x8030U51#define ROGUE_CR_USC_PERF_INDIRECT_MASKFULL 0x000000000000000FULL52#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U53#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U54 55/* Register ROGUE_CR_BLACKPEARL_INDIRECT */56#define ROGUE_CR_BLACKPEARL_INDIRECT 0x8388U57#define ROGUE_CR_BLACKPEARL_INDIRECT_MASKFULL 0x0000000000000003ULL58#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U59#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU60 61/* Register ROGUE_CR_BLACKPEARL_PERF_INDIRECT */62#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT 0x83F8U63#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL64#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U65#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU66 67/* Register ROGUE_CR_TEXAS3_PERF_INDIRECT */68#define ROGUE_CR_TEXAS3_PERF_INDIRECT 0x83D0U69#define ROGUE_CR_TEXAS3_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL70#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U71#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U72 73/* Register ROGUE_CR_TEXAS_PERF_INDIRECT */74#define ROGUE_CR_TEXAS_PERF_INDIRECT 0x8288U75#define ROGUE_CR_TEXAS_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL76#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U77#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU78 79/* Register ROGUE_CR_BX_TU_PERF_INDIRECT */80#define ROGUE_CR_BX_TU_PERF_INDIRECT 0xC900U81#define ROGUE_CR_BX_TU_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL82#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U83#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU84 85/* Register ROGUE_CR_CLK_CTRL */86#define ROGUE_CR_CLK_CTRL 0x0000U87#define ROGUE_CR_CLK_CTRL__PBE2_XE__MASKFULL 0xFFFFFF003F3FFFFFULL88#define ROGUE_CR_CLK_CTRL__S7_TOP__MASKFULL 0xCFCF03000F3F3F0FULL89#define ROGUE_CR_CLK_CTRL_MASKFULL 0xFFFFFF003F3FFFFFULL90#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U91#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_CLRMSK 0x3FFFFFFFFFFFFFFFULL92#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_OFF 0x0000000000000000ULL93#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_ON 0x4000000000000000ULL94#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_AUTO 0x8000000000000000ULL95#define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U96#define ROGUE_CR_CLK_CTRL_IPP_CLRMSK 0xCFFFFFFFFFFFFFFFULL97#define ROGUE_CR_CLK_CTRL_IPP_OFF 0x0000000000000000ULL98#define ROGUE_CR_CLK_CTRL_IPP_ON 0x1000000000000000ULL99#define ROGUE_CR_CLK_CTRL_IPP_AUTO 0x2000000000000000ULL100#define ROGUE_CR_CLK_CTRL_FBC_SHIFT 58U101#define ROGUE_CR_CLK_CTRL_FBC_CLRMSK 0xF3FFFFFFFFFFFFFFULL102#define ROGUE_CR_CLK_CTRL_FBC_OFF 0x0000000000000000ULL103#define ROGUE_CR_CLK_CTRL_FBC_ON 0x0400000000000000ULL104#define ROGUE_CR_CLK_CTRL_FBC_AUTO 0x0800000000000000ULL105#define ROGUE_CR_CLK_CTRL_FBDC_SHIFT 56U106#define ROGUE_CR_CLK_CTRL_FBDC_CLRMSK 0xFCFFFFFFFFFFFFFFULL107#define ROGUE_CR_CLK_CTRL_FBDC_OFF 0x0000000000000000ULL108#define ROGUE_CR_CLK_CTRL_FBDC_ON 0x0100000000000000ULL109#define ROGUE_CR_CLK_CTRL_FBDC_AUTO 0x0200000000000000ULL110#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_SHIFT 54U111#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_CLRMSK 0xFF3FFFFFFFFFFFFFULL112#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_OFF 0x0000000000000000ULL113#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_ON 0x0040000000000000ULL114#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_AUTO 0x0080000000000000ULL115#define ROGUE_CR_CLK_CTRL_USCS_SHIFT 52U116#define ROGUE_CR_CLK_CTRL_USCS_CLRMSK 0xFFCFFFFFFFFFFFFFULL117#define ROGUE_CR_CLK_CTRL_USCS_OFF 0x0000000000000000ULL118#define ROGUE_CR_CLK_CTRL_USCS_ON 0x0010000000000000ULL119#define ROGUE_CR_CLK_CTRL_USCS_AUTO 0x0020000000000000ULL120#define ROGUE_CR_CLK_CTRL_PBE_SHIFT 50U121#define ROGUE_CR_CLK_CTRL_PBE_CLRMSK 0xFFF3FFFFFFFFFFFFULL122#define ROGUE_CR_CLK_CTRL_PBE_OFF 0x0000000000000000ULL123#define ROGUE_CR_CLK_CTRL_PBE_ON 0x0004000000000000ULL124#define ROGUE_CR_CLK_CTRL_PBE_AUTO 0x0008000000000000ULL125#define ROGUE_CR_CLK_CTRL_MCU_L1_SHIFT 48U126#define ROGUE_CR_CLK_CTRL_MCU_L1_CLRMSK 0xFFFCFFFFFFFFFFFFULL127#define ROGUE_CR_CLK_CTRL_MCU_L1_OFF 0x0000000000000000ULL128#define ROGUE_CR_CLK_CTRL_MCU_L1_ON 0x0001000000000000ULL129#define ROGUE_CR_CLK_CTRL_MCU_L1_AUTO 0x0002000000000000ULL130#define ROGUE_CR_CLK_CTRL_CDM_SHIFT 46U131#define ROGUE_CR_CLK_CTRL_CDM_CLRMSK 0xFFFF3FFFFFFFFFFFULL132#define ROGUE_CR_CLK_CTRL_CDM_OFF 0x0000000000000000ULL133#define ROGUE_CR_CLK_CTRL_CDM_ON 0x0000400000000000ULL134#define ROGUE_CR_CLK_CTRL_CDM_AUTO 0x0000800000000000ULL135#define ROGUE_CR_CLK_CTRL_SIDEKICK_SHIFT 44U136#define ROGUE_CR_CLK_CTRL_SIDEKICK_CLRMSK 0xFFFFCFFFFFFFFFFFULL137#define ROGUE_CR_CLK_CTRL_SIDEKICK_OFF 0x0000000000000000ULL138#define ROGUE_CR_CLK_CTRL_SIDEKICK_ON 0x0000100000000000ULL139#define ROGUE_CR_CLK_CTRL_SIDEKICK_AUTO 0x0000200000000000ULL140#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_SHIFT 42U141#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_CLRMSK 0xFFFFF3FFFFFFFFFFULL142#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_OFF 0x0000000000000000ULL143#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_ON 0x0000040000000000ULL144#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_AUTO 0x0000080000000000ULL145#define ROGUE_CR_CLK_CTRL_BIF_SHIFT 40U146#define ROGUE_CR_CLK_CTRL_BIF_CLRMSK 0xFFFFFCFFFFFFFFFFULL147#define ROGUE_CR_CLK_CTRL_BIF_OFF 0x0000000000000000ULL148#define ROGUE_CR_CLK_CTRL_BIF_ON 0x0000010000000000ULL149#define ROGUE_CR_CLK_CTRL_BIF_AUTO 0x0000020000000000ULL150#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_SHIFT 28U151#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFCFFFFFFFULL152#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_OFF 0x0000000000000000ULL153#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_ON 0x0000000010000000ULL154#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_AUTO 0x0000000020000000ULL155#define ROGUE_CR_CLK_CTRL_MCU_L0_SHIFT 26U156#define ROGUE_CR_CLK_CTRL_MCU_L0_CLRMSK 0xFFFFFFFFF3FFFFFFULL157#define ROGUE_CR_CLK_CTRL_MCU_L0_OFF 0x0000000000000000ULL158#define ROGUE_CR_CLK_CTRL_MCU_L0_ON 0x0000000004000000ULL159#define ROGUE_CR_CLK_CTRL_MCU_L0_AUTO 0x0000000008000000ULL160#define ROGUE_CR_CLK_CTRL_TPU_SHIFT 24U161#define ROGUE_CR_CLK_CTRL_TPU_CLRMSK 0xFFFFFFFFFCFFFFFFULL162#define ROGUE_CR_CLK_CTRL_TPU_OFF 0x0000000000000000ULL163#define ROGUE_CR_CLK_CTRL_TPU_ON 0x0000000001000000ULL164#define ROGUE_CR_CLK_CTRL_TPU_AUTO 0x0000000002000000ULL165#define ROGUE_CR_CLK_CTRL_USC_SHIFT 20U166#define ROGUE_CR_CLK_CTRL_USC_CLRMSK 0xFFFFFFFFFFCFFFFFULL167#define ROGUE_CR_CLK_CTRL_USC_OFF 0x0000000000000000ULL168#define ROGUE_CR_CLK_CTRL_USC_ON 0x0000000000100000ULL169#define ROGUE_CR_CLK_CTRL_USC_AUTO 0x0000000000200000ULL170#define ROGUE_CR_CLK_CTRL_TLA_SHIFT 18U171#define ROGUE_CR_CLK_CTRL_TLA_CLRMSK 0xFFFFFFFFFFF3FFFFULL172#define ROGUE_CR_CLK_CTRL_TLA_OFF 0x0000000000000000ULL173#define ROGUE_CR_CLK_CTRL_TLA_ON 0x0000000000040000ULL174#define ROGUE_CR_CLK_CTRL_TLA_AUTO 0x0000000000080000ULL175#define ROGUE_CR_CLK_CTRL_SLC_SHIFT 16U176#define ROGUE_CR_CLK_CTRL_SLC_CLRMSK 0xFFFFFFFFFFFCFFFFULL177#define ROGUE_CR_CLK_CTRL_SLC_OFF 0x0000000000000000ULL178#define ROGUE_CR_CLK_CTRL_SLC_ON 0x0000000000010000ULL179#define ROGUE_CR_CLK_CTRL_SLC_AUTO 0x0000000000020000ULL180#define ROGUE_CR_CLK_CTRL_UVS_SHIFT 14U181#define ROGUE_CR_CLK_CTRL_UVS_CLRMSK 0xFFFFFFFFFFFF3FFFULL182#define ROGUE_CR_CLK_CTRL_UVS_OFF 0x0000000000000000ULL183#define ROGUE_CR_CLK_CTRL_UVS_ON 0x0000000000004000ULL184#define ROGUE_CR_CLK_CTRL_UVS_AUTO 0x0000000000008000ULL185#define ROGUE_CR_CLK_CTRL_PDS_SHIFT 12U186#define ROGUE_CR_CLK_CTRL_PDS_CLRMSK 0xFFFFFFFFFFFFCFFFULL187#define ROGUE_CR_CLK_CTRL_PDS_OFF 0x0000000000000000ULL188#define ROGUE_CR_CLK_CTRL_PDS_ON 0x0000000000001000ULL189#define ROGUE_CR_CLK_CTRL_PDS_AUTO 0x0000000000002000ULL190#define ROGUE_CR_CLK_CTRL_VDM_SHIFT 10U191#define ROGUE_CR_CLK_CTRL_VDM_CLRMSK 0xFFFFFFFFFFFFF3FFULL192#define ROGUE_CR_CLK_CTRL_VDM_OFF 0x0000000000000000ULL193#define ROGUE_CR_CLK_CTRL_VDM_ON 0x0000000000000400ULL194#define ROGUE_CR_CLK_CTRL_VDM_AUTO 0x0000000000000800ULL195#define ROGUE_CR_CLK_CTRL_PM_SHIFT 8U196#define ROGUE_CR_CLK_CTRL_PM_CLRMSK 0xFFFFFFFFFFFFFCFFULL197#define ROGUE_CR_CLK_CTRL_PM_OFF 0x0000000000000000ULL198#define ROGUE_CR_CLK_CTRL_PM_ON 0x0000000000000100ULL199#define ROGUE_CR_CLK_CTRL_PM_AUTO 0x0000000000000200ULL200#define ROGUE_CR_CLK_CTRL_GPP_SHIFT 6U201#define ROGUE_CR_CLK_CTRL_GPP_CLRMSK 0xFFFFFFFFFFFFFF3FULL202#define ROGUE_CR_CLK_CTRL_GPP_OFF 0x0000000000000000ULL203#define ROGUE_CR_CLK_CTRL_GPP_ON 0x0000000000000040ULL204#define ROGUE_CR_CLK_CTRL_GPP_AUTO 0x0000000000000080ULL205#define ROGUE_CR_CLK_CTRL_TE_SHIFT 4U206#define ROGUE_CR_CLK_CTRL_TE_CLRMSK 0xFFFFFFFFFFFFFFCFULL207#define ROGUE_CR_CLK_CTRL_TE_OFF 0x0000000000000000ULL208#define ROGUE_CR_CLK_CTRL_TE_ON 0x0000000000000010ULL209#define ROGUE_CR_CLK_CTRL_TE_AUTO 0x0000000000000020ULL210#define ROGUE_CR_CLK_CTRL_TSP_SHIFT 2U211#define ROGUE_CR_CLK_CTRL_TSP_CLRMSK 0xFFFFFFFFFFFFFFF3ULL212#define ROGUE_CR_CLK_CTRL_TSP_OFF 0x0000000000000000ULL213#define ROGUE_CR_CLK_CTRL_TSP_ON 0x0000000000000004ULL214#define ROGUE_CR_CLK_CTRL_TSP_AUTO 0x0000000000000008ULL215#define ROGUE_CR_CLK_CTRL_ISP_SHIFT 0U216#define ROGUE_CR_CLK_CTRL_ISP_CLRMSK 0xFFFFFFFFFFFFFFFCULL217#define ROGUE_CR_CLK_CTRL_ISP_OFF 0x0000000000000000ULL218#define ROGUE_CR_CLK_CTRL_ISP_ON 0x0000000000000001ULL219#define ROGUE_CR_CLK_CTRL_ISP_AUTO 0x0000000000000002ULL220 221/* Register ROGUE_CR_CLK_STATUS */222#define ROGUE_CR_CLK_STATUS 0x0008U223#define ROGUE_CR_CLK_STATUS__PBE2_XE__MASKFULL 0x00000001FFF077FFULL224#define ROGUE_CR_CLK_STATUS__S7_TOP__MASKFULL 0x00000001B3101773ULL225#define ROGUE_CR_CLK_STATUS_MASKFULL 0x00000001FFF077FFULL226#define ROGUE_CR_CLK_STATUS_MCU_FBTC_SHIFT 32U227#define ROGUE_CR_CLK_STATUS_MCU_FBTC_CLRMSK 0xFFFFFFFEFFFFFFFFULL228#define ROGUE_CR_CLK_STATUS_MCU_FBTC_GATED 0x0000000000000000ULL229#define ROGUE_CR_CLK_STATUS_MCU_FBTC_RUNNING 0x0000000100000000ULL230#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_SHIFT 31U231#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_CLRMSK 0xFFFFFFFF7FFFFFFFULL232#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_GATED 0x0000000000000000ULL233#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_RUNNING 0x0000000080000000ULL234#define ROGUE_CR_CLK_STATUS_IPP_SHIFT 30U235#define ROGUE_CR_CLK_STATUS_IPP_CLRMSK 0xFFFFFFFFBFFFFFFFULL236#define ROGUE_CR_CLK_STATUS_IPP_GATED 0x0000000000000000ULL237#define ROGUE_CR_CLK_STATUS_IPP_RUNNING 0x0000000040000000ULL238#define ROGUE_CR_CLK_STATUS_FBC_SHIFT 29U239#define ROGUE_CR_CLK_STATUS_FBC_CLRMSK 0xFFFFFFFFDFFFFFFFULL240#define ROGUE_CR_CLK_STATUS_FBC_GATED 0x0000000000000000ULL241#define ROGUE_CR_CLK_STATUS_FBC_RUNNING 0x0000000020000000ULL242#define ROGUE_CR_CLK_STATUS_FBDC_SHIFT 28U243#define ROGUE_CR_CLK_STATUS_FBDC_CLRMSK 0xFFFFFFFFEFFFFFFFULL244#define ROGUE_CR_CLK_STATUS_FBDC_GATED 0x0000000000000000ULL245#define ROGUE_CR_CLK_STATUS_FBDC_RUNNING 0x0000000010000000ULL246#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_SHIFT 27U247#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_CLRMSK 0xFFFFFFFFF7FFFFFFULL248#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_GATED 0x0000000000000000ULL249#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_RUNNING 0x0000000008000000ULL250#define ROGUE_CR_CLK_STATUS_USCS_SHIFT 26U251#define ROGUE_CR_CLK_STATUS_USCS_CLRMSK 0xFFFFFFFFFBFFFFFFULL252#define ROGUE_CR_CLK_STATUS_USCS_GATED 0x0000000000000000ULL253#define ROGUE_CR_CLK_STATUS_USCS_RUNNING 0x0000000004000000ULL254#define ROGUE_CR_CLK_STATUS_PBE_SHIFT 25U255#define ROGUE_CR_CLK_STATUS_PBE_CLRMSK 0xFFFFFFFFFDFFFFFFULL256#define ROGUE_CR_CLK_STATUS_PBE_GATED 0x0000000000000000ULL257#define ROGUE_CR_CLK_STATUS_PBE_RUNNING 0x0000000002000000ULL258#define ROGUE_CR_CLK_STATUS_MCU_L1_SHIFT 24U259#define ROGUE_CR_CLK_STATUS_MCU_L1_CLRMSK 0xFFFFFFFFFEFFFFFFULL260#define ROGUE_CR_CLK_STATUS_MCU_L1_GATED 0x0000000000000000ULL261#define ROGUE_CR_CLK_STATUS_MCU_L1_RUNNING 0x0000000001000000ULL262#define ROGUE_CR_CLK_STATUS_CDM_SHIFT 23U263#define ROGUE_CR_CLK_STATUS_CDM_CLRMSK 0xFFFFFFFFFF7FFFFFULL264#define ROGUE_CR_CLK_STATUS_CDM_GATED 0x0000000000000000ULL265#define ROGUE_CR_CLK_STATUS_CDM_RUNNING 0x0000000000800000ULL266#define ROGUE_CR_CLK_STATUS_SIDEKICK_SHIFT 22U267#define ROGUE_CR_CLK_STATUS_SIDEKICK_CLRMSK 0xFFFFFFFFFFBFFFFFULL268#define ROGUE_CR_CLK_STATUS_SIDEKICK_GATED 0x0000000000000000ULL269#define ROGUE_CR_CLK_STATUS_SIDEKICK_RUNNING 0x0000000000400000ULL270#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_SHIFT 21U271#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_CLRMSK 0xFFFFFFFFFFDFFFFFULL272#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_GATED 0x0000000000000000ULL273#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_RUNNING 0x0000000000200000ULL274#define ROGUE_CR_CLK_STATUS_BIF_SHIFT 20U275#define ROGUE_CR_CLK_STATUS_BIF_CLRMSK 0xFFFFFFFFFFEFFFFFULL276#define ROGUE_CR_CLK_STATUS_BIF_GATED 0x0000000000000000ULL277#define ROGUE_CR_CLK_STATUS_BIF_RUNNING 0x0000000000100000ULL278#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_SHIFT 14U279#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFBFFFULL280#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_GATED 0x0000000000000000ULL281#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_RUNNING 0x0000000000004000ULL282#define ROGUE_CR_CLK_STATUS_MCU_L0_SHIFT 13U283#define ROGUE_CR_CLK_STATUS_MCU_L0_CLRMSK 0xFFFFFFFFFFFFDFFFULL284#define ROGUE_CR_CLK_STATUS_MCU_L0_GATED 0x0000000000000000ULL285#define ROGUE_CR_CLK_STATUS_MCU_L0_RUNNING 0x0000000000002000ULL286#define ROGUE_CR_CLK_STATUS_TPU_SHIFT 12U287#define ROGUE_CR_CLK_STATUS_TPU_CLRMSK 0xFFFFFFFFFFFFEFFFULL288#define ROGUE_CR_CLK_STATUS_TPU_GATED 0x0000000000000000ULL289#define ROGUE_CR_CLK_STATUS_TPU_RUNNING 0x0000000000001000ULL290#define ROGUE_CR_CLK_STATUS_USC_SHIFT 10U291#define ROGUE_CR_CLK_STATUS_USC_CLRMSK 0xFFFFFFFFFFFFFBFFULL292#define ROGUE_CR_CLK_STATUS_USC_GATED 0x0000000000000000ULL293#define ROGUE_CR_CLK_STATUS_USC_RUNNING 0x0000000000000400ULL294#define ROGUE_CR_CLK_STATUS_TLA_SHIFT 9U295#define ROGUE_CR_CLK_STATUS_TLA_CLRMSK 0xFFFFFFFFFFFFFDFFULL296#define ROGUE_CR_CLK_STATUS_TLA_GATED 0x0000000000000000ULL297#define ROGUE_CR_CLK_STATUS_TLA_RUNNING 0x0000000000000200ULL298#define ROGUE_CR_CLK_STATUS_SLC_SHIFT 8U299#define ROGUE_CR_CLK_STATUS_SLC_CLRMSK 0xFFFFFFFFFFFFFEFFULL300#define ROGUE_CR_CLK_STATUS_SLC_GATED 0x0000000000000000ULL301#define ROGUE_CR_CLK_STATUS_SLC_RUNNING 0x0000000000000100ULL302#define ROGUE_CR_CLK_STATUS_UVS_SHIFT 7U303#define ROGUE_CR_CLK_STATUS_UVS_CLRMSK 0xFFFFFFFFFFFFFF7FULL304#define ROGUE_CR_CLK_STATUS_UVS_GATED 0x0000000000000000ULL305#define ROGUE_CR_CLK_STATUS_UVS_RUNNING 0x0000000000000080ULL306#define ROGUE_CR_CLK_STATUS_PDS_SHIFT 6U307#define ROGUE_CR_CLK_STATUS_PDS_CLRMSK 0xFFFFFFFFFFFFFFBFULL308#define ROGUE_CR_CLK_STATUS_PDS_GATED 0x0000000000000000ULL309#define ROGUE_CR_CLK_STATUS_PDS_RUNNING 0x0000000000000040ULL310#define ROGUE_CR_CLK_STATUS_VDM_SHIFT 5U311#define ROGUE_CR_CLK_STATUS_VDM_CLRMSK 0xFFFFFFFFFFFFFFDFULL312#define ROGUE_CR_CLK_STATUS_VDM_GATED 0x0000000000000000ULL313#define ROGUE_CR_CLK_STATUS_VDM_RUNNING 0x0000000000000020ULL314#define ROGUE_CR_CLK_STATUS_PM_SHIFT 4U315#define ROGUE_CR_CLK_STATUS_PM_CLRMSK 0xFFFFFFFFFFFFFFEFULL316#define ROGUE_CR_CLK_STATUS_PM_GATED 0x0000000000000000ULL317#define ROGUE_CR_CLK_STATUS_PM_RUNNING 0x0000000000000010ULL318#define ROGUE_CR_CLK_STATUS_GPP_SHIFT 3U319#define ROGUE_CR_CLK_STATUS_GPP_CLRMSK 0xFFFFFFFFFFFFFFF7ULL320#define ROGUE_CR_CLK_STATUS_GPP_GATED 0x0000000000000000ULL321#define ROGUE_CR_CLK_STATUS_GPP_RUNNING 0x0000000000000008ULL322#define ROGUE_CR_CLK_STATUS_TE_SHIFT 2U323#define ROGUE_CR_CLK_STATUS_TE_CLRMSK 0xFFFFFFFFFFFFFFFBULL324#define ROGUE_CR_CLK_STATUS_TE_GATED 0x0000000000000000ULL325#define ROGUE_CR_CLK_STATUS_TE_RUNNING 0x0000000000000004ULL326#define ROGUE_CR_CLK_STATUS_TSP_SHIFT 1U327#define ROGUE_CR_CLK_STATUS_TSP_CLRMSK 0xFFFFFFFFFFFFFFFDULL328#define ROGUE_CR_CLK_STATUS_TSP_GATED 0x0000000000000000ULL329#define ROGUE_CR_CLK_STATUS_TSP_RUNNING 0x0000000000000002ULL330#define ROGUE_CR_CLK_STATUS_ISP_SHIFT 0U331#define ROGUE_CR_CLK_STATUS_ISP_CLRMSK 0xFFFFFFFFFFFFFFFEULL332#define ROGUE_CR_CLK_STATUS_ISP_GATED 0x0000000000000000ULL333#define ROGUE_CR_CLK_STATUS_ISP_RUNNING 0x0000000000000001ULL334 335/* Register ROGUE_CR_CORE_ID */336#define ROGUE_CR_CORE_ID__PBVNC 0x0020U337#define ROGUE_CR_CORE_ID__PBVNC__MASKFULL 0xFFFFFFFFFFFFFFFFULL338#define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_SHIFT 48U339#define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_CLRMSK 0x0000FFFFFFFFFFFFULL340#define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_SHIFT 32U341#define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_CLRMSK 0xFFFF0000FFFFFFFFULL342#define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_SHIFT 16U343#define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_CLRMSK 0xFFFFFFFF0000FFFFULL344#define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_SHIFT 0U345#define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_CLRMSK 0xFFFFFFFFFFFF0000ULL346 347/* Register ROGUE_CR_CORE_ID */348#define ROGUE_CR_CORE_ID 0x0018U349#define ROGUE_CR_CORE_ID_MASKFULL 0x00000000FFFFFFFFULL350#define ROGUE_CR_CORE_ID_ID_SHIFT 16U351#define ROGUE_CR_CORE_ID_ID_CLRMSK 0x0000FFFFU352#define ROGUE_CR_CORE_ID_CONFIG_SHIFT 0U353#define ROGUE_CR_CORE_ID_CONFIG_CLRMSK 0xFFFF0000U354 355/* Register ROGUE_CR_CORE_REVISION */356#define ROGUE_CR_CORE_REVISION 0x0020U357#define ROGUE_CR_CORE_REVISION_MASKFULL 0x00000000FFFFFFFFULL358#define ROGUE_CR_CORE_REVISION_DESIGNER_SHIFT 24U359#define ROGUE_CR_CORE_REVISION_DESIGNER_CLRMSK 0x00FFFFFFU360#define ROGUE_CR_CORE_REVISION_MAJOR_SHIFT 16U361#define ROGUE_CR_CORE_REVISION_MAJOR_CLRMSK 0xFF00FFFFU362#define ROGUE_CR_CORE_REVISION_MINOR_SHIFT 8U363#define ROGUE_CR_CORE_REVISION_MINOR_CLRMSK 0xFFFF00FFU364#define ROGUE_CR_CORE_REVISION_MAINTENANCE_SHIFT 0U365#define ROGUE_CR_CORE_REVISION_MAINTENANCE_CLRMSK 0xFFFFFF00U366 367/* Register ROGUE_CR_DESIGNER_REV_FIELD1 */368#define ROGUE_CR_DESIGNER_REV_FIELD1 0x0028U369#define ROGUE_CR_DESIGNER_REV_FIELD1_MASKFULL 0x00000000FFFFFFFFULL370#define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0U371#define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_CLRMSK 0x00000000U372 373/* Register ROGUE_CR_DESIGNER_REV_FIELD2 */374#define ROGUE_CR_DESIGNER_REV_FIELD2 0x0030U375#define ROGUE_CR_DESIGNER_REV_FIELD2_MASKFULL 0x00000000FFFFFFFFULL376#define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0U377#define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_CLRMSK 0x00000000U378 379/* Register ROGUE_CR_CHANGESET_NUMBER */380#define ROGUE_CR_CHANGESET_NUMBER 0x0040U381#define ROGUE_CR_CHANGESET_NUMBER_MASKFULL 0xFFFFFFFFFFFFFFFFULL382#define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_SHIFT 0U383#define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK 0x0000000000000000ULL384 385/* Register ROGUE_CR_CLK_XTPLUS_CTRL */386#define ROGUE_CR_CLK_XTPLUS_CTRL 0x0080U387#define ROGUE_CR_CLK_XTPLUS_CTRL_MASKFULL 0x0000003FFFFF0000ULL388#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_SHIFT 36U389#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_CLRMSK 0xFFFFFFCFFFFFFFFFULL390#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_OFF 0x0000000000000000ULL391#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_ON 0x0000001000000000ULL392#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_AUTO 0x0000002000000000ULL393#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_SHIFT 34U394#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_CLRMSK 0xFFFFFFF3FFFFFFFFULL395#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_OFF 0x0000000000000000ULL396#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_ON 0x0000000400000000ULL397#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_AUTO 0x0000000800000000ULL398#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_SHIFT 32U399#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_CLRMSK 0xFFFFFFFCFFFFFFFFULL400#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_OFF 0x0000000000000000ULL401#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_ON 0x0000000100000000ULL402#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_AUTO 0x0000000200000000ULL403#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_SHIFT 30U404#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_CLRMSK 0xFFFFFFFF3FFFFFFFULL405#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_OFF 0x0000000000000000ULL406#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_ON 0x0000000040000000ULL407#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_AUTO 0x0000000080000000ULL408#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_SHIFT 28U409#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_CLRMSK 0xFFFFFFFFCFFFFFFFULL410#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_OFF 0x0000000000000000ULL411#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_ON 0x0000000010000000ULL412#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_AUTO 0x0000000020000000ULL413#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_SHIFT 26U414#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_CLRMSK 0xFFFFFFFFF3FFFFFFULL415#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_OFF 0x0000000000000000ULL416#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_ON 0x0000000004000000ULL417#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_AUTO 0x0000000008000000ULL418#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_SHIFT 24U419#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_CLRMSK 0xFFFFFFFFFCFFFFFFULL420#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_OFF 0x0000000000000000ULL421#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_ON 0x0000000001000000ULL422#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_AUTO 0x0000000002000000ULL423#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_SHIFT 22U424#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_CLRMSK 0xFFFFFFFFFF3FFFFFULL425#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_OFF 0x0000000000000000ULL426#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_ON 0x0000000000400000ULL427#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_AUTO 0x0000000000800000ULL428#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_SHIFT 20U429#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFCFFFFFULL430#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_OFF 0x0000000000000000ULL431#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_ON 0x0000000000100000ULL432#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_AUTO 0x0000000000200000ULL433#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_SHIFT 18U434#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_CLRMSK 0xFFFFFFFFFFF3FFFFULL435#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_OFF 0x0000000000000000ULL436#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_ON 0x0000000000040000ULL437#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_AUTO 0x0000000000080000ULL438#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_SHIFT 16U439#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_CLRMSK 0xFFFFFFFFFFFCFFFFULL440#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_OFF 0x0000000000000000ULL441#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_ON 0x0000000000010000ULL442#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_AUTO 0x0000000000020000ULL443 444/* Register ROGUE_CR_CLK_XTPLUS_STATUS */445#define ROGUE_CR_CLK_XTPLUS_STATUS 0x0088U446#define ROGUE_CR_CLK_XTPLUS_STATUS_MASKFULL 0x00000000000007FFULL447#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_SHIFT 10U448#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_CLRMSK 0xFFFFFFFFFFFFFBFFULL449#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_GATED 0x0000000000000000ULL450#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_RUNNING 0x0000000000000400ULL451#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_SHIFT 9U452#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_CLRMSK 0xFFFFFFFFFFFFFDFFULL453#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_GATED 0x0000000000000000ULL454#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_RUNNING 0x0000000000000200ULL455#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_SHIFT 8U456#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFEFFULL457#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_GATED 0x0000000000000000ULL458#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_RUNNING 0x0000000000000100ULL459#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_SHIFT 7U460#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_CLRMSK 0xFFFFFFFFFFFFFF7FULL461#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_GATED 0x0000000000000000ULL462#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_RUNNING 0x0000000000000080ULL463#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_SHIFT 6U464#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFBFULL465#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_GATED 0x0000000000000000ULL466#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_RUNNING 0x0000000000000040ULL467#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_SHIFT 5U468#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_CLRMSK 0xFFFFFFFFFFFFFFDFULL469#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_GATED 0x0000000000000000ULL470#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_RUNNING 0x0000000000000020ULL471#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_SHIFT 4U472#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_CLRMSK 0xFFFFFFFFFFFFFFEFULL473#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_GATED 0x0000000000000000ULL474#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_RUNNING 0x0000000000000010ULL475#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_SHIFT 3U476#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_CLRMSK 0xFFFFFFFFFFFFFFF7ULL477#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_GATED 0x0000000000000000ULL478#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_RUNNING 0x0000000000000008ULL479#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_SHIFT 2U480#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFFFFFFBULL481#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_GATED 0x0000000000000000ULL482#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_RUNNING 0x0000000000000004ULL483#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_SHIFT 1U484#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_CLRMSK 0xFFFFFFFFFFFFFFFDULL485#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_GATED 0x0000000000000000ULL486#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_RUNNING 0x0000000000000002ULL487#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_SHIFT 0U488#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_CLRMSK 0xFFFFFFFFFFFFFFFEULL489#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_GATED 0x0000000000000000ULL490#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_RUNNING 0x0000000000000001ULL491 492/* Register ROGUE_CR_SOFT_RESET */493#define ROGUE_CR_SOFT_RESET 0x0100U494#define ROGUE_CR_SOFT_RESET__PBE2_XE__MASKFULL 0xFFEFFFFFFFFFFC3DULL495#define ROGUE_CR_SOFT_RESET_MASKFULL 0x00E7FFFFFFFFFC3DULL496#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_SHIFT 63U497#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_CLRMSK 0x7FFFFFFFFFFFFFFFULL498#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_EN 0x8000000000000000ULL499#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_SHIFT 62U500#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_CLRMSK 0xBFFFFFFFFFFFFFFFULL501#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_EN 0x4000000000000000ULL502#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_SHIFT 61U503#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_CLRMSK 0xDFFFFFFFFFFFFFFFULL504#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_EN 0x2000000000000000ULL505#define ROGUE_CR_SOFT_RESET_JONES_CORE_SHIFT 60U506#define ROGUE_CR_SOFT_RESET_JONES_CORE_CLRMSK 0xEFFFFFFFFFFFFFFFULL507#define ROGUE_CR_SOFT_RESET_JONES_CORE_EN 0x1000000000000000ULL508#define ROGUE_CR_SOFT_RESET_TILING_CORE_SHIFT 59U509#define ROGUE_CR_SOFT_RESET_TILING_CORE_CLRMSK 0xF7FFFFFFFFFFFFFFULL510#define ROGUE_CR_SOFT_RESET_TILING_CORE_EN 0x0800000000000000ULL511#define ROGUE_CR_SOFT_RESET_TE3_SHIFT 58U512#define ROGUE_CR_SOFT_RESET_TE3_CLRMSK 0xFBFFFFFFFFFFFFFFULL513#define ROGUE_CR_SOFT_RESET_TE3_EN 0x0400000000000000ULL514#define ROGUE_CR_SOFT_RESET_VCE_SHIFT 57U515#define ROGUE_CR_SOFT_RESET_VCE_CLRMSK 0xFDFFFFFFFFFFFFFFULL516#define ROGUE_CR_SOFT_RESET_VCE_EN 0x0200000000000000ULL517#define ROGUE_CR_SOFT_RESET_VBS_SHIFT 56U518#define ROGUE_CR_SOFT_RESET_VBS_CLRMSK 0xFEFFFFFFFFFFFFFFULL519#define ROGUE_CR_SOFT_RESET_VBS_EN 0x0100000000000000ULL520#define ROGUE_CR_SOFT_RESET_DPX1_CORE_SHIFT 55U521#define ROGUE_CR_SOFT_RESET_DPX1_CORE_CLRMSK 0xFF7FFFFFFFFFFFFFULL522#define ROGUE_CR_SOFT_RESET_DPX1_CORE_EN 0x0080000000000000ULL523#define ROGUE_CR_SOFT_RESET_DPX0_CORE_SHIFT 54U524#define ROGUE_CR_SOFT_RESET_DPX0_CORE_CLRMSK 0xFFBFFFFFFFFFFFFFULL525#define ROGUE_CR_SOFT_RESET_DPX0_CORE_EN 0x0040000000000000ULL526#define ROGUE_CR_SOFT_RESET_FBA_SHIFT 53U527#define ROGUE_CR_SOFT_RESET_FBA_CLRMSK 0xFFDFFFFFFFFFFFFFULL528#define ROGUE_CR_SOFT_RESET_FBA_EN 0x0020000000000000ULL529#define ROGUE_CR_SOFT_RESET_FB_CDC_SHIFT 51U530#define ROGUE_CR_SOFT_RESET_FB_CDC_CLRMSK 0xFFF7FFFFFFFFFFFFULL531#define ROGUE_CR_SOFT_RESET_FB_CDC_EN 0x0008000000000000ULL532#define ROGUE_CR_SOFT_RESET_SH_SHIFT 50U533#define ROGUE_CR_SOFT_RESET_SH_CLRMSK 0xFFFBFFFFFFFFFFFFULL534#define ROGUE_CR_SOFT_RESET_SH_EN 0x0004000000000000ULL535#define ROGUE_CR_SOFT_RESET_VRDM_SHIFT 49U536#define ROGUE_CR_SOFT_RESET_VRDM_CLRMSK 0xFFFDFFFFFFFFFFFFULL537#define ROGUE_CR_SOFT_RESET_VRDM_EN 0x0002000000000000ULL538#define ROGUE_CR_SOFT_RESET_MCU_FBTC_SHIFT 48U539#define ROGUE_CR_SOFT_RESET_MCU_FBTC_CLRMSK 0xFFFEFFFFFFFFFFFFULL540#define ROGUE_CR_SOFT_RESET_MCU_FBTC_EN 0x0001000000000000ULL541#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_SHIFT 47U542#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_CLRMSK 0xFFFF7FFFFFFFFFFFULL543#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_EN 0x0000800000000000ULL544#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_SHIFT 46U545#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_CLRMSK 0xFFFFBFFFFFFFFFFFULL546#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_EN 0x0000400000000000ULL547#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_SHIFT 45U548#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_CLRMSK 0xFFFFDFFFFFFFFFFFULL549#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_EN 0x0000200000000000ULL550#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_SHIFT 44U551#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_CLRMSK 0xFFFFEFFFFFFFFFFFULL552#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_EN 0x0000100000000000ULL553#define ROGUE_CR_SOFT_RESET_IPP_SHIFT 43U554#define ROGUE_CR_SOFT_RESET_IPP_CLRMSK 0xFFFFF7FFFFFFFFFFULL555#define ROGUE_CR_SOFT_RESET_IPP_EN 0x0000080000000000ULL556#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_SHIFT 42U557#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_CLRMSK 0xFFFFFBFFFFFFFFFFULL558#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_EN 0x0000040000000000ULL559#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_SHIFT 41U560#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_CLRMSK 0xFFFFFDFFFFFFFFFFULL561#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_EN 0x0000020000000000ULL562#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_SHIFT 40U563#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_CLRMSK 0xFFFFFEFFFFFFFFFFULL564#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN 0x0000010000000000ULL565#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_SHIFT 39U566#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_CLRMSK 0xFFFFFF7FFFFFFFFFULL567#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN 0x0000008000000000ULL568#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_SHIFT 38U569#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_CLRMSK 0xFFFFFFBFFFFFFFFFULL570#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN 0x0000004000000000ULL571#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_SHIFT 37U572#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_CLRMSK 0xFFFFFFDFFFFFFFFFULL573#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN 0x0000002000000000ULL574#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_SHIFT 36U575#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_CLRMSK 0xFFFFFFEFFFFFFFFFULL576#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN 0x0000001000000000ULL577#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_SHIFT 35U578#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_CLRMSK 0xFFFFFFF7FFFFFFFFULL579#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN 0x0000000800000000ULL580#define ROGUE_CR_SOFT_RESET_MMU_SHIFT 34U581#define ROGUE_CR_SOFT_RESET_MMU_CLRMSK 0xFFFFFFFBFFFFFFFFULL582#define ROGUE_CR_SOFT_RESET_MMU_EN 0x0000000400000000ULL583#define ROGUE_CR_SOFT_RESET_BIF1_SHIFT 33U584#define ROGUE_CR_SOFT_RESET_BIF1_CLRMSK 0xFFFFFFFDFFFFFFFFULL585#define ROGUE_CR_SOFT_RESET_BIF1_EN 0x0000000200000000ULL586#define ROGUE_CR_SOFT_RESET_GARTEN_SHIFT 32U587#define ROGUE_CR_SOFT_RESET_GARTEN_CLRMSK 0xFFFFFFFEFFFFFFFFULL588#define ROGUE_CR_SOFT_RESET_GARTEN_EN 0x0000000100000000ULL589#define ROGUE_CR_SOFT_RESET_CPU_SHIFT 32U590#define ROGUE_CR_SOFT_RESET_CPU_CLRMSK 0xFFFFFFFEFFFFFFFFULL591#define ROGUE_CR_SOFT_RESET_CPU_EN 0x0000000100000000ULL592#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_SHIFT 31U593#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_CLRMSK 0xFFFFFFFF7FFFFFFFULL594#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN 0x0000000080000000ULL595#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_SHIFT 30U596#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_CLRMSK 0xFFFFFFFFBFFFFFFFULL597#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN 0x0000000040000000ULL598#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_SHIFT 29U599#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_CLRMSK 0xFFFFFFFFDFFFFFFFULL600#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN 0x0000000020000000ULL601#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_SHIFT 28U602#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_CLRMSK 0xFFFFFFFFEFFFFFFFULL603#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_EN 0x0000000010000000ULL604#define ROGUE_CR_SOFT_RESET_SLC_SHIFT 27U605#define ROGUE_CR_SOFT_RESET_SLC_CLRMSK 0xFFFFFFFFF7FFFFFFULL606#define ROGUE_CR_SOFT_RESET_SLC_EN 0x0000000008000000ULL607#define ROGUE_CR_SOFT_RESET_TLA_SHIFT 26U608#define ROGUE_CR_SOFT_RESET_TLA_CLRMSK 0xFFFFFFFFFBFFFFFFULL609#define ROGUE_CR_SOFT_RESET_TLA_EN 0x0000000004000000ULL610#define ROGUE_CR_SOFT_RESET_UVS_SHIFT 25U611#define ROGUE_CR_SOFT_RESET_UVS_CLRMSK 0xFFFFFFFFFDFFFFFFULL612#define ROGUE_CR_SOFT_RESET_UVS_EN 0x0000000002000000ULL613#define ROGUE_CR_SOFT_RESET_TE_SHIFT 24U614#define ROGUE_CR_SOFT_RESET_TE_CLRMSK 0xFFFFFFFFFEFFFFFFULL615#define ROGUE_CR_SOFT_RESET_TE_EN 0x0000000001000000ULL616#define ROGUE_CR_SOFT_RESET_GPP_SHIFT 23U617#define ROGUE_CR_SOFT_RESET_GPP_CLRMSK 0xFFFFFFFFFF7FFFFFULL618#define ROGUE_CR_SOFT_RESET_GPP_EN 0x0000000000800000ULL619#define ROGUE_CR_SOFT_RESET_FBDC_SHIFT 22U620#define ROGUE_CR_SOFT_RESET_FBDC_CLRMSK 0xFFFFFFFFFFBFFFFFULL621#define ROGUE_CR_SOFT_RESET_FBDC_EN 0x0000000000400000ULL622#define ROGUE_CR_SOFT_RESET_FBC_SHIFT 21U623#define ROGUE_CR_SOFT_RESET_FBC_CLRMSK 0xFFFFFFFFFFDFFFFFULL624#define ROGUE_CR_SOFT_RESET_FBC_EN 0x0000000000200000ULL625#define ROGUE_CR_SOFT_RESET_PM_SHIFT 20U626#define ROGUE_CR_SOFT_RESET_PM_CLRMSK 0xFFFFFFFFFFEFFFFFULL627#define ROGUE_CR_SOFT_RESET_PM_EN 0x0000000000100000ULL628#define ROGUE_CR_SOFT_RESET_PBE_SHIFT 19U629#define ROGUE_CR_SOFT_RESET_PBE_CLRMSK 0xFFFFFFFFFFF7FFFFULL630#define ROGUE_CR_SOFT_RESET_PBE_EN 0x0000000000080000ULL631#define ROGUE_CR_SOFT_RESET_USC_SHARED_SHIFT 18U632#define ROGUE_CR_SOFT_RESET_USC_SHARED_CLRMSK 0xFFFFFFFFFFFBFFFFULL633#define ROGUE_CR_SOFT_RESET_USC_SHARED_EN 0x0000000000040000ULL634#define ROGUE_CR_SOFT_RESET_MCU_L1_SHIFT 17U635#define ROGUE_CR_SOFT_RESET_MCU_L1_CLRMSK 0xFFFFFFFFFFFDFFFFULL636#define ROGUE_CR_SOFT_RESET_MCU_L1_EN 0x0000000000020000ULL637#define ROGUE_CR_SOFT_RESET_BIF_SHIFT 16U638#define ROGUE_CR_SOFT_RESET_BIF_CLRMSK 0xFFFFFFFFFFFEFFFFULL639#define ROGUE_CR_SOFT_RESET_BIF_EN 0x0000000000010000ULL640#define ROGUE_CR_SOFT_RESET_CDM_SHIFT 15U641#define ROGUE_CR_SOFT_RESET_CDM_CLRMSK 0xFFFFFFFFFFFF7FFFULL642#define ROGUE_CR_SOFT_RESET_CDM_EN 0x0000000000008000ULL643#define ROGUE_CR_SOFT_RESET_VDM_SHIFT 14U644#define ROGUE_CR_SOFT_RESET_VDM_CLRMSK 0xFFFFFFFFFFFFBFFFULL645#define ROGUE_CR_SOFT_RESET_VDM_EN 0x0000000000004000ULL646#define ROGUE_CR_SOFT_RESET_TESS_SHIFT 13U647#define ROGUE_CR_SOFT_RESET_TESS_CLRMSK 0xFFFFFFFFFFFFDFFFULL648#define ROGUE_CR_SOFT_RESET_TESS_EN 0x0000000000002000ULL649#define ROGUE_CR_SOFT_RESET_PDS_SHIFT 12U650#define ROGUE_CR_SOFT_RESET_PDS_CLRMSK 0xFFFFFFFFFFFFEFFFULL651#define ROGUE_CR_SOFT_RESET_PDS_EN 0x0000000000001000ULL652#define ROGUE_CR_SOFT_RESET_ISP_SHIFT 11U653#define ROGUE_CR_SOFT_RESET_ISP_CLRMSK 0xFFFFFFFFFFFFF7FFULL654#define ROGUE_CR_SOFT_RESET_ISP_EN 0x0000000000000800ULL655#define ROGUE_CR_SOFT_RESET_TSP_SHIFT 10U656#define ROGUE_CR_SOFT_RESET_TSP_CLRMSK 0xFFFFFFFFFFFFFBFFULL657#define ROGUE_CR_SOFT_RESET_TSP_EN 0x0000000000000400ULL658#define ROGUE_CR_SOFT_RESET_SYSARB_SHIFT 5U659#define ROGUE_CR_SOFT_RESET_SYSARB_CLRMSK 0xFFFFFFFFFFFFFFDFULL660#define ROGUE_CR_SOFT_RESET_SYSARB_EN 0x0000000000000020ULL661#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_SHIFT 4U662#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFFFEFULL663#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_EN 0x0000000000000010ULL664#define ROGUE_CR_SOFT_RESET_MCU_L0_SHIFT 3U665#define ROGUE_CR_SOFT_RESET_MCU_L0_CLRMSK 0xFFFFFFFFFFFFFFF7ULL666#define ROGUE_CR_SOFT_RESET_MCU_L0_EN 0x0000000000000008ULL667#define ROGUE_CR_SOFT_RESET_TPU_SHIFT 2U668#define ROGUE_CR_SOFT_RESET_TPU_CLRMSK 0xFFFFFFFFFFFFFFFBULL669#define ROGUE_CR_SOFT_RESET_TPU_EN 0x0000000000000004ULL670#define ROGUE_CR_SOFT_RESET_USC_SHIFT 0U671#define ROGUE_CR_SOFT_RESET_USC_CLRMSK 0xFFFFFFFFFFFFFFFEULL672#define ROGUE_CR_SOFT_RESET_USC_EN 0x0000000000000001ULL673 674/* Register ROGUE_CR_SOFT_RESET2 */675#define ROGUE_CR_SOFT_RESET2 0x0108U676#define ROGUE_CR_SOFT_RESET2_MASKFULL 0x00000000001FFFFFULL677#define ROGUE_CR_SOFT_RESET2_SPFILTER_SHIFT 12U678#define ROGUE_CR_SOFT_RESET2_SPFILTER_CLRMSK 0xFFE00FFFU679#define ROGUE_CR_SOFT_RESET2_TDM_SHIFT 11U680#define ROGUE_CR_SOFT_RESET2_TDM_CLRMSK 0xFFFFF7FFU681#define ROGUE_CR_SOFT_RESET2_TDM_EN 0x00000800U682#define ROGUE_CR_SOFT_RESET2_ASTC_SHIFT 10U683#define ROGUE_CR_SOFT_RESET2_ASTC_CLRMSK 0xFFFFFBFFU684#define ROGUE_CR_SOFT_RESET2_ASTC_EN 0x00000400U685#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_SHIFT 9U686#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_CLRMSK 0xFFFFFDFFU687#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN 0x00000200U688#define ROGUE_CR_SOFT_RESET2_USCPS_SHIFT 8U689#define ROGUE_CR_SOFT_RESET2_USCPS_CLRMSK 0xFFFFFEFFU690#define ROGUE_CR_SOFT_RESET2_USCPS_EN 0x00000100U691#define ROGUE_CR_SOFT_RESET2_IPF_SHIFT 7U692#define ROGUE_CR_SOFT_RESET2_IPF_CLRMSK 0xFFFFFF7FU693#define ROGUE_CR_SOFT_RESET2_IPF_EN 0x00000080U694#define ROGUE_CR_SOFT_RESET2_GEOMETRY_SHIFT 6U695#define ROGUE_CR_SOFT_RESET2_GEOMETRY_CLRMSK 0xFFFFFFBFU696#define ROGUE_CR_SOFT_RESET2_GEOMETRY_EN 0x00000040U697#define ROGUE_CR_SOFT_RESET2_USC_SHARED_SHIFT 5U698#define ROGUE_CR_SOFT_RESET2_USC_SHARED_CLRMSK 0xFFFFFFDFU699#define ROGUE_CR_SOFT_RESET2_USC_SHARED_EN 0x00000020U700#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_SHIFT 4U701#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_CLRMSK 0xFFFFFFEFU702#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_EN 0x00000010U703#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_SHIFT 3U704#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_CLRMSK 0xFFFFFFF7U705#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_EN 0x00000008U706#define ROGUE_CR_SOFT_RESET2_PIXEL_SHIFT 2U707#define ROGUE_CR_SOFT_RESET2_PIXEL_CLRMSK 0xFFFFFFFBU708#define ROGUE_CR_SOFT_RESET2_PIXEL_EN 0x00000004U709#define ROGUE_CR_SOFT_RESET2_CDM_SHIFT 1U710#define ROGUE_CR_SOFT_RESET2_CDM_CLRMSK 0xFFFFFFFDU711#define ROGUE_CR_SOFT_RESET2_CDM_EN 0x00000002U712#define ROGUE_CR_SOFT_RESET2_VERTEX_SHIFT 0U713#define ROGUE_CR_SOFT_RESET2_VERTEX_CLRMSK 0xFFFFFFFEU714#define ROGUE_CR_SOFT_RESET2_VERTEX_EN 0x00000001U715 716/* Register ROGUE_CR_EVENT_STATUS */717#define ROGUE_CR_EVENT_STATUS 0x0130U718#define ROGUE_CR_EVENT_STATUS__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL719#define ROGUE_CR_EVENT_STATUS__SIGNALS__MASKFULL 0x00000000E007FFFFULL720#define ROGUE_CR_EVENT_STATUS_MASKFULL 0x00000000FFFFFFFFULL721#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT 31U722#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU723#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_EN 0x80000000U724#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT 30U725#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU726#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_EN 0x40000000U727#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT 29U728#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU729#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U730#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_SHIFT 28U731#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU732#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_EN 0x10000000U733#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_SHIFT 27U734#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU735#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_EN 0x08000000U736#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_SHIFT 26U737#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU738#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_EN 0x04000000U739#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_SHIFT 25U740#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU741#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_EN 0x02000000U742#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_SHIFT 24U743#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU744#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_EN 0x01000000U745#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_SHIFT 23U746#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU747#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_EN 0x00800000U748#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_SHIFT 22U749#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU750#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_EN 0x00400000U751#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_SHIFT 21U752#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU753#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_EN 0x00200000U754#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_SHIFT 20U755#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU756#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_EN 0x00100000U757#define ROGUE_CR_EVENT_STATUS_SAFETY_SHIFT 20U758#define ROGUE_CR_EVENT_STATUS_SAFETY_CLRMSK 0xFFEFFFFFU759#define ROGUE_CR_EVENT_STATUS_SAFETY_EN 0x00100000U760#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_SHIFT 19U761#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU762#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_EN 0x00080000U763#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_SHIFT 19U764#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_CLRMSK 0xFFF7FFFFU765#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_EN 0x00080000U766#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_SHIFT 18U767#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU768#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_EN 0x00040000U769#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U770#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU771#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U772#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_SHIFT 17U773#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_CLRMSK 0xFFFDFFFFU774#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_EN 0x00020000U775#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT 17U776#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU777#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U778#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT 16U779#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU780#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_EN 0x00010000U781#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_SHIFT 15U782#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_CLRMSK 0xFFFF7FFFU783#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_EN 0x00008000U784#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_SHIFT 14U785#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU786#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_EN 0x00004000U787#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_SHIFT 13U788#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_CLRMSK 0xFFFFDFFFU789#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_EN 0x00002000U790#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_SHIFT 12U791#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_CLRMSK 0xFFFFEFFFU792#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_EN 0x00001000U793#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_SHIFT 11U794#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_CLRMSK 0xFFFFF7FFU795#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_EN 0x00000800U796#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT 10U797#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU798#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_EN 0x00000400U799#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT 9U800#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU801#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_EN 0x00000200U802#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_SHIFT 8U803#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU804#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_EN 0x00000100U805#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT 7U806#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU807#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_EN 0x00000080U808#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 6U809#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_CLRMSK 0xFFFFFFBFU810#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_EN 0x00000040U811#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_SHIFT 5U812#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_CLRMSK 0xFFFFFFDFU813#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_EN 0x00000020U814#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT 4U815#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU816#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_EN 0x00000010U817#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 3U818#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U819#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_EN 0x00000008U820#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT 2U821#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU822#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_EN 0x00000004U823#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT 1U824#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU825#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_EN 0x00000002U826#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_SHIFT 0U827#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU828#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U829 830/* Register ROGUE_CR_TIMER */831#define ROGUE_CR_TIMER 0x0160U832#define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL833#define ROGUE_CR_TIMER_BIT31_SHIFT 63U834#define ROGUE_CR_TIMER_BIT31_CLRMSK 0x7FFFFFFFFFFFFFFFULL835#define ROGUE_CR_TIMER_BIT31_EN 0x8000000000000000ULL836#define ROGUE_CR_TIMER_VALUE_SHIFT 0U837#define ROGUE_CR_TIMER_VALUE_CLRMSK 0xFFFF000000000000ULL838 839/* Register ROGUE_CR_TLA_STATUS */840#define ROGUE_CR_TLA_STATUS 0x0178U841#define ROGUE_CR_TLA_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL842#define ROGUE_CR_TLA_STATUS_BLIT_COUNT_SHIFT 39U843#define ROGUE_CR_TLA_STATUS_BLIT_COUNT_CLRMSK 0x0000007FFFFFFFFFULL844#define ROGUE_CR_TLA_STATUS_REQUEST_SHIFT 7U845#define ROGUE_CR_TLA_STATUS_REQUEST_CLRMSK 0xFFFFFF800000007FULL846#define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_SHIFT 1U847#define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_CLRMSK 0xFFFFFFFFFFFFFF81ULL848#define ROGUE_CR_TLA_STATUS_BUSY_SHIFT 0U849#define ROGUE_CR_TLA_STATUS_BUSY_CLRMSK 0xFFFFFFFFFFFFFFFEULL850#define ROGUE_CR_TLA_STATUS_BUSY_EN 0x0000000000000001ULL851 852/* Register ROGUE_CR_PM_PARTIAL_RENDER_ENABLE */853#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE 0x0338U854#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_MASKFULL 0x0000000000000001ULL855#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT 0U856#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_CLRMSK 0xFFFFFFFEU857#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_EN 0x00000001U858 859/* Register ROGUE_CR_SIDEKICK_IDLE */860#define ROGUE_CR_SIDEKICK_IDLE 0x03C8U861#define ROGUE_CR_SIDEKICK_IDLE_MASKFULL 0x000000000000007FULL862#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_SHIFT 6U863#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_CLRMSK 0xFFFFFFBFU864#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_EN 0x00000040U865#define ROGUE_CR_SIDEKICK_IDLE_MMU_SHIFT 5U866#define ROGUE_CR_SIDEKICK_IDLE_MMU_CLRMSK 0xFFFFFFDFU867#define ROGUE_CR_SIDEKICK_IDLE_MMU_EN 0x00000020U868#define ROGUE_CR_SIDEKICK_IDLE_BIF128_SHIFT 4U869#define ROGUE_CR_SIDEKICK_IDLE_BIF128_CLRMSK 0xFFFFFFEFU870#define ROGUE_CR_SIDEKICK_IDLE_BIF128_EN 0x00000010U871#define ROGUE_CR_SIDEKICK_IDLE_TLA_SHIFT 3U872#define ROGUE_CR_SIDEKICK_IDLE_TLA_CLRMSK 0xFFFFFFF7U873#define ROGUE_CR_SIDEKICK_IDLE_TLA_EN 0x00000008U874#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_SHIFT 2U875#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_CLRMSK 0xFFFFFFFBU876#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN 0x00000004U877#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_SHIFT 1U878#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_CLRMSK 0xFFFFFFFDU879#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN 0x00000002U880#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_SHIFT 0U881#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU882#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN 0x00000001U883 884/* Register ROGUE_CR_MARS_IDLE */885#define ROGUE_CR_MARS_IDLE 0x08F8U886#define ROGUE_CR_MARS_IDLE_MASKFULL 0x0000000000000007ULL887#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_SHIFT 2U888#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFFFBU889#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN 0x00000004U890#define ROGUE_CR_MARS_IDLE_CPU_SHIFT 1U891#define ROGUE_CR_MARS_IDLE_CPU_CLRMSK 0xFFFFFFFDU892#define ROGUE_CR_MARS_IDLE_CPU_EN 0x00000002U893#define ROGUE_CR_MARS_IDLE_SOCIF_SHIFT 0U894#define ROGUE_CR_MARS_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU895#define ROGUE_CR_MARS_IDLE_SOCIF_EN 0x00000001U896 897/* Register ROGUE_CR_VDM_CONTEXT_STORE_STATUS */898#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS 0x0430U899#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_MASKFULL 0x00000000000000F3ULL900#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_SHIFT 4U901#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_CLRMSK 0xFFFFFF0FU902#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U903#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU904#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U905#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U906#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU907#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U908 909/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK0 */910#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0 0x0438U911#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL912#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_SHIFT 32U913#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL914#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_SHIFT 0U915#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL916 917/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK1 */918#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1 0x0440U919#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_MASKFULL 0x00000000FFFFFFFFULL920#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_SHIFT 0U921#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_CLRMSK 0x00000000U922 923/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK2 */924#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2 0x0448U925#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL926#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_SHIFT 32U927#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL928#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_SHIFT 0U929#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL930 931/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 */932#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 0x0450U933#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL934#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_SHIFT 32U935#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL936#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_SHIFT 0U937#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL938 939/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 */940#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 0x0458U941#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_MASKFULL 0x00000000FFFFFFFFULL942#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_SHIFT 0U943#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_CLRMSK 0x00000000U944 945/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 */946#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 0x0460U947#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL948#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_SHIFT 32U949#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL950#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_SHIFT 0U951#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL952 953/* Register ROGUE_CR_CDM_CONTEXT_STORE_STATUS */954#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS 0x04A0U955#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_MASKFULL 0x0000000000000003ULL956#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U957#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU958#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U959#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U960#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU961#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U962 963/* Register ROGUE_CR_CDM_CONTEXT_PDS0 */964#define ROGUE_CR_CDM_CONTEXT_PDS0 0x04A8U965#define ROGUE_CR_CDM_CONTEXT_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL966#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT 36U967#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL968#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT 4U969#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE 16U970#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT 4U971#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL972#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT 4U973#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE 16U974 975/* Register ROGUE_CR_CDM_CONTEXT_PDS1 */976#define ROGUE_CR_CDM_CONTEXT_PDS1 0x04B0U977#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL978#define ROGUE_CR_CDM_CONTEXT_PDS1_MASKFULL 0x000000003FFFFFFFULL979#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U980#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU981#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U982#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT 29U983#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU984#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_EN 0x20000000U985#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U986#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU987#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U988#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT 28U989#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU990#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_EN 0x10000000U991#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_SHIFT 28U992#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU993#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U994#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT 27U995#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_CLRMSK 0xF7FFFFFFU996#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_EN 0x08000000U997#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U998#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU999#define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT 21U1000#define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU1001#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U1002#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU1003#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U1004#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_SHIFT 20U1005#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU1006#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_EN 0x00100000U1007#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U1008#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU1009#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_SHIFT 11U1010#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU1011#define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT 7U1012#define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU1013#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U1014#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU1015#define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT 1U1016#define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U1017#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_SHIFT 0U1018#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_CLRMSK 0xFFFFFFFEU1019#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_EN 0x00000001U1020 1021/* Register ROGUE_CR_CDM_TERMINATE_PDS */1022#define ROGUE_CR_CDM_TERMINATE_PDS 0x04B8U1023#define ROGUE_CR_CDM_TERMINATE_PDS_MASKFULL 0xFFFFFFF0FFFFFFF0ULL1024#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT 36U1025#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL1026#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT 4U1027#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE 16U1028#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT 4U1029#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL1030#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT 4U1031#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE 16U1032 1033/* Register ROGUE_CR_CDM_TERMINATE_PDS1 */1034#define ROGUE_CR_CDM_TERMINATE_PDS1 0x04C0U1035#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL1036#define ROGUE_CR_CDM_TERMINATE_PDS1_MASKFULL 0x000000003FFFFFFFULL1037#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U1038#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU1039#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U1040#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT 29U1041#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU1042#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_EN 0x20000000U1043#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U1044#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU1045#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U1046#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT 28U1047#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU1048#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_EN 0x10000000U1049#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_SHIFT 28U1050#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU1051#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U1052#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_SHIFT 27U1053#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_CLRMSK 0xF7FFFFFFU1054#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_EN 0x08000000U1055#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U1056#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU1057#define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT 21U1058#define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU1059#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U1060#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU1061#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U1062#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_SHIFT 20U1063#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU1064#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_EN 0x00100000U1065#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U1066#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU1067#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_SHIFT 11U1068#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU1069#define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT 7U1070#define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU1071#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U1072#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU1073#define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT 1U1074#define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U1075#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_SHIFT 0U1076#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_CLRMSK 0xFFFFFFFEU1077#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_EN 0x00000001U1078 1079/* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 */1080#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 0x04D8U1081#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL1082#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT 36U1083#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL1084#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT 4U1085#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE 16U1086#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT 4U1087#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL1088#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT 4U1089#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE 16U1090 1091/* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 */1092#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 0x04E0U1093#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL1094#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_MASKFULL 0x000000003FFFFFFFULL1095#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U1096#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU1097#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U1098#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT 29U1099#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU1100#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_EN 0x20000000U1101#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U1102#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU1103#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U1104#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT 28U1105#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU1106#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_EN 0x10000000U1107#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_SHIFT 28U1108#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU1109#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U1110#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_SHIFT 27U1111#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_CLRMSK 0xF7FFFFFFU1112#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_EN 0x08000000U1113#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U1114#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU1115#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT 21U1116#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU1117#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U1118#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU1119#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U1120#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_SHIFT 20U1121#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU1122#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_EN 0x00100000U1123#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U1124#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU1125#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_SHIFT 11U1126#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU1127#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT 7U1128#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU1129#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U1130#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU1131#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT 1U1132#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U1133#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_SHIFT 0U1134#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_CLRMSK 0xFFFFFFFEU1135#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_EN 0x00000001U1136 1137/* Register ROGUE_CR_MIPS_WRAPPER_CONFIG */1138#define ROGUE_CR_MIPS_WRAPPER_CONFIG 0x0810U1139#define ROGUE_CR_MIPS_WRAPPER_CONFIG_MASKFULL 0x000001030F01FFFFULL1140#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_SHIFT 40U1141#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_CLRMSK 0xFFFFFEFFFFFFFFFFULL1142#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_EN 0x0000010000000000ULL1143#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_SHIFT 33U1144#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_CLRMSK 0xFFFFFFFDFFFFFFFFULL1145#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_EN 0x0000000200000000ULL1146#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_SHIFT 32U1147#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_CLRMSK 0xFFFFFFFEFFFFFFFFULL1148#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_EN 0x0000000100000000ULL1149#define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_SHIFT 25U1150#define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_CLRMSK 0xFFFFFFFFF1FFFFFFULL1151#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_SHIFT 24U1152#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFEFFFFFFULL1153#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_EN 0x0000000001000000ULL1154#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_SHIFT 16U1155#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_CLRMSK 0xFFFFFFFFFFFEFFFFULL1156#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MIPS32 0x0000000000000000ULL1157#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS 0x0000000000010000ULL1158#define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_SHIFT 0U1159#define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_CLRMSK 0xFFFFFFFFFFFF0000ULL1160 1161/* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 */1162#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 0x0818U1163#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MASKFULL 0x00000000FFFFF001ULL1164#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_SHIFT 12U1165#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1166#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_SHIFT 0U1167#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1168#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL1169 1170/* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 */1171#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 0x0820U1172#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL1173#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_SHIFT 12U1174#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL1175#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_SHIFT 6U1176#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL1177#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_SHIFT 5U1178#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL1179#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_EN 0x0000000000000020ULL1180#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_SHIFT 0U1181#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL1182 1183/* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 */1184#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 0x0828U1185#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MASKFULL 0x00000000FFFFF001ULL1186#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_SHIFT 12U1187#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1188#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_SHIFT 0U1189#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1190#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL1191 1192/* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 */1193#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 0x0830U1194#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL1195#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_SHIFT 12U1196#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL1197#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_SHIFT 6U1198#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL1199#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_SHIFT 5U1200#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL1201#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_EN 0x0000000000000020ULL1202#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_SHIFT 0U1203#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL1204 1205/* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 */1206#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 0x0838U1207#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MASKFULL 0x00000000FFFFF001ULL1208#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_SHIFT 12U1209#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1210#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_SHIFT 0U1211#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1212#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL1213 1214/* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 */1215#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 0x0840U1216#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL1217#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_SHIFT 12U1218#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL1219#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_SHIFT 6U1220#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL1221#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_SHIFT 5U1222#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL1223#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_EN 0x0000000000000020ULL1224#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_SHIFT 0U1225#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL1226 1227/* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 */1228#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 0x0848U1229#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MASKFULL 0x00000000FFFFF001ULL1230#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_SHIFT 12U1231#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1232#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_SHIFT 0U1233#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1234#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL1235 1236/* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 */1237#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 0x0850U1238#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL1239#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_SHIFT 12U1240#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL1241#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_SHIFT 6U1242#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL1243#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_SHIFT 5U1244#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL1245#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_EN 0x0000000000000020ULL1246#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_SHIFT 0U1247#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL1248 1249/* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 */1250#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 0x0858U1251#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MASKFULL 0x00000000FFFFF001ULL1252#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_SHIFT 12U1253#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1254#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_SHIFT 0U1255#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1256#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL1257 1258/* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 */1259#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 0x0860U1260#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL1261#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_SHIFT 12U1262#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL1263#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_SHIFT 6U1264#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL1265#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_SHIFT 5U1266#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL1267#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_EN 0x0000000000000020ULL1268#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_SHIFT 0U1269#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL1270 1271/* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS */1272#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS 0x0868U1273#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_MASKFULL 0x00000001FFFFFFFFULL1274#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_SHIFT 32U1275#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_CLRMSK 0xFFFFFFFEFFFFFFFFULL1276#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_EN 0x0000000100000000ULL1277#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_SHIFT 0U1278#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_CLRMSK 0xFFFFFFFF00000000ULL1279 1280/* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR */1281#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR 0x0870U1282#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_MASKFULL 0x0000000000000001ULL1283#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_SHIFT 0U1284#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU1285#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_EN 0x00000001U1286 1287/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG */1288#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG 0x0878U1289#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MASKFULL 0xFFFFFFF7FFFFFFBFULL1290#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_SHIFT 36U1291#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL1292#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_SHIFT 32U1293#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL1294#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_SHIFT 12U1295#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1296#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_SHIFT 11U1297#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL1298#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_EN 0x0000000000000800ULL1299#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_SHIFT 7U1300#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL1301#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4KB 0x0000000000000000ULL1302#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16KB 0x0000000000000080ULL1303#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64KB 0x0000000000000100ULL1304#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256KB 0x0000000000000180ULL1305#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_1MB 0x0000000000000200ULL1306#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4MB 0x0000000000000280ULL1307#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16MB 0x0000000000000300ULL1308#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64MB 0x0000000000000380ULL1309#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256MB 0x0000000000000400ULL1310#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_SHIFT 1U1311#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_CLRMSK 0xFFFFFFFFFFFFFFC1ULL1312#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_SHIFT 0U1313#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1314#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_EN 0x0000000000000001ULL1315 1316/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ */1317#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ 0x0880U1318#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_MASKFULL 0x000000000000003FULL1319#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_SHIFT 1U1320#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_CLRMSK 0xFFFFFFC1U1321#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_SHIFT 0U1322#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_CLRMSK 0xFFFFFFFEU1323#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_EN 0x00000001U1324 1325/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA */1326#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA 0x0888U1327#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MASKFULL 0xFFFFFFF7FFFFFF81ULL1328#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_SHIFT 36U1329#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL1330#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_SHIFT 32U1331#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL1332#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_SHIFT 12U1333#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL1334#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_SHIFT 11U1335#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL1336#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_EN 0x0000000000000800ULL1337#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_SHIFT 7U1338#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL1339#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_SHIFT 0U1340#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL1341#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_EN 0x0000000000000001ULL1342 1343/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE */1344#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE 0x08A0U1345#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_MASKFULL 0x0000000000000001ULL1346#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_SHIFT 0U1347#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU1348#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_EN 0x00000001U1349 1350/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS */1351#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS 0x08A8U1352#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_MASKFULL 0x0000000000000001ULL1353#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_SHIFT 0U1354#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_CLRMSK 0xFFFFFFFEU1355#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN 0x00000001U1356 1357/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR */1358#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR 0x08B0U1359#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_MASKFULL 0x0000000000000001ULL1360#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_SHIFT 0U1361#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU1362#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN 0x00000001U1363 1364/* Register ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE */1365#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE 0x08B8U1366#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_MASKFULL 0x0000000000000001ULL1367#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_SHIFT 0U1368#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU1369#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_EN 0x00000001U1370 1371/* Register ROGUE_CR_MIPS_WRAPPER_NMI_EVENT */1372#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT 0x08C0U1373#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL1374#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_SHIFT 0U1375#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_CLRMSK 0xFFFFFFFEU1376#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_EN 0x00000001U1377 1378/* Register ROGUE_CR_MIPS_DEBUG_CONFIG */1379#define ROGUE_CR_MIPS_DEBUG_CONFIG 0x08C8U1380#define ROGUE_CR_MIPS_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL1381#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_SHIFT 0U1382#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_CLRMSK 0xFFFFFFFEU1383#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_EN 0x00000001U1384 1385/* Register ROGUE_CR_MIPS_EXCEPTION_STATUS */1386#define ROGUE_CR_MIPS_EXCEPTION_STATUS 0x08D0U1387#define ROGUE_CR_MIPS_EXCEPTION_STATUS_MASKFULL 0x000000000000003FULL1388#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_SHIFT 5U1389#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_CLRMSK 0xFFFFFFDFU1390#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_EN 0x00000020U1391#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_SHIFT 4U1392#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_CLRMSK 0xFFFFFFEFU1393#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_EN 0x00000010U1394#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_SHIFT 3U1395#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_CLRMSK 0xFFFFFFF7U1396#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_EN 0x00000008U1397#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_SHIFT 2U1398#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_CLRMSK 0xFFFFFFFBU1399#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_EN 0x00000004U1400#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_SHIFT 1U1401#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_CLRMSK 0xFFFFFFFDU1402#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_EN 0x00000002U1403#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_SHIFT 0U1404#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_CLRMSK 0xFFFFFFFEU1405#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_EN 0x00000001U1406 1407/* Register ROGUE_CR_MIPS_WRAPPER_STATUS */1408#define ROGUE_CR_MIPS_WRAPPER_STATUS 0x08E8U1409#define ROGUE_CR_MIPS_WRAPPER_STATUS_MASKFULL 0x00000000000000FFULL1410#define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_SHIFT 0U1411#define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_CLRMSK 0xFFFFFF00U1412 1413/* Register ROGUE_CR_XPU_BROADCAST */1414#define ROGUE_CR_XPU_BROADCAST 0x0890U1415#define ROGUE_CR_XPU_BROADCAST_MASKFULL 0x00000000000001FFULL1416#define ROGUE_CR_XPU_BROADCAST_MASK_SHIFT 0U1417#define ROGUE_CR_XPU_BROADCAST_MASK_CLRMSK 0xFFFFFE00U1418 1419/* Register ROGUE_CR_META_SP_MSLVDATAX */1420#define ROGUE_CR_META_SP_MSLVDATAX 0x0A00U1421#define ROGUE_CR_META_SP_MSLVDATAX_MASKFULL 0x00000000FFFFFFFFULL1422#define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT 0U1423#define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_CLRMSK 0x00000000U1424 1425/* Register ROGUE_CR_META_SP_MSLVDATAT */1426#define ROGUE_CR_META_SP_MSLVDATAT 0x0A08U1427#define ROGUE_CR_META_SP_MSLVDATAT_MASKFULL 0x00000000FFFFFFFFULL1428#define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT 0U1429#define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_CLRMSK 0x00000000U1430 1431/* Register ROGUE_CR_META_SP_MSLVCTRL0 */1432#define ROGUE_CR_META_SP_MSLVCTRL0 0x0A10U1433#define ROGUE_CR_META_SP_MSLVCTRL0_MASKFULL 0x00000000FFFFFFFFULL1434#define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_SHIFT 2U1435#define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_CLRMSK 0x00000003U1436#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT 1U1437#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_CLRMSK 0xFFFFFFFDU1438#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_EN 0x00000002U1439#define ROGUE_CR_META_SP_MSLVCTRL0_RD_SHIFT 0U1440#define ROGUE_CR_META_SP_MSLVCTRL0_RD_CLRMSK 0xFFFFFFFEU1441#define ROGUE_CR_META_SP_MSLVCTRL0_RD_EN 0x00000001U1442 1443/* Register ROGUE_CR_META_SP_MSLVCTRL1 */1444#define ROGUE_CR_META_SP_MSLVCTRL1 0x0A18U1445#define ROGUE_CR_META_SP_MSLVCTRL1_MASKFULL 0x00000000F7F4003FULL1446#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT 30U1447#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_CLRMSK 0x3FFFFFFFU1448#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT 29U1449#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_CLRMSK 0xDFFFFFFFU1450#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_EN 0x20000000U1451#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT 28U1452#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_CLRMSK 0xEFFFFFFFU1453#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_EN 0x10000000U1454#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT 26U1455#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_CLRMSK 0xFBFFFFFFU1456#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN 0x04000000U1457#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT 25U1458#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_CLRMSK 0xFDFFFFFFU1459#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_EN 0x02000000U1460#define ROGUE_CR_META_SP_MSLVCTRL1_READY_SHIFT 24U1461#define ROGUE_CR_META_SP_MSLVCTRL1_READY_CLRMSK 0xFEFFFFFFU1462#define ROGUE_CR_META_SP_MSLVCTRL1_READY_EN 0x01000000U1463#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT 21U1464#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_CLRMSK 0xFF1FFFFFU1465#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT 20U1466#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_CLRMSK 0xFFEFFFFFU1467#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_EN 0x00100000U1468#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT 18U1469#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_CLRMSK 0xFFFBFFFFU1470#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_EN 0x00040000U1471#define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_SHIFT 4U1472#define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_CLRMSK 0xFFFFFFCFU1473#define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT 2U1474#define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_CLRMSK 0xFFFFFFF3U1475#define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT 0U1476#define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_CLRMSK 0xFFFFFFFCU1477 1478/* Register ROGUE_CR_META_SP_MSLVHANDSHKE */1479#define ROGUE_CR_META_SP_MSLVHANDSHKE 0x0A50U1480#define ROGUE_CR_META_SP_MSLVHANDSHKE_MASKFULL 0x000000000000000FULL1481#define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT 2U1482#define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_CLRMSK 0xFFFFFFF3U1483#define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT 0U1484#define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_CLRMSK 0xFFFFFFFCU1485 1486/* Register ROGUE_CR_META_SP_MSLVT0KICK */1487#define ROGUE_CR_META_SP_MSLVT0KICK 0x0A80U1488#define ROGUE_CR_META_SP_MSLVT0KICK_MASKFULL 0x000000000000FFFFULL1489#define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT 0U1490#define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_CLRMSK 0xFFFF0000U1491 1492/* Register ROGUE_CR_META_SP_MSLVT0KICKI */1493#define ROGUE_CR_META_SP_MSLVT0KICKI 0x0A88U1494#define ROGUE_CR_META_SP_MSLVT0KICKI_MASKFULL 0x000000000000FFFFULL1495#define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT 0U1496#define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_CLRMSK 0xFFFF0000U1497 1498/* Register ROGUE_CR_META_SP_MSLVT1KICK */1499#define ROGUE_CR_META_SP_MSLVT1KICK 0x0A90U1500#define ROGUE_CR_META_SP_MSLVT1KICK_MASKFULL 0x000000000000FFFFULL1501#define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT 0U1502#define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_CLRMSK 0xFFFF0000U1503 1504/* Register ROGUE_CR_META_SP_MSLVT1KICKI */1505#define ROGUE_CR_META_SP_MSLVT1KICKI 0x0A98U1506#define ROGUE_CR_META_SP_MSLVT1KICKI_MASKFULL 0x000000000000FFFFULL1507#define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT 0U1508#define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_CLRMSK 0xFFFF0000U1509 1510/* Register ROGUE_CR_META_SP_MSLVT2KICK */1511#define ROGUE_CR_META_SP_MSLVT2KICK 0x0AA0U1512#define ROGUE_CR_META_SP_MSLVT2KICK_MASKFULL 0x000000000000FFFFULL1513#define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT 0U1514#define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_CLRMSK 0xFFFF0000U1515 1516/* Register ROGUE_CR_META_SP_MSLVT2KICKI */1517#define ROGUE_CR_META_SP_MSLVT2KICKI 0x0AA8U1518#define ROGUE_CR_META_SP_MSLVT2KICKI_MASKFULL 0x000000000000FFFFULL1519#define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT 0U1520#define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_CLRMSK 0xFFFF0000U1521 1522/* Register ROGUE_CR_META_SP_MSLVT3KICK */1523#define ROGUE_CR_META_SP_MSLVT3KICK 0x0AB0U1524#define ROGUE_CR_META_SP_MSLVT3KICK_MASKFULL 0x000000000000FFFFULL1525#define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT 0U1526#define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_CLRMSK 0xFFFF0000U1527 1528/* Register ROGUE_CR_META_SP_MSLVT3KICKI */1529#define ROGUE_CR_META_SP_MSLVT3KICKI 0x0AB8U1530#define ROGUE_CR_META_SP_MSLVT3KICKI_MASKFULL 0x000000000000FFFFULL1531#define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT 0U1532#define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_CLRMSK 0xFFFF0000U1533 1534/* Register ROGUE_CR_META_SP_MSLVRST */1535#define ROGUE_CR_META_SP_MSLVRST 0x0AC0U1536#define ROGUE_CR_META_SP_MSLVRST_MASKFULL 0x0000000000000001ULL1537#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_SHIFT 0U1538#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_CLRMSK 0xFFFFFFFEU1539#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_EN 0x00000001U1540 1541/* Register ROGUE_CR_META_SP_MSLVIRQSTATUS */1542#define ROGUE_CR_META_SP_MSLVIRQSTATUS 0x0AC8U1543#define ROGUE_CR_META_SP_MSLVIRQSTATUS_MASKFULL 0x000000000000000CULL1544#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT 3U1545#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_CLRMSK 0xFFFFFFF7U1546#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_EN 0x00000008U1547#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT 2U1548#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK 0xFFFFFFFBU1549#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN 0x00000004U1550 1551/* Register ROGUE_CR_META_SP_MSLVIRQENABLE */1552#define ROGUE_CR_META_SP_MSLVIRQENABLE 0x0AD0U1553#define ROGUE_CR_META_SP_MSLVIRQENABLE_MASKFULL 0x000000000000000CULL1554#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT 3U1555#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_CLRMSK 0xFFFFFFF7U1556#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_EN 0x00000008U1557#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT 2U1558#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_CLRMSK 0xFFFFFFFBU1559#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_EN 0x00000004U1560 1561/* Register ROGUE_CR_META_SP_MSLVIRQLEVEL */1562#define ROGUE_CR_META_SP_MSLVIRQLEVEL 0x0AD8U1563#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MASKFULL 0x0000000000000001ULL1564#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT 0U1565#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_CLRMSK 0xFFFFFFFEU1566#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_EN 0x00000001U1567 1568/* Register ROGUE_CR_MTS_SCHEDULE */1569#define ROGUE_CR_MTS_SCHEDULE 0x0B00U1570#define ROGUE_CR_MTS_SCHEDULE_MASKFULL 0x00000000000001FFULL1571#define ROGUE_CR_MTS_SCHEDULE_HOST_SHIFT 8U1572#define ROGUE_CR_MTS_SCHEDULE_HOST_CLRMSK 0xFFFFFEFFU1573#define ROGUE_CR_MTS_SCHEDULE_HOST_BG_TIMER 0x00000000U1574#define ROGUE_CR_MTS_SCHEDULE_HOST_HOST 0x00000100U1575#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_SHIFT 6U1576#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_CLRMSK 0xFFFFFF3FU1577#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT0 0x00000000U1578#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT1 0x00000040U1579#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT2 0x00000080U1580#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT3 0x000000C0U1581#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_SHIFT 5U1582#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_CLRMSK 0xFFFFFFDFU1583#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_BGCTX 0x00000000U1584#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_INTCTX 0x00000020U1585#define ROGUE_CR_MTS_SCHEDULE_TASK_SHIFT 4U1586#define ROGUE_CR_MTS_SCHEDULE_TASK_CLRMSK 0xFFFFFFEFU1587#define ROGUE_CR_MTS_SCHEDULE_TASK_NON_COUNTED 0x00000000U1588#define ROGUE_CR_MTS_SCHEDULE_TASK_COUNTED 0x00000010U1589#define ROGUE_CR_MTS_SCHEDULE_DM_SHIFT 0U1590#define ROGUE_CR_MTS_SCHEDULE_DM_CLRMSK 0xFFFFFFF0U1591#define ROGUE_CR_MTS_SCHEDULE_DM_DM0 0x00000000U1592#define ROGUE_CR_MTS_SCHEDULE_DM_DM1 0x00000001U1593#define ROGUE_CR_MTS_SCHEDULE_DM_DM2 0x00000002U1594#define ROGUE_CR_MTS_SCHEDULE_DM_DM3 0x00000003U1595#define ROGUE_CR_MTS_SCHEDULE_DM_DM4 0x00000004U1596#define ROGUE_CR_MTS_SCHEDULE_DM_DM5 0x00000005U1597#define ROGUE_CR_MTS_SCHEDULE_DM_DM6 0x00000006U1598#define ROGUE_CR_MTS_SCHEDULE_DM_DM7 0x00000007U1599#define ROGUE_CR_MTS_SCHEDULE_DM_DM_ALL 0x0000000FU1600 1601/* Register ROGUE_CR_MTS_SCHEDULE1 */1602#define ROGUE_CR_MTS_SCHEDULE1 0x10B00U1603#define ROGUE_CR_MTS_SCHEDULE1_MASKFULL 0x00000000000001FFULL1604#define ROGUE_CR_MTS_SCHEDULE1_HOST_SHIFT 8U1605#define ROGUE_CR_MTS_SCHEDULE1_HOST_CLRMSK 0xFFFFFEFFU1606#define ROGUE_CR_MTS_SCHEDULE1_HOST_BG_TIMER 0x00000000U1607#define ROGUE_CR_MTS_SCHEDULE1_HOST_HOST 0x00000100U1608#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_SHIFT 6U1609#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_CLRMSK 0xFFFFFF3FU1610#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT0 0x00000000U1611#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT1 0x00000040U1612#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT2 0x00000080U1613#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT3 0x000000C0U1614#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_SHIFT 5U1615#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_CLRMSK 0xFFFFFFDFU1616#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_BGCTX 0x00000000U1617#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_INTCTX 0x00000020U1618#define ROGUE_CR_MTS_SCHEDULE1_TASK_SHIFT 4U1619#define ROGUE_CR_MTS_SCHEDULE1_TASK_CLRMSK 0xFFFFFFEFU1620#define ROGUE_CR_MTS_SCHEDULE1_TASK_NON_COUNTED 0x00000000U1621#define ROGUE_CR_MTS_SCHEDULE1_TASK_COUNTED 0x00000010U1622#define ROGUE_CR_MTS_SCHEDULE1_DM_SHIFT 0U1623#define ROGUE_CR_MTS_SCHEDULE1_DM_CLRMSK 0xFFFFFFF0U1624#define ROGUE_CR_MTS_SCHEDULE1_DM_DM0 0x00000000U1625#define ROGUE_CR_MTS_SCHEDULE1_DM_DM1 0x00000001U1626#define ROGUE_CR_MTS_SCHEDULE1_DM_DM2 0x00000002U1627#define ROGUE_CR_MTS_SCHEDULE1_DM_DM3 0x00000003U1628#define ROGUE_CR_MTS_SCHEDULE1_DM_DM4 0x00000004U1629#define ROGUE_CR_MTS_SCHEDULE1_DM_DM5 0x00000005U1630#define ROGUE_CR_MTS_SCHEDULE1_DM_DM6 0x00000006U1631#define ROGUE_CR_MTS_SCHEDULE1_DM_DM7 0x00000007U1632#define ROGUE_CR_MTS_SCHEDULE1_DM_DM_ALL 0x0000000FU1633 1634/* Register ROGUE_CR_MTS_SCHEDULE2 */1635#define ROGUE_CR_MTS_SCHEDULE2 0x20B00U1636#define ROGUE_CR_MTS_SCHEDULE2_MASKFULL 0x00000000000001FFULL1637#define ROGUE_CR_MTS_SCHEDULE2_HOST_SHIFT 8U1638#define ROGUE_CR_MTS_SCHEDULE2_HOST_CLRMSK 0xFFFFFEFFU1639#define ROGUE_CR_MTS_SCHEDULE2_HOST_BG_TIMER 0x00000000U1640#define ROGUE_CR_MTS_SCHEDULE2_HOST_HOST 0x00000100U1641#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_SHIFT 6U1642#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_CLRMSK 0xFFFFFF3FU1643#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT0 0x00000000U1644#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT1 0x00000040U1645#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT2 0x00000080U1646#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT3 0x000000C0U1647#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_SHIFT 5U1648#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_CLRMSK 0xFFFFFFDFU1649#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_BGCTX 0x00000000U1650#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_INTCTX 0x00000020U1651#define ROGUE_CR_MTS_SCHEDULE2_TASK_SHIFT 4U1652#define ROGUE_CR_MTS_SCHEDULE2_TASK_CLRMSK 0xFFFFFFEFU1653#define ROGUE_CR_MTS_SCHEDULE2_TASK_NON_COUNTED 0x00000000U1654#define ROGUE_CR_MTS_SCHEDULE2_TASK_COUNTED 0x00000010U1655#define ROGUE_CR_MTS_SCHEDULE2_DM_SHIFT 0U1656#define ROGUE_CR_MTS_SCHEDULE2_DM_CLRMSK 0xFFFFFFF0U1657#define ROGUE_CR_MTS_SCHEDULE2_DM_DM0 0x00000000U1658#define ROGUE_CR_MTS_SCHEDULE2_DM_DM1 0x00000001U1659#define ROGUE_CR_MTS_SCHEDULE2_DM_DM2 0x00000002U1660#define ROGUE_CR_MTS_SCHEDULE2_DM_DM3 0x00000003U1661#define ROGUE_CR_MTS_SCHEDULE2_DM_DM4 0x00000004U1662#define ROGUE_CR_MTS_SCHEDULE2_DM_DM5 0x00000005U1663#define ROGUE_CR_MTS_SCHEDULE2_DM_DM6 0x00000006U1664#define ROGUE_CR_MTS_SCHEDULE2_DM_DM7 0x00000007U1665#define ROGUE_CR_MTS_SCHEDULE2_DM_DM_ALL 0x0000000FU1666 1667/* Register ROGUE_CR_MTS_SCHEDULE3 */1668#define ROGUE_CR_MTS_SCHEDULE3 0x30B00U1669#define ROGUE_CR_MTS_SCHEDULE3_MASKFULL 0x00000000000001FFULL1670#define ROGUE_CR_MTS_SCHEDULE3_HOST_SHIFT 8U1671#define ROGUE_CR_MTS_SCHEDULE3_HOST_CLRMSK 0xFFFFFEFFU1672#define ROGUE_CR_MTS_SCHEDULE3_HOST_BG_TIMER 0x00000000U1673#define ROGUE_CR_MTS_SCHEDULE3_HOST_HOST 0x00000100U1674#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_SHIFT 6U1675#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_CLRMSK 0xFFFFFF3FU1676#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT0 0x00000000U1677#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT1 0x00000040U1678#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT2 0x00000080U1679#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT3 0x000000C0U1680#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_SHIFT 5U1681#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_CLRMSK 0xFFFFFFDFU1682#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_BGCTX 0x00000000U1683#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_INTCTX 0x00000020U1684#define ROGUE_CR_MTS_SCHEDULE3_TASK_SHIFT 4U1685#define ROGUE_CR_MTS_SCHEDULE3_TASK_CLRMSK 0xFFFFFFEFU1686#define ROGUE_CR_MTS_SCHEDULE3_TASK_NON_COUNTED 0x00000000U1687#define ROGUE_CR_MTS_SCHEDULE3_TASK_COUNTED 0x00000010U1688#define ROGUE_CR_MTS_SCHEDULE3_DM_SHIFT 0U1689#define ROGUE_CR_MTS_SCHEDULE3_DM_CLRMSK 0xFFFFFFF0U1690#define ROGUE_CR_MTS_SCHEDULE3_DM_DM0 0x00000000U1691#define ROGUE_CR_MTS_SCHEDULE3_DM_DM1 0x00000001U1692#define ROGUE_CR_MTS_SCHEDULE3_DM_DM2 0x00000002U1693#define ROGUE_CR_MTS_SCHEDULE3_DM_DM3 0x00000003U1694#define ROGUE_CR_MTS_SCHEDULE3_DM_DM4 0x00000004U1695#define ROGUE_CR_MTS_SCHEDULE3_DM_DM5 0x00000005U1696#define ROGUE_CR_MTS_SCHEDULE3_DM_DM6 0x00000006U1697#define ROGUE_CR_MTS_SCHEDULE3_DM_DM7 0x00000007U1698#define ROGUE_CR_MTS_SCHEDULE3_DM_DM_ALL 0x0000000FU1699 1700/* Register ROGUE_CR_MTS_SCHEDULE4 */1701#define ROGUE_CR_MTS_SCHEDULE4 0x40B00U1702#define ROGUE_CR_MTS_SCHEDULE4_MASKFULL 0x00000000000001FFULL1703#define ROGUE_CR_MTS_SCHEDULE4_HOST_SHIFT 8U1704#define ROGUE_CR_MTS_SCHEDULE4_HOST_CLRMSK 0xFFFFFEFFU1705#define ROGUE_CR_MTS_SCHEDULE4_HOST_BG_TIMER 0x00000000U1706#define ROGUE_CR_MTS_SCHEDULE4_HOST_HOST 0x00000100U1707#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_SHIFT 6U1708#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_CLRMSK 0xFFFFFF3FU1709#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT0 0x00000000U1710#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT1 0x00000040U1711#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT2 0x00000080U1712#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT3 0x000000C0U1713#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_SHIFT 5U1714#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_CLRMSK 0xFFFFFFDFU1715#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_BGCTX 0x00000000U1716#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_INTCTX 0x00000020U1717#define ROGUE_CR_MTS_SCHEDULE4_TASK_SHIFT 4U1718#define ROGUE_CR_MTS_SCHEDULE4_TASK_CLRMSK 0xFFFFFFEFU1719#define ROGUE_CR_MTS_SCHEDULE4_TASK_NON_COUNTED 0x00000000U1720#define ROGUE_CR_MTS_SCHEDULE4_TASK_COUNTED 0x00000010U1721#define ROGUE_CR_MTS_SCHEDULE4_DM_SHIFT 0U1722#define ROGUE_CR_MTS_SCHEDULE4_DM_CLRMSK 0xFFFFFFF0U1723#define ROGUE_CR_MTS_SCHEDULE4_DM_DM0 0x00000000U1724#define ROGUE_CR_MTS_SCHEDULE4_DM_DM1 0x00000001U1725#define ROGUE_CR_MTS_SCHEDULE4_DM_DM2 0x00000002U1726#define ROGUE_CR_MTS_SCHEDULE4_DM_DM3 0x00000003U1727#define ROGUE_CR_MTS_SCHEDULE4_DM_DM4 0x00000004U1728#define ROGUE_CR_MTS_SCHEDULE4_DM_DM5 0x00000005U1729#define ROGUE_CR_MTS_SCHEDULE4_DM_DM6 0x00000006U1730#define ROGUE_CR_MTS_SCHEDULE4_DM_DM7 0x00000007U1731#define ROGUE_CR_MTS_SCHEDULE4_DM_DM_ALL 0x0000000FU1732 1733/* Register ROGUE_CR_MTS_SCHEDULE5 */1734#define ROGUE_CR_MTS_SCHEDULE5 0x50B00U1735#define ROGUE_CR_MTS_SCHEDULE5_MASKFULL 0x00000000000001FFULL1736#define ROGUE_CR_MTS_SCHEDULE5_HOST_SHIFT 8U1737#define ROGUE_CR_MTS_SCHEDULE5_HOST_CLRMSK 0xFFFFFEFFU1738#define ROGUE_CR_MTS_SCHEDULE5_HOST_BG_TIMER 0x00000000U1739#define ROGUE_CR_MTS_SCHEDULE5_HOST_HOST 0x00000100U1740#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_SHIFT 6U1741#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_CLRMSK 0xFFFFFF3FU1742#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT0 0x00000000U1743#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT1 0x00000040U1744#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT2 0x00000080U1745#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT3 0x000000C0U1746#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_SHIFT 5U1747#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_CLRMSK 0xFFFFFFDFU1748#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_BGCTX 0x00000000U1749#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_INTCTX 0x00000020U1750#define ROGUE_CR_MTS_SCHEDULE5_TASK_SHIFT 4U1751#define ROGUE_CR_MTS_SCHEDULE5_TASK_CLRMSK 0xFFFFFFEFU1752#define ROGUE_CR_MTS_SCHEDULE5_TASK_NON_COUNTED 0x00000000U1753#define ROGUE_CR_MTS_SCHEDULE5_TASK_COUNTED 0x00000010U1754#define ROGUE_CR_MTS_SCHEDULE5_DM_SHIFT 0U1755#define ROGUE_CR_MTS_SCHEDULE5_DM_CLRMSK 0xFFFFFFF0U1756#define ROGUE_CR_MTS_SCHEDULE5_DM_DM0 0x00000000U1757#define ROGUE_CR_MTS_SCHEDULE5_DM_DM1 0x00000001U1758#define ROGUE_CR_MTS_SCHEDULE5_DM_DM2 0x00000002U1759#define ROGUE_CR_MTS_SCHEDULE5_DM_DM3 0x00000003U1760#define ROGUE_CR_MTS_SCHEDULE5_DM_DM4 0x00000004U1761#define ROGUE_CR_MTS_SCHEDULE5_DM_DM5 0x00000005U1762#define ROGUE_CR_MTS_SCHEDULE5_DM_DM6 0x00000006U1763#define ROGUE_CR_MTS_SCHEDULE5_DM_DM7 0x00000007U1764#define ROGUE_CR_MTS_SCHEDULE5_DM_DM_ALL 0x0000000FU1765 1766/* Register ROGUE_CR_MTS_SCHEDULE6 */1767#define ROGUE_CR_MTS_SCHEDULE6 0x60B00U1768#define ROGUE_CR_MTS_SCHEDULE6_MASKFULL 0x00000000000001FFULL1769#define ROGUE_CR_MTS_SCHEDULE6_HOST_SHIFT 8U1770#define ROGUE_CR_MTS_SCHEDULE6_HOST_CLRMSK 0xFFFFFEFFU1771#define ROGUE_CR_MTS_SCHEDULE6_HOST_BG_TIMER 0x00000000U1772#define ROGUE_CR_MTS_SCHEDULE6_HOST_HOST 0x00000100U1773#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_SHIFT 6U1774#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_CLRMSK 0xFFFFFF3FU1775#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT0 0x00000000U1776#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT1 0x00000040U1777#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT2 0x00000080U1778#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT3 0x000000C0U1779#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_SHIFT 5U1780#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_CLRMSK 0xFFFFFFDFU1781#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_BGCTX 0x00000000U1782#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_INTCTX 0x00000020U1783#define ROGUE_CR_MTS_SCHEDULE6_TASK_SHIFT 4U1784#define ROGUE_CR_MTS_SCHEDULE6_TASK_CLRMSK 0xFFFFFFEFU1785#define ROGUE_CR_MTS_SCHEDULE6_TASK_NON_COUNTED 0x00000000U1786#define ROGUE_CR_MTS_SCHEDULE6_TASK_COUNTED 0x00000010U1787#define ROGUE_CR_MTS_SCHEDULE6_DM_SHIFT 0U1788#define ROGUE_CR_MTS_SCHEDULE6_DM_CLRMSK 0xFFFFFFF0U1789#define ROGUE_CR_MTS_SCHEDULE6_DM_DM0 0x00000000U1790#define ROGUE_CR_MTS_SCHEDULE6_DM_DM1 0x00000001U1791#define ROGUE_CR_MTS_SCHEDULE6_DM_DM2 0x00000002U1792#define ROGUE_CR_MTS_SCHEDULE6_DM_DM3 0x00000003U1793#define ROGUE_CR_MTS_SCHEDULE6_DM_DM4 0x00000004U1794#define ROGUE_CR_MTS_SCHEDULE6_DM_DM5 0x00000005U1795#define ROGUE_CR_MTS_SCHEDULE6_DM_DM6 0x00000006U1796#define ROGUE_CR_MTS_SCHEDULE6_DM_DM7 0x00000007U1797#define ROGUE_CR_MTS_SCHEDULE6_DM_DM_ALL 0x0000000FU1798 1799/* Register ROGUE_CR_MTS_SCHEDULE7 */1800#define ROGUE_CR_MTS_SCHEDULE7 0x70B00U1801#define ROGUE_CR_MTS_SCHEDULE7_MASKFULL 0x00000000000001FFULL1802#define ROGUE_CR_MTS_SCHEDULE7_HOST_SHIFT 8U1803#define ROGUE_CR_MTS_SCHEDULE7_HOST_CLRMSK 0xFFFFFEFFU1804#define ROGUE_CR_MTS_SCHEDULE7_HOST_BG_TIMER 0x00000000U1805#define ROGUE_CR_MTS_SCHEDULE7_HOST_HOST 0x00000100U1806#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_SHIFT 6U1807#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_CLRMSK 0xFFFFFF3FU1808#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT0 0x00000000U1809#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT1 0x00000040U1810#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT2 0x00000080U1811#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT3 0x000000C0U1812#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_SHIFT 5U1813#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_CLRMSK 0xFFFFFFDFU1814#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_BGCTX 0x00000000U1815#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_INTCTX 0x00000020U1816#define ROGUE_CR_MTS_SCHEDULE7_TASK_SHIFT 4U1817#define ROGUE_CR_MTS_SCHEDULE7_TASK_CLRMSK 0xFFFFFFEFU1818#define ROGUE_CR_MTS_SCHEDULE7_TASK_NON_COUNTED 0x00000000U1819#define ROGUE_CR_MTS_SCHEDULE7_TASK_COUNTED 0x00000010U1820#define ROGUE_CR_MTS_SCHEDULE7_DM_SHIFT 0U1821#define ROGUE_CR_MTS_SCHEDULE7_DM_CLRMSK 0xFFFFFFF0U1822#define ROGUE_CR_MTS_SCHEDULE7_DM_DM0 0x00000000U1823#define ROGUE_CR_MTS_SCHEDULE7_DM_DM1 0x00000001U1824#define ROGUE_CR_MTS_SCHEDULE7_DM_DM2 0x00000002U1825#define ROGUE_CR_MTS_SCHEDULE7_DM_DM3 0x00000003U1826#define ROGUE_CR_MTS_SCHEDULE7_DM_DM4 0x00000004U1827#define ROGUE_CR_MTS_SCHEDULE7_DM_DM5 0x00000005U1828#define ROGUE_CR_MTS_SCHEDULE7_DM_DM6 0x00000006U1829#define ROGUE_CR_MTS_SCHEDULE7_DM_DM7 0x00000007U1830#define ROGUE_CR_MTS_SCHEDULE7_DM_DM_ALL 0x0000000FU1831 1832/* Register ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC */1833#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC 0x0B30U1834#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL1835#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U1836#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U1837 1838/* Register ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC */1839#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC 0x0B38U1840#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL1841#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U1842#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U1843 1844/* Register ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC */1845#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC 0x0B40U1846#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL1847#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U1848#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U1849 1850/* Register ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC */1851#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC 0x0B48U1852#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL1853#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U1854#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U1855 1856/* Register ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG */1857#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG 0x0B50U1858#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__MASKFULL 0x000FF0FFFFFFF701ULL1859#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_MASKFULL 0x0000FFFFFFFFF001ULL1860#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT 44U1861#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK 0xFFFF0FFFFFFFFFFFULL1862#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_SHIFT 44U1863#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_CLRMSK 0xFFF00FFFFFFFFFFFULL1864#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT 40U1865#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_CLRMSK 0xFFFFF0FFFFFFFFFFULL1866#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_SHIFT 12U1867#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_CLRMSK 0xFFFFFF0000000FFFULL1868#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_SHIFT 9U1869#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_CLRMSK 0xFFFFFFFFFFFFF9FFULL1870#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT 8U1871#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_CLRMSK 0xFFFFFFFFFFFFFEFFULL1872#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_EN 0x0000000000000100ULL1873#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT 0U1874#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_CLRMSK 0xFFFFFFFFFFFFFFFEULL1875#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META 0x0000000000000000ULL1876#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_MTS 0x0000000000000001ULL1877 1878/* Register ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE */1879#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE 0x0B58U1880#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1881#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1882#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1883 1884/* Register ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE */1885#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE 0x0B60U1886#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1887#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1888#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1889 1890/* Register ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE */1891#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE 0x0B68U1892#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1893#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1894#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1895 1896/* Register ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE */1897#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE 0x0B70U1898#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1899#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1900#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1901 1902/* Register ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE */1903#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE 0x0B78U1904#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1905#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1906#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1907 1908/* Register ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE */1909#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE 0x0B80U1910#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL1911#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U1912#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U1913 1914/* Register ROGUE_CR_MTS_INTCTX */1915#define ROGUE_CR_MTS_INTCTX 0x0B98U1916#define ROGUE_CR_MTS_INTCTX_MASKFULL 0x000000003FFFFFFFULL1917#define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT 22U1918#define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_CLRMSK 0xC03FFFFFU1919#define ROGUE_CR_MTS_INTCTX_DM_PTR_SHIFT 18U1920#define ROGUE_CR_MTS_INTCTX_DM_PTR_CLRMSK 0xFFC3FFFFU1921#define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_SHIFT 16U1922#define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_CLRMSK 0xFFFCFFFFU1923#define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT 8U1924#define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_CLRMSK 0xFFFF00FFU1925#define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT 0U1926#define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_CLRMSK 0xFFFFFF00U1927 1928/* Register ROGUE_CR_MTS_BGCTX */1929#define ROGUE_CR_MTS_BGCTX 0x0BA0U1930#define ROGUE_CR_MTS_BGCTX_MASKFULL 0x0000000000003FFFULL1931#define ROGUE_CR_MTS_BGCTX_DM_PTR_SHIFT 10U1932#define ROGUE_CR_MTS_BGCTX_DM_PTR_CLRMSK 0xFFFFC3FFU1933#define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_SHIFT 8U1934#define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_CLRMSK 0xFFFFFCFFU1935#define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT 0U1936#define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_CLRMSK 0xFFFFFF00U1937 1938/* Register ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE */1939#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE 0x0BA8U1940#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_MASKFULL 0xFFFFFFFFFFFFFFFFULL1941#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT 56U1942#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_CLRMSK 0x00FFFFFFFFFFFFFFULL1943#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT 48U1944#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_CLRMSK 0xFF00FFFFFFFFFFFFULL1945#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT 40U1946#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_CLRMSK 0xFFFF00FFFFFFFFFFULL1947#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT 32U1948#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_CLRMSK 0xFFFFFF00FFFFFFFFULL1949#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT 24U1950#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_CLRMSK 0xFFFFFFFF00FFFFFFULL1951#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT 16U1952#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_CLRMSK 0xFFFFFFFFFF00FFFFULL1953#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT 8U1954#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_CLRMSK 0xFFFFFFFFFFFF00FFULL1955#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT 0U1956#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_CLRMSK 0xFFFFFFFFFFFFFF00ULL1957 1958/* Register ROGUE_CR_MTS_GPU_INT_STATUS */1959#define ROGUE_CR_MTS_GPU_INT_STATUS 0x0BB0U1960#define ROGUE_CR_MTS_GPU_INT_STATUS_MASKFULL 0x00000000FFFFFFFFULL1961#define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT 0U1962#define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_CLRMSK 0x00000000U1963 1964/* Register ROGUE_CR_MTS_SCHEDULE_ENABLE */1965#define ROGUE_CR_MTS_SCHEDULE_ENABLE 0x0BC8U1966#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASKFULL 0x00000000000000FFULL1967#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT 0U1968#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_CLRMSK 0xFFFFFF00U1969 1970/* Register ROGUE_CR_IRQ_OS0_EVENT_STATUS */1971#define ROGUE_CR_IRQ_OS0_EVENT_STATUS 0x0BD8U1972#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_MASKFULL 0x0000000000000001ULL1973#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT 0U1974#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU1975#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN 0x00000001U1976 1977/* Register ROGUE_CR_IRQ_OS0_EVENT_CLEAR */1978#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR 0x0BE8U1979#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL1980#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT 0U1981#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU1982#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN 0x00000001U1983 1984/* Register ROGUE_CR_IRQ_OS1_EVENT_STATUS */1985#define ROGUE_CR_IRQ_OS1_EVENT_STATUS 0x10BD8U1986#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_MASKFULL 0x0000000000000001ULL1987#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT 0U1988#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU1989#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_EN 0x00000001U1990 1991/* Register ROGUE_CR_IRQ_OS1_EVENT_CLEAR */1992#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR 0x10BE8U1993#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL1994#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT 0U1995#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU1996#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_EN 0x00000001U1997 1998/* Register ROGUE_CR_IRQ_OS2_EVENT_STATUS */1999#define ROGUE_CR_IRQ_OS2_EVENT_STATUS 0x20BD8U2000#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2001#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT 0U2002#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2003#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_EN 0x00000001U2004 2005/* Register ROGUE_CR_IRQ_OS2_EVENT_CLEAR */2006#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR 0x20BE8U2007#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2008#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT 0U2009#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2010#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_EN 0x00000001U2011 2012/* Register ROGUE_CR_IRQ_OS3_EVENT_STATUS */2013#define ROGUE_CR_IRQ_OS3_EVENT_STATUS 0x30BD8U2014#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2015#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT 0U2016#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2017#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_EN 0x00000001U2018 2019/* Register ROGUE_CR_IRQ_OS3_EVENT_CLEAR */2020#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR 0x30BE8U2021#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2022#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT 0U2023#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2024#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_EN 0x00000001U2025 2026/* Register ROGUE_CR_IRQ_OS4_EVENT_STATUS */2027#define ROGUE_CR_IRQ_OS4_EVENT_STATUS 0x40BD8U2028#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2029#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT 0U2030#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2031#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_EN 0x00000001U2032 2033/* Register ROGUE_CR_IRQ_OS4_EVENT_CLEAR */2034#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR 0x40BE8U2035#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2036#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT 0U2037#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2038#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_EN 0x00000001U2039 2040/* Register ROGUE_CR_IRQ_OS5_EVENT_STATUS */2041#define ROGUE_CR_IRQ_OS5_EVENT_STATUS 0x50BD8U2042#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2043#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT 0U2044#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2045#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_EN 0x00000001U2046 2047/* Register ROGUE_CR_IRQ_OS5_EVENT_CLEAR */2048#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR 0x50BE8U2049#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2050#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT 0U2051#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2052#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_EN 0x00000001U2053 2054/* Register ROGUE_CR_IRQ_OS6_EVENT_STATUS */2055#define ROGUE_CR_IRQ_OS6_EVENT_STATUS 0x60BD8U2056#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2057#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT 0U2058#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2059#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_EN 0x00000001U2060 2061/* Register ROGUE_CR_IRQ_OS6_EVENT_CLEAR */2062#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR 0x60BE8U2063#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2064#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT 0U2065#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2066#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_EN 0x00000001U2067 2068/* Register ROGUE_CR_IRQ_OS7_EVENT_STATUS */2069#define ROGUE_CR_IRQ_OS7_EVENT_STATUS 0x70BD8U2070#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_MASKFULL 0x0000000000000001ULL2071#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT 0U2072#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU2073#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_EN 0x00000001U2074 2075/* Register ROGUE_CR_IRQ_OS7_EVENT_CLEAR */2076#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR 0x70BE8U2077#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL2078#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT 0U2079#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU2080#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_EN 0x00000001U2081 2082/* Register ROGUE_CR_META_BOOT */2083#define ROGUE_CR_META_BOOT 0x0BF8U2084#define ROGUE_CR_META_BOOT_MASKFULL 0x0000000000000001ULL2085#define ROGUE_CR_META_BOOT_MODE_SHIFT 0U2086#define ROGUE_CR_META_BOOT_MODE_CLRMSK 0xFFFFFFFEU2087#define ROGUE_CR_META_BOOT_MODE_EN 0x00000001U2088 2089/* Register ROGUE_CR_GARTEN_SLC */2090#define ROGUE_CR_GARTEN_SLC 0x0BB8U2091#define ROGUE_CR_GARTEN_SLC_MASKFULL 0x0000000000000001ULL2092#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT 0U2093#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_CLRMSK 0xFFFFFFFEU2094#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_EN 0x00000001U2095 2096/* Register ROGUE_CR_PPP */2097#define ROGUE_CR_PPP 0x0CD0U2098#define ROGUE_CR_PPP_MASKFULL 0x00000000FFFFFFFFULL2099#define ROGUE_CR_PPP_CHECKSUM_SHIFT 0U2100#define ROGUE_CR_PPP_CHECKSUM_CLRMSK 0x00000000U2101 2102#define ROGUE_CR_ISP_RENDER_DIR_TYPE_MASK 0x00000003U2103/* Top-left to bottom-right */2104#define ROGUE_CR_ISP_RENDER_DIR_TYPE_TL2BR 0x00000000U2105/* Top-right to bottom-left */2106#define ROGUE_CR_ISP_RENDER_DIR_TYPE_TR2BL 0x00000001U2107/* Bottom-left to top-right */2108#define ROGUE_CR_ISP_RENDER_DIR_TYPE_BL2TR 0x00000002U2109/* Bottom-right to top-left */2110#define ROGUE_CR_ISP_RENDER_DIR_TYPE_BR2TL 0x00000003U2111 2112#define ROGUE_CR_ISP_RENDER_MODE_TYPE_MASK 0x00000003U2113/* Normal render */2114#define ROGUE_CR_ISP_RENDER_MODE_TYPE_NORM 0x00000000U2115/* Fast 2D render */2116#define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_2D 0x00000002U2117/* Fast scale render */2118#define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_SCALE 0x00000003U2119 2120/* Register ROGUE_CR_ISP_RENDER */2121#define ROGUE_CR_ISP_RENDER 0x0F08U2122#define ROGUE_CR_ISP_RENDER_MASKFULL 0x00000000000001FFULL2123#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_SHIFT 8U2124#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_CLRMSK 0xFFFFFEFFU2125#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_EN 0x00000100U2126#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT 7U2127#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_CLRMSK 0xFFFFFF7FU2128#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_EN 0x00000080U2129#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT 6U2130#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_CLRMSK 0xFFFFFFBFU2131#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_EN 0x00000040U2132#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_SHIFT 5U2133#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_CLRMSK 0xFFFFFFDFU2134#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_EN 0x00000020U2135#define ROGUE_CR_ISP_RENDER_RESUME_SHIFT 4U2136#define ROGUE_CR_ISP_RENDER_RESUME_CLRMSK 0xFFFFFFEFU2137#define ROGUE_CR_ISP_RENDER_RESUME_EN 0x00000010U2138#define ROGUE_CR_ISP_RENDER_DIR_SHIFT 2U2139#define ROGUE_CR_ISP_RENDER_DIR_CLRMSK 0xFFFFFFF3U2140#define ROGUE_CR_ISP_RENDER_DIR_TL2BR 0x00000000U2141#define ROGUE_CR_ISP_RENDER_DIR_TR2BL 0x00000004U2142#define ROGUE_CR_ISP_RENDER_DIR_BL2TR 0x00000008U2143#define ROGUE_CR_ISP_RENDER_DIR_BR2TL 0x0000000CU2144#define ROGUE_CR_ISP_RENDER_MODE_SHIFT 0U2145#define ROGUE_CR_ISP_RENDER_MODE_CLRMSK 0xFFFFFFFCU2146#define ROGUE_CR_ISP_RENDER_MODE_NORM 0x00000000U2147#define ROGUE_CR_ISP_RENDER_MODE_FAST_2D 0x00000002U2148#define ROGUE_CR_ISP_RENDER_MODE_FAST_SCALE 0x00000003U2149 2150/* Register ROGUE_CR_ISP_CTL */2151#define ROGUE_CR_ISP_CTL 0x0F38U2152#define ROGUE_CR_ISP_CTL_MASKFULL 0x00000000FFFFF3FFULL2153#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_SHIFT 31U2154#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_CLRMSK 0x7FFFFFFFU2155#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_EN 0x80000000U2156#define ROGUE_CR_ISP_CTL_LINE_STYLE_SHIFT 30U2157#define ROGUE_CR_ISP_CTL_LINE_STYLE_CLRMSK 0xBFFFFFFFU2158#define ROGUE_CR_ISP_CTL_LINE_STYLE_EN 0x40000000U2159#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_SHIFT 29U2160#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_CLRMSK 0xDFFFFFFFU2161#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_EN 0x20000000U2162#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_SHIFT 28U2163#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_CLRMSK 0xEFFFFFFFU2164#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_EN 0x10000000U2165#define ROGUE_CR_ISP_CTL_PAIR_TILES_SHIFT 27U2166#define ROGUE_CR_ISP_CTL_PAIR_TILES_CLRMSK 0xF7FFFFFFU2167#define ROGUE_CR_ISP_CTL_PAIR_TILES_EN 0x08000000U2168#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_SHIFT 26U2169#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_CLRMSK 0xFBFFFFFFU2170#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_EN 0x04000000U2171#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_SHIFT 25U2172#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_CLRMSK 0xFDFFFFFFU2173#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_EN 0x02000000U2174#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_SHIFT 23U2175#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_CLRMSK 0xFE7FFFFFU2176#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX9 0x00000000U2177#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX10 0x00800000U2178#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_OGL 0x01000000U2179#define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_SHIFT 21U2180#define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_CLRMSK 0xFF9FFFFFU2181#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_SHIFT 20U2182#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_CLRMSK 0xFFEFFFFFU2183#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_EN 0x00100000U2184#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT 19U2185#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_CLRMSK 0xFFF7FFFFU2186#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_EN 0x00080000U2187#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_SHIFT 18U2188#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_CLRMSK 0xFFFBFFFFU2189#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_EN 0x00040000U2190#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_SHIFT 17U2191#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_CLRMSK 0xFFFDFFFFU2192#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_EN 0x00020000U2193#define ROGUE_CR_ISP_CTL_SAMPLE_POS_SHIFT 16U2194#define ROGUE_CR_ISP_CTL_SAMPLE_POS_CLRMSK 0xFFFEFFFFU2195#define ROGUE_CR_ISP_CTL_SAMPLE_POS_EN 0x00010000U2196#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_SHIFT 12U2197#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_CLRMSK 0xFFFF0FFFU2198#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ONE 0x00000000U2199#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWO 0x00001000U2200#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THREE 0x00002000U2201#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOUR 0x00003000U2202#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIVE 0x00004000U2203#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIX 0x00005000U2204#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SEVEN 0x00006000U2205#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_EIGHT 0x00007000U2206#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_NINE 0x00008000U2207#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TEN 0x00009000U2208#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ELEVEN 0x0000A000U2209#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWELVE 0x0000B000U2210#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THIRTEEN 0x0000C000U2211#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOURTEEN 0x0000D000U2212#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIFTEEN 0x0000E000U2213#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIXTEEN 0x0000F000U2214#define ROGUE_CR_ISP_CTL_VALID_ID_SHIFT 4U2215#define ROGUE_CR_ISP_CTL_VALID_ID_CLRMSK 0xFFFFFC0FU2216#define ROGUE_CR_ISP_CTL_UPASS_START_SHIFT 0U2217#define ROGUE_CR_ISP_CTL_UPASS_START_CLRMSK 0xFFFFFFF0U2218 2219/* Register ROGUE_CR_ISP_STATUS */2220#define ROGUE_CR_ISP_STATUS 0x1038U2221#define ROGUE_CR_ISP_STATUS_MASKFULL 0x0000000000000007ULL2222#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_SHIFT 2U2223#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_CLRMSK 0xFFFFFFFBU2224#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_EN 0x00000004U2225#define ROGUE_CR_ISP_STATUS_ACTIVE_SHIFT 1U2226#define ROGUE_CR_ISP_STATUS_ACTIVE_CLRMSK 0xFFFFFFFDU2227#define ROGUE_CR_ISP_STATUS_ACTIVE_EN 0x00000002U2228#define ROGUE_CR_ISP_STATUS_EOR_SHIFT 0U2229#define ROGUE_CR_ISP_STATUS_EOR_CLRMSK 0xFFFFFFFEU2230#define ROGUE_CR_ISP_STATUS_EOR_EN 0x00000001U2231 2232/* Register group: ROGUE_CR_ISP_XTP_RESUME, with 64 repeats */2233#define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U2234/* Register ROGUE_CR_ISP_XTP_RESUME0 */2235#define ROGUE_CR_ISP_XTP_RESUME0 0x3A00U2236#define ROGUE_CR_ISP_XTP_RESUME0_MASKFULL 0x00000000003FF3FFULL2237#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U2238#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_CLRMSK 0xFFC00FFFU2239#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U2240#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_CLRMSK 0xFFFFFC00U2241 2242/* Register group: ROGUE_CR_ISP_XTP_STORE, with 32 repeats */2243#define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U2244/* Register ROGUE_CR_ISP_XTP_STORE0 */2245#define ROGUE_CR_ISP_XTP_STORE0 0x3C00U2246#define ROGUE_CR_ISP_XTP_STORE0_MASKFULL 0x000000007F3FF3FFULL2247#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U2248#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_CLRMSK 0xBFFFFFFFU2249#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_EN 0x40000000U2250#define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U2251#define ROGUE_CR_ISP_XTP_STORE0_EOR_CLRMSK 0xDFFFFFFFU2252#define ROGUE_CR_ISP_XTP_STORE0_EOR_EN 0x20000000U2253#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U2254#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_CLRMSK 0xEFFFFFFFU2255#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_EN 0x10000000U2256#define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U2257#define ROGUE_CR_ISP_XTP_STORE0_MT_CLRMSK 0xF0FFFFFFU2258#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U2259#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_CLRMSK 0xFFC00FFFU2260#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U2261#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_CLRMSK 0xFFFFFC00U2262 2263/* Register group: ROGUE_CR_BIF_CAT_BASE, with 8 repeats */2264#define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U2265/* Register ROGUE_CR_BIF_CAT_BASE0 */2266#define ROGUE_CR_BIF_CAT_BASE0 0x1200U2267#define ROGUE_CR_BIF_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL2268#define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U2269#define ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2270#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U2271#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U2272 2273/* Register ROGUE_CR_BIF_CAT_BASE1 */2274#define ROGUE_CR_BIF_CAT_BASE1 0x1208U2275#define ROGUE_CR_BIF_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL2276#define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U2277#define ROGUE_CR_BIF_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2278#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U2279#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U2280 2281/* Register ROGUE_CR_BIF_CAT_BASE2 */2282#define ROGUE_CR_BIF_CAT_BASE2 0x1210U2283#define ROGUE_CR_BIF_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL2284#define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U2285#define ROGUE_CR_BIF_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2286#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U2287#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U2288 2289/* Register ROGUE_CR_BIF_CAT_BASE3 */2290#define ROGUE_CR_BIF_CAT_BASE3 0x1218U2291#define ROGUE_CR_BIF_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL2292#define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U2293#define ROGUE_CR_BIF_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2294#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U2295#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U2296 2297/* Register ROGUE_CR_BIF_CAT_BASE4 */2298#define ROGUE_CR_BIF_CAT_BASE4 0x1220U2299#define ROGUE_CR_BIF_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL2300#define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U2301#define ROGUE_CR_BIF_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2302#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U2303#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U2304 2305/* Register ROGUE_CR_BIF_CAT_BASE5 */2306#define ROGUE_CR_BIF_CAT_BASE5 0x1228U2307#define ROGUE_CR_BIF_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL2308#define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U2309#define ROGUE_CR_BIF_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2310#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U2311#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U2312 2313/* Register ROGUE_CR_BIF_CAT_BASE6 */2314#define ROGUE_CR_BIF_CAT_BASE6 0x1230U2315#define ROGUE_CR_BIF_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL2316#define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U2317#define ROGUE_CR_BIF_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2318#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U2319#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U2320 2321/* Register ROGUE_CR_BIF_CAT_BASE7 */2322#define ROGUE_CR_BIF_CAT_BASE7 0x1238U2323#define ROGUE_CR_BIF_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL2324#define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U2325#define ROGUE_CR_BIF_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2326#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U2327#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U2328 2329/* Register ROGUE_CR_BIF_CAT_BASE_INDEX */2330#define ROGUE_CR_BIF_CAT_BASE_INDEX 0x1240U2331#define ROGUE_CR_BIF_CAT_BASE_INDEX_MASKFULL 0x00070707073F0707ULL2332#define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_SHIFT 48U2333#define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_CLRMSK 0xFFF8FFFFFFFFFFFFULL2334#define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_SHIFT 40U2335#define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_CLRMSK 0xFFFFF8FFFFFFFFFFULL2336#define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_SHIFT 32U2337#define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_CLRMSK 0xFFFFFFF8FFFFFFFFULL2338#define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_SHIFT 24U2339#define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_CLRMSK 0xFFFFFFFFF8FFFFFFULL2340#define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_SHIFT 19U2341#define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_CLRMSK 0xFFFFFFFFFFC7FFFFULL2342#define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_SHIFT 16U2343#define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_CLRMSK 0xFFFFFFFFFFF8FFFFULL2344#define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_SHIFT 8U2345#define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_CLRMSK 0xFFFFFFFFFFFFF8FFULL2346#define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_SHIFT 0U2347#define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_CLRMSK 0xFFFFFFFFFFFFFFF8ULL2348 2349/* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE0 */2350#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0 0x1248U2351#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_MASKFULL 0x0FFFFFFFFFFFF003ULL2352#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_SHIFT 40U2353#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2354#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_SHIFT 12U2355#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2356#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_SHIFT 1U2357#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2358#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_EN 0x0000000000000002ULL2359#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_SHIFT 0U2360#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2361#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_EN 0x0000000000000001ULL2362 2363/* Register ROGUE_CR_BIF_PM_CAT_BASE_TE0 */2364#define ROGUE_CR_BIF_PM_CAT_BASE_TE0 0x1250U2365#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_MASKFULL 0x0FFFFFFFFFFFF003ULL2366#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_SHIFT 40U2367#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2368#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_SHIFT 12U2369#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2370#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_SHIFT 1U2371#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2372#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_EN 0x0000000000000002ULL2373#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_SHIFT 0U2374#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2375#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_EN 0x0000000000000001ULL2376 2377/* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 */2378#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 0x1260U2379#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_MASKFULL 0x0FFFFFFFFFFFF003ULL2380#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT 40U2381#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2382#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_SHIFT 12U2383#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2384#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_SHIFT 1U2385#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2386#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_EN 0x0000000000000002ULL2387#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_SHIFT 0U2388#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2389#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_EN 0x0000000000000001ULL2390 2391/* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE1 */2392#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1 0x1268U2393#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_MASKFULL 0x0FFFFFFFFFFFF003ULL2394#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_SHIFT 40U2395#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2396#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_SHIFT 12U2397#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2398#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_SHIFT 1U2399#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2400#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_EN 0x0000000000000002ULL2401#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_SHIFT 0U2402#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2403#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_EN 0x0000000000000001ULL2404 2405/* Register ROGUE_CR_BIF_PM_CAT_BASE_TE1 */2406#define ROGUE_CR_BIF_PM_CAT_BASE_TE1 0x1270U2407#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_MASKFULL 0x0FFFFFFFFFFFF003ULL2408#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_SHIFT 40U2409#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2410#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_SHIFT 12U2411#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2412#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_SHIFT 1U2413#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2414#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_EN 0x0000000000000002ULL2415#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_SHIFT 0U2416#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2417#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_EN 0x0000000000000001ULL2418 2419/* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 */2420#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 0x1280U2421#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_MASKFULL 0x0FFFFFFFFFFFF003ULL2422#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT 40U2423#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL2424#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_SHIFT 12U2425#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL2426#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_SHIFT 1U2427#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL2428#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_EN 0x0000000000000002ULL2429#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_SHIFT 0U2430#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL2431#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_EN 0x0000000000000001ULL2432 2433/* Register ROGUE_CR_BIF_MMU_ENTRY_STATUS */2434#define ROGUE_CR_BIF_MMU_ENTRY_STATUS 0x1288U2435#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_MASKFULL 0x000000FFFFFFF0F3ULL2436#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_SHIFT 12U2437#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_CLRMSK 0xFFFFFF0000000FFFULL2438#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_SHIFT 4U2439#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_CLRMSK 0xFFFFFFFFFFFFFF0FULL2440#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_SHIFT 0U2441#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_CLRMSK 0xFFFFFFFFFFFFFFFCULL2442 2443/* Register ROGUE_CR_BIF_MMU_ENTRY */2444#define ROGUE_CR_BIF_MMU_ENTRY 0x1290U2445#define ROGUE_CR_BIF_MMU_ENTRY_MASKFULL 0x0000000000000003ULL2446#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_SHIFT 1U2447#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_CLRMSK 0xFFFFFFFDU2448#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_EN 0x00000002U2449#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_SHIFT 0U2450#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_CLRMSK 0xFFFFFFFEU2451#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_EN 0x00000001U2452 2453/* Register ROGUE_CR_BIF_CTRL_INVAL */2454#define ROGUE_CR_BIF_CTRL_INVAL 0x12A0U2455#define ROGUE_CR_BIF_CTRL_INVAL_MASKFULL 0x000000000000000FULL2456#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_SHIFT 3U2457#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_CLRMSK 0xFFFFFFF7U2458#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_EN 0x00000008U2459#define ROGUE_CR_BIF_CTRL_INVAL_PC_SHIFT 2U2460#define ROGUE_CR_BIF_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU2461#define ROGUE_CR_BIF_CTRL_INVAL_PC_EN 0x00000004U2462#define ROGUE_CR_BIF_CTRL_INVAL_PD_SHIFT 1U2463#define ROGUE_CR_BIF_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU2464#define ROGUE_CR_BIF_CTRL_INVAL_PD_EN 0x00000002U2465#define ROGUE_CR_BIF_CTRL_INVAL_PT_SHIFT 0U2466#define ROGUE_CR_BIF_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU2467#define ROGUE_CR_BIF_CTRL_INVAL_PT_EN 0x00000001U2468 2469/* Register ROGUE_CR_BIF_CTRL */2470#define ROGUE_CR_BIF_CTRL 0x12A8U2471#define ROGUE_CR_BIF_CTRL__XE_MEM__MASKFULL 0x000000000000033FULL2472#define ROGUE_CR_BIF_CTRL_MASKFULL 0x00000000000000FFULL2473#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_SHIFT 9U2474#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_CLRMSK 0xFFFFFDFFU2475#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_EN 0x00000200U2476#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_SHIFT 8U2477#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_CLRMSK 0xFFFFFEFFU2478#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_EN 0x00000100U2479#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_SHIFT 7U2480#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_CLRMSK 0xFFFFFF7FU2481#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_EN 0x00000080U2482#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_SHIFT 6U2483#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_CLRMSK 0xFFFFFFBFU2484#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_EN 0x00000040U2485#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_SHIFT 5U2486#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_CLRMSK 0xFFFFFFDFU2487#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_EN 0x00000020U2488#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_SHIFT 4U2489#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_CLRMSK 0xFFFFFFEFU2490#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_EN 0x00000010U2491#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_SHIFT 3U2492#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_CLRMSK 0xFFFFFFF7U2493#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_EN 0x00000008U2494#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_SHIFT 2U2495#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_CLRMSK 0xFFFFFFFBU2496#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_EN 0x00000004U2497#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_SHIFT 1U2498#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_CLRMSK 0xFFFFFFFDU2499#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_EN 0x00000002U2500#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_SHIFT 0U2501#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_CLRMSK 0xFFFFFFFEU2502#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_EN 0x00000001U2503 2504/* Register ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS */2505#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS 0x12B0U2506#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL2507#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U2508#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU2509#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U2510#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU2511#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U2512#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU2513#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U2514#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU2515#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U2516#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U2517#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU2518#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U2519#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U2520#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU2521#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U2522 2523/* Register ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS */2524#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS 0x12B8U2525#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__MASKFULL 0x001FFFFFFFFFFFF0ULL2526#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL2527#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_SHIFT 52U2528#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL2529#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_EN 0x0010000000000000ULL2530#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U2531#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL2532#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL2533#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_SHIFT 46U2534#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL2535#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U2536#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL2537#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U2538#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL2539#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_SHIFT 40U2540#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL2541#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U2542#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL2543#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U2544#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U2545 2546/* Register ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS */2547#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS 0x12C0U2548#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_MASKFULL 0x000000000000F775ULL2549#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_SHIFT 12U2550#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU2551#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_SHIFT 8U2552#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU2553#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_SHIFT 5U2554#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU2555#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_SHIFT 4U2556#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU2557#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_EN 0x00000010U2558#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U2559#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU2560#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U2561#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_SHIFT 0U2562#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU2563#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_EN 0x00000001U2564 2565/* Register ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS */2566#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS 0x12C8U2567#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL2568#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_SHIFT 50U2569#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL2570#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_EN 0x0004000000000000ULL2571#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_SHIFT 44U2572#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL2573#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_SHIFT 40U2574#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL2575#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_SHIFT 4U2576#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL2577#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U2578#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSIZE 16U2579 2580/* Register ROGUE_CR_BIF_MMU_STATUS */2581#define ROGUE_CR_BIF_MMU_STATUS 0x12D0U2582#define ROGUE_CR_BIF_MMU_STATUS__XE_MEM__MASKFULL 0x000000001FFFFFF7ULL2583#define ROGUE_CR_BIF_MMU_STATUS_MASKFULL 0x000000001FFFFFF7ULL2584#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_SHIFT 28U2585#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_CLRMSK 0xEFFFFFFFU2586#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_EN 0x10000000U2587#define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U2588#define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU2589#define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U2590#define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU2591#define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U2592#define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU2593#define ROGUE_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U2594#define ROGUE_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU2595#define ROGUE_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U2596#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U2597#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU2598#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U2599#define ROGUE_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U2600#define ROGUE_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU2601#define ROGUE_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U2602 2603/* Register group: ROGUE_CR_BIF_TILING_CFG, with 8 repeats */2604#define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U2605/* Register ROGUE_CR_BIF_TILING_CFG0 */2606#define ROGUE_CR_BIF_TILING_CFG0 0x12D8U2607#define ROGUE_CR_BIF_TILING_CFG0_MASKFULL 0xFFFFFFFF0FFFFFFFULL2608#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U2609#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2610#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U2611#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2612#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_EN 0x1000000000000000ULL2613#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U2614#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2615#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U2616#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U2617#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U2618#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2619#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U2620#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U2621 2622/* Register ROGUE_CR_BIF_TILING_CFG1 */2623#define ROGUE_CR_BIF_TILING_CFG1 0x12E0U2624#define ROGUE_CR_BIF_TILING_CFG1_MASKFULL 0xFFFFFFFF0FFFFFFFULL2625#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U2626#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2627#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U2628#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2629#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_EN 0x1000000000000000ULL2630#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U2631#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2632#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U2633#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U2634#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U2635#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2636#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U2637#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U2638 2639/* Register ROGUE_CR_BIF_TILING_CFG2 */2640#define ROGUE_CR_BIF_TILING_CFG2 0x12E8U2641#define ROGUE_CR_BIF_TILING_CFG2_MASKFULL 0xFFFFFFFF0FFFFFFFULL2642#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U2643#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2644#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U2645#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2646#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_EN 0x1000000000000000ULL2647#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U2648#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2649#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U2650#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U2651#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U2652#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2653#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U2654#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U2655 2656/* Register ROGUE_CR_BIF_TILING_CFG3 */2657#define ROGUE_CR_BIF_TILING_CFG3 0x12F0U2658#define ROGUE_CR_BIF_TILING_CFG3_MASKFULL 0xFFFFFFFF0FFFFFFFULL2659#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U2660#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2661#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U2662#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2663#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_EN 0x1000000000000000ULL2664#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U2665#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2666#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U2667#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U2668#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U2669#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2670#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U2671#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U2672 2673/* Register ROGUE_CR_BIF_TILING_CFG4 */2674#define ROGUE_CR_BIF_TILING_CFG4 0x12F8U2675#define ROGUE_CR_BIF_TILING_CFG4_MASKFULL 0xFFFFFFFF0FFFFFFFULL2676#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U2677#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2678#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U2679#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2680#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_EN 0x1000000000000000ULL2681#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U2682#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2683#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U2684#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U2685#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U2686#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2687#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U2688#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U2689 2690/* Register ROGUE_CR_BIF_TILING_CFG5 */2691#define ROGUE_CR_BIF_TILING_CFG5 0x1300U2692#define ROGUE_CR_BIF_TILING_CFG5_MASKFULL 0xFFFFFFFF0FFFFFFFULL2693#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U2694#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2695#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U2696#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2697#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_EN 0x1000000000000000ULL2698#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U2699#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2700#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U2701#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U2702#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U2703#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2704#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U2705#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U2706 2707/* Register ROGUE_CR_BIF_TILING_CFG6 */2708#define ROGUE_CR_BIF_TILING_CFG6 0x1308U2709#define ROGUE_CR_BIF_TILING_CFG6_MASKFULL 0xFFFFFFFF0FFFFFFFULL2710#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U2711#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2712#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U2713#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2714#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_EN 0x1000000000000000ULL2715#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U2716#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2717#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U2718#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U2719#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U2720#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2721#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U2722#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U2723 2724/* Register ROGUE_CR_BIF_TILING_CFG7 */2725#define ROGUE_CR_BIF_TILING_CFG7 0x1310U2726#define ROGUE_CR_BIF_TILING_CFG7_MASKFULL 0xFFFFFFFF0FFFFFFFULL2727#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U2728#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL2729#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U2730#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL2731#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_EN 0x1000000000000000ULL2732#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U2733#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL2734#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U2735#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U2736#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U2737#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL2738#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U2739#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U2740 2741/* Register ROGUE_CR_BIF_READS_EXT_STATUS */2742#define ROGUE_CR_BIF_READS_EXT_STATUS 0x1320U2743#define ROGUE_CR_BIF_READS_EXT_STATUS_MASKFULL 0x000000000FFFFFFFULL2744#define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_SHIFT 16U2745#define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_CLRMSK 0xF000FFFFU2746#define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_SHIFT 0U2747#define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_CLRMSK 0xFFFF0000U2748 2749/* Register ROGUE_CR_BIF_READS_INT_STATUS */2750#define ROGUE_CR_BIF_READS_INT_STATUS 0x1328U2751#define ROGUE_CR_BIF_READS_INT_STATUS_MASKFULL 0x0000000007FFFFFFULL2752#define ROGUE_CR_BIF_READS_INT_STATUS_MMU_SHIFT 16U2753#define ROGUE_CR_BIF_READS_INT_STATUS_MMU_CLRMSK 0xF800FFFFU2754#define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_SHIFT 0U2755#define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_CLRMSK 0xFFFF0000U2756 2757/* Register ROGUE_CR_BIFPM_READS_INT_STATUS */2758#define ROGUE_CR_BIFPM_READS_INT_STATUS 0x1330U2759#define ROGUE_CR_BIFPM_READS_INT_STATUS_MASKFULL 0x000000000000FFFFULL2760#define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_SHIFT 0U2761#define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_CLRMSK 0xFFFF0000U2762 2763/* Register ROGUE_CR_BIFPM_READS_EXT_STATUS */2764#define ROGUE_CR_BIFPM_READS_EXT_STATUS 0x1338U2765#define ROGUE_CR_BIFPM_READS_EXT_STATUS_MASKFULL 0x000000000000FFFFULL2766#define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_SHIFT 0U2767#define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_CLRMSK 0xFFFF0000U2768 2769/* Register ROGUE_CR_BIFPM_STATUS_MMU */2770#define ROGUE_CR_BIFPM_STATUS_MMU 0x1350U2771#define ROGUE_CR_BIFPM_STATUS_MMU_MASKFULL 0x00000000000000FFULL2772#define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_SHIFT 0U2773#define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U2774 2775/* Register ROGUE_CR_BIF_STATUS_MMU */2776#define ROGUE_CR_BIF_STATUS_MMU 0x1358U2777#define ROGUE_CR_BIF_STATUS_MMU_MASKFULL 0x00000000000000FFULL2778#define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_SHIFT 0U2779#define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U2780 2781/* Register ROGUE_CR_BIF_FAULT_READ */2782#define ROGUE_CR_BIF_FAULT_READ 0x13E0U2783#define ROGUE_CR_BIF_FAULT_READ_MASKFULL 0x000000FFFFFFFFF0ULL2784#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_SHIFT 4U2785#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_CLRMSK 0xFFFFFF000000000FULL2786#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSHIFT 4U2787#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSIZE 16U2788 2789/* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS */2790#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS 0x1430U2791#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL2792#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U2793#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU2794#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U2795#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU2796#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U2797#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU2798#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U2799#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU2800#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U2801#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U2802#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU2803#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U2804#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U2805#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU2806#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U2807 2808/* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS */2809#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS 0x1438U2810#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL2811#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U2812#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL2813#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL2814#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U2815#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL2816#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U2817#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL2818#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U2819#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL2820#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U2821#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U2822 2823/* Register ROGUE_CR_MCU_FENCE */2824#define ROGUE_CR_MCU_FENCE 0x1740U2825#define ROGUE_CR_MCU_FENCE_MASKFULL 0x000007FFFFFFFFE0ULL2826#define ROGUE_CR_MCU_FENCE_DM_SHIFT 40U2827#define ROGUE_CR_MCU_FENCE_DM_CLRMSK 0xFFFFF8FFFFFFFFFFULL2828#define ROGUE_CR_MCU_FENCE_DM_VERTEX 0x0000000000000000ULL2829#define ROGUE_CR_MCU_FENCE_DM_PIXEL 0x0000010000000000ULL2830#define ROGUE_CR_MCU_FENCE_DM_COMPUTE 0x0000020000000000ULL2831#define ROGUE_CR_MCU_FENCE_DM_RAY_VERTEX 0x0000030000000000ULL2832#define ROGUE_CR_MCU_FENCE_DM_RAY 0x0000040000000000ULL2833#define ROGUE_CR_MCU_FENCE_DM_FASTRENDER 0x0000050000000000ULL2834#define ROGUE_CR_MCU_FENCE_ADDR_SHIFT 5U2835#define ROGUE_CR_MCU_FENCE_ADDR_CLRMSK 0xFFFFFF000000001FULL2836#define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSHIFT 5U2837#define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U2838 2839/* Register group: ROGUE_CR_SCRATCH, with 16 repeats */2840#define ROGUE_CR_SCRATCH_REPEATCOUNT 16U2841/* Register ROGUE_CR_SCRATCH0 */2842#define ROGUE_CR_SCRATCH0 0x1A00U2843#define ROGUE_CR_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL2844#define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U2845#define ROGUE_CR_SCRATCH0_DATA_CLRMSK 0x00000000U2846 2847/* Register ROGUE_CR_SCRATCH1 */2848#define ROGUE_CR_SCRATCH1 0x1A08U2849#define ROGUE_CR_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL2850#define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U2851#define ROGUE_CR_SCRATCH1_DATA_CLRMSK 0x00000000U2852 2853/* Register ROGUE_CR_SCRATCH2 */2854#define ROGUE_CR_SCRATCH2 0x1A10U2855#define ROGUE_CR_SCRATCH2_MASKFULL 0x00000000FFFFFFFFULL2856#define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U2857#define ROGUE_CR_SCRATCH2_DATA_CLRMSK 0x00000000U2858 2859/* Register ROGUE_CR_SCRATCH3 */2860#define ROGUE_CR_SCRATCH3 0x1A18U2861#define ROGUE_CR_SCRATCH3_MASKFULL 0x00000000FFFFFFFFULL2862#define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U2863#define ROGUE_CR_SCRATCH3_DATA_CLRMSK 0x00000000U2864 2865/* Register ROGUE_CR_SCRATCH4 */2866#define ROGUE_CR_SCRATCH4 0x1A20U2867#define ROGUE_CR_SCRATCH4_MASKFULL 0x00000000FFFFFFFFULL2868#define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U2869#define ROGUE_CR_SCRATCH4_DATA_CLRMSK 0x00000000U2870 2871/* Register ROGUE_CR_SCRATCH5 */2872#define ROGUE_CR_SCRATCH5 0x1A28U2873#define ROGUE_CR_SCRATCH5_MASKFULL 0x00000000FFFFFFFFULL2874#define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U2875#define ROGUE_CR_SCRATCH5_DATA_CLRMSK 0x00000000U2876 2877/* Register ROGUE_CR_SCRATCH6 */2878#define ROGUE_CR_SCRATCH6 0x1A30U2879#define ROGUE_CR_SCRATCH6_MASKFULL 0x00000000FFFFFFFFULL2880#define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U2881#define ROGUE_CR_SCRATCH6_DATA_CLRMSK 0x00000000U2882 2883/* Register ROGUE_CR_SCRATCH7 */2884#define ROGUE_CR_SCRATCH7 0x1A38U2885#define ROGUE_CR_SCRATCH7_MASKFULL 0x00000000FFFFFFFFULL2886#define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U2887#define ROGUE_CR_SCRATCH7_DATA_CLRMSK 0x00000000U2888 2889/* Register ROGUE_CR_SCRATCH8 */2890#define ROGUE_CR_SCRATCH8 0x1A40U2891#define ROGUE_CR_SCRATCH8_MASKFULL 0x00000000FFFFFFFFULL2892#define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U2893#define ROGUE_CR_SCRATCH8_DATA_CLRMSK 0x00000000U2894 2895/* Register ROGUE_CR_SCRATCH9 */2896#define ROGUE_CR_SCRATCH9 0x1A48U2897#define ROGUE_CR_SCRATCH9_MASKFULL 0x00000000FFFFFFFFULL2898#define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U2899#define ROGUE_CR_SCRATCH9_DATA_CLRMSK 0x00000000U2900 2901/* Register ROGUE_CR_SCRATCH10 */2902#define ROGUE_CR_SCRATCH10 0x1A50U2903#define ROGUE_CR_SCRATCH10_MASKFULL 0x00000000FFFFFFFFULL2904#define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U2905#define ROGUE_CR_SCRATCH10_DATA_CLRMSK 0x00000000U2906 2907/* Register ROGUE_CR_SCRATCH11 */2908#define ROGUE_CR_SCRATCH11 0x1A58U2909#define ROGUE_CR_SCRATCH11_MASKFULL 0x00000000FFFFFFFFULL2910#define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U2911#define ROGUE_CR_SCRATCH11_DATA_CLRMSK 0x00000000U2912 2913/* Register ROGUE_CR_SCRATCH12 */2914#define ROGUE_CR_SCRATCH12 0x1A60U2915#define ROGUE_CR_SCRATCH12_MASKFULL 0x00000000FFFFFFFFULL2916#define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U2917#define ROGUE_CR_SCRATCH12_DATA_CLRMSK 0x00000000U2918 2919/* Register ROGUE_CR_SCRATCH13 */2920#define ROGUE_CR_SCRATCH13 0x1A68U2921#define ROGUE_CR_SCRATCH13_MASKFULL 0x00000000FFFFFFFFULL2922#define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U2923#define ROGUE_CR_SCRATCH13_DATA_CLRMSK 0x00000000U2924 2925/* Register ROGUE_CR_SCRATCH14 */2926#define ROGUE_CR_SCRATCH14 0x1A70U2927#define ROGUE_CR_SCRATCH14_MASKFULL 0x00000000FFFFFFFFULL2928#define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U2929#define ROGUE_CR_SCRATCH14_DATA_CLRMSK 0x00000000U2930 2931/* Register ROGUE_CR_SCRATCH15 */2932#define ROGUE_CR_SCRATCH15 0x1A78U2933#define ROGUE_CR_SCRATCH15_MASKFULL 0x00000000FFFFFFFFULL2934#define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U2935#define ROGUE_CR_SCRATCH15_DATA_CLRMSK 0x00000000U2936 2937/* Register group: ROGUE_CR_OS0_SCRATCH, with 2 repeats */2938#define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U2939/* Register ROGUE_CR_OS0_SCRATCH0 */2940#define ROGUE_CR_OS0_SCRATCH0 0x1A80U2941#define ROGUE_CR_OS0_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL2942#define ROGUE_CR_OS0_SCRATCH0_DATA_SHIFT 0U2943#define ROGUE_CR_OS0_SCRATCH0_DATA_CLRMSK 0x00000000U2944 2945/* Register ROGUE_CR_OS0_SCRATCH1 */2946#define ROGUE_CR_OS0_SCRATCH1 0x1A88U2947#define ROGUE_CR_OS0_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL2948#define ROGUE_CR_OS0_SCRATCH1_DATA_SHIFT 0U2949#define ROGUE_CR_OS0_SCRATCH1_DATA_CLRMSK 0x00000000U2950 2951/* Register ROGUE_CR_OS0_SCRATCH2 */2952#define ROGUE_CR_OS0_SCRATCH2 0x1A90U2953#define ROGUE_CR_OS0_SCRATCH2_MASKFULL 0x00000000000000FFULL2954#define ROGUE_CR_OS0_SCRATCH2_DATA_SHIFT 0U2955#define ROGUE_CR_OS0_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U2956 2957/* Register ROGUE_CR_OS0_SCRATCH3 */2958#define ROGUE_CR_OS0_SCRATCH3 0x1A98U2959#define ROGUE_CR_OS0_SCRATCH3_MASKFULL 0x00000000000000FFULL2960#define ROGUE_CR_OS0_SCRATCH3_DATA_SHIFT 0U2961#define ROGUE_CR_OS0_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U2962 2963/* Register group: ROGUE_CR_OS1_SCRATCH, with 2 repeats */2964#define ROGUE_CR_OS1_SCRATCH_REPEATCOUNT 2U2965/* Register ROGUE_CR_OS1_SCRATCH0 */2966#define ROGUE_CR_OS1_SCRATCH0 0x11A80U2967#define ROGUE_CR_OS1_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL2968#define ROGUE_CR_OS1_SCRATCH0_DATA_SHIFT 0U2969#define ROGUE_CR_OS1_SCRATCH0_DATA_CLRMSK 0x00000000U2970 2971/* Register ROGUE_CR_OS1_SCRATCH1 */2972#define ROGUE_CR_OS1_SCRATCH1 0x11A88U2973#define ROGUE_CR_OS1_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL2974#define ROGUE_CR_OS1_SCRATCH1_DATA_SHIFT 0U2975#define ROGUE_CR_OS1_SCRATCH1_DATA_CLRMSK 0x00000000U2976 2977/* Register ROGUE_CR_OS1_SCRATCH2 */2978#define ROGUE_CR_OS1_SCRATCH2 0x11A90U2979#define ROGUE_CR_OS1_SCRATCH2_MASKFULL 0x00000000000000FFULL2980#define ROGUE_CR_OS1_SCRATCH2_DATA_SHIFT 0U2981#define ROGUE_CR_OS1_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U2982 2983/* Register ROGUE_CR_OS1_SCRATCH3 */2984#define ROGUE_CR_OS1_SCRATCH3 0x11A98U2985#define ROGUE_CR_OS1_SCRATCH3_MASKFULL 0x00000000000000FFULL2986#define ROGUE_CR_OS1_SCRATCH3_DATA_SHIFT 0U2987#define ROGUE_CR_OS1_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U2988 2989/* Register group: ROGUE_CR_OS2_SCRATCH, with 2 repeats */2990#define ROGUE_CR_OS2_SCRATCH_REPEATCOUNT 2U2991/* Register ROGUE_CR_OS2_SCRATCH0 */2992#define ROGUE_CR_OS2_SCRATCH0 0x21A80U2993#define ROGUE_CR_OS2_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL2994#define ROGUE_CR_OS2_SCRATCH0_DATA_SHIFT 0U2995#define ROGUE_CR_OS2_SCRATCH0_DATA_CLRMSK 0x00000000U2996 2997/* Register ROGUE_CR_OS2_SCRATCH1 */2998#define ROGUE_CR_OS2_SCRATCH1 0x21A88U2999#define ROGUE_CR_OS2_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3000#define ROGUE_CR_OS2_SCRATCH1_DATA_SHIFT 0U3001#define ROGUE_CR_OS2_SCRATCH1_DATA_CLRMSK 0x00000000U3002 3003/* Register ROGUE_CR_OS2_SCRATCH2 */3004#define ROGUE_CR_OS2_SCRATCH2 0x21A90U3005#define ROGUE_CR_OS2_SCRATCH2_MASKFULL 0x00000000000000FFULL3006#define ROGUE_CR_OS2_SCRATCH2_DATA_SHIFT 0U3007#define ROGUE_CR_OS2_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3008 3009/* Register ROGUE_CR_OS2_SCRATCH3 */3010#define ROGUE_CR_OS2_SCRATCH3 0x21A98U3011#define ROGUE_CR_OS2_SCRATCH3_MASKFULL 0x00000000000000FFULL3012#define ROGUE_CR_OS2_SCRATCH3_DATA_SHIFT 0U3013#define ROGUE_CR_OS2_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3014 3015/* Register group: ROGUE_CR_OS3_SCRATCH, with 2 repeats */3016#define ROGUE_CR_OS3_SCRATCH_REPEATCOUNT 2U3017/* Register ROGUE_CR_OS3_SCRATCH0 */3018#define ROGUE_CR_OS3_SCRATCH0 0x31A80U3019#define ROGUE_CR_OS3_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL3020#define ROGUE_CR_OS3_SCRATCH0_DATA_SHIFT 0U3021#define ROGUE_CR_OS3_SCRATCH0_DATA_CLRMSK 0x00000000U3022 3023/* Register ROGUE_CR_OS3_SCRATCH1 */3024#define ROGUE_CR_OS3_SCRATCH1 0x31A88U3025#define ROGUE_CR_OS3_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3026#define ROGUE_CR_OS3_SCRATCH1_DATA_SHIFT 0U3027#define ROGUE_CR_OS3_SCRATCH1_DATA_CLRMSK 0x00000000U3028 3029/* Register ROGUE_CR_OS3_SCRATCH2 */3030#define ROGUE_CR_OS3_SCRATCH2 0x31A90U3031#define ROGUE_CR_OS3_SCRATCH2_MASKFULL 0x00000000000000FFULL3032#define ROGUE_CR_OS3_SCRATCH2_DATA_SHIFT 0U3033#define ROGUE_CR_OS3_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3034 3035/* Register ROGUE_CR_OS3_SCRATCH3 */3036#define ROGUE_CR_OS3_SCRATCH3 0x31A98U3037#define ROGUE_CR_OS3_SCRATCH3_MASKFULL 0x00000000000000FFULL3038#define ROGUE_CR_OS3_SCRATCH3_DATA_SHIFT 0U3039#define ROGUE_CR_OS3_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3040 3041/* Register group: ROGUE_CR_OS4_SCRATCH, with 2 repeats */3042#define ROGUE_CR_OS4_SCRATCH_REPEATCOUNT 2U3043/* Register ROGUE_CR_OS4_SCRATCH0 */3044#define ROGUE_CR_OS4_SCRATCH0 0x41A80U3045#define ROGUE_CR_OS4_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL3046#define ROGUE_CR_OS4_SCRATCH0_DATA_SHIFT 0U3047#define ROGUE_CR_OS4_SCRATCH0_DATA_CLRMSK 0x00000000U3048 3049/* Register ROGUE_CR_OS4_SCRATCH1 */3050#define ROGUE_CR_OS4_SCRATCH1 0x41A88U3051#define ROGUE_CR_OS4_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3052#define ROGUE_CR_OS4_SCRATCH1_DATA_SHIFT 0U3053#define ROGUE_CR_OS4_SCRATCH1_DATA_CLRMSK 0x00000000U3054 3055/* Register ROGUE_CR_OS4_SCRATCH2 */3056#define ROGUE_CR_OS4_SCRATCH2 0x41A90U3057#define ROGUE_CR_OS4_SCRATCH2_MASKFULL 0x00000000000000FFULL3058#define ROGUE_CR_OS4_SCRATCH2_DATA_SHIFT 0U3059#define ROGUE_CR_OS4_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3060 3061/* Register ROGUE_CR_OS4_SCRATCH3 */3062#define ROGUE_CR_OS4_SCRATCH3 0x41A98U3063#define ROGUE_CR_OS4_SCRATCH3_MASKFULL 0x00000000000000FFULL3064#define ROGUE_CR_OS4_SCRATCH3_DATA_SHIFT 0U3065#define ROGUE_CR_OS4_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3066 3067/* Register group: ROGUE_CR_OS5_SCRATCH, with 2 repeats */3068#define ROGUE_CR_OS5_SCRATCH_REPEATCOUNT 2U3069/* Register ROGUE_CR_OS5_SCRATCH0 */3070#define ROGUE_CR_OS5_SCRATCH0 0x51A80U3071#define ROGUE_CR_OS5_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL3072#define ROGUE_CR_OS5_SCRATCH0_DATA_SHIFT 0U3073#define ROGUE_CR_OS5_SCRATCH0_DATA_CLRMSK 0x00000000U3074 3075/* Register ROGUE_CR_OS5_SCRATCH1 */3076#define ROGUE_CR_OS5_SCRATCH1 0x51A88U3077#define ROGUE_CR_OS5_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3078#define ROGUE_CR_OS5_SCRATCH1_DATA_SHIFT 0U3079#define ROGUE_CR_OS5_SCRATCH1_DATA_CLRMSK 0x00000000U3080 3081/* Register ROGUE_CR_OS5_SCRATCH2 */3082#define ROGUE_CR_OS5_SCRATCH2 0x51A90U3083#define ROGUE_CR_OS5_SCRATCH2_MASKFULL 0x00000000000000FFULL3084#define ROGUE_CR_OS5_SCRATCH2_DATA_SHIFT 0U3085#define ROGUE_CR_OS5_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3086 3087/* Register ROGUE_CR_OS5_SCRATCH3 */3088#define ROGUE_CR_OS5_SCRATCH3 0x51A98U3089#define ROGUE_CR_OS5_SCRATCH3_MASKFULL 0x00000000000000FFULL3090#define ROGUE_CR_OS5_SCRATCH3_DATA_SHIFT 0U3091#define ROGUE_CR_OS5_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3092 3093/* Register group: ROGUE_CR_OS6_SCRATCH, with 2 repeats */3094#define ROGUE_CR_OS6_SCRATCH_REPEATCOUNT 2U3095/* Register ROGUE_CR_OS6_SCRATCH0 */3096#define ROGUE_CR_OS6_SCRATCH0 0x61A80U3097#define ROGUE_CR_OS6_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL3098#define ROGUE_CR_OS6_SCRATCH0_DATA_SHIFT 0U3099#define ROGUE_CR_OS6_SCRATCH0_DATA_CLRMSK 0x00000000U3100 3101/* Register ROGUE_CR_OS6_SCRATCH1 */3102#define ROGUE_CR_OS6_SCRATCH1 0x61A88U3103#define ROGUE_CR_OS6_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3104#define ROGUE_CR_OS6_SCRATCH1_DATA_SHIFT 0U3105#define ROGUE_CR_OS6_SCRATCH1_DATA_CLRMSK 0x00000000U3106 3107/* Register ROGUE_CR_OS6_SCRATCH2 */3108#define ROGUE_CR_OS6_SCRATCH2 0x61A90U3109#define ROGUE_CR_OS6_SCRATCH2_MASKFULL 0x00000000000000FFULL3110#define ROGUE_CR_OS6_SCRATCH2_DATA_SHIFT 0U3111#define ROGUE_CR_OS6_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3112 3113/* Register ROGUE_CR_OS6_SCRATCH3 */3114#define ROGUE_CR_OS6_SCRATCH3 0x61A98U3115#define ROGUE_CR_OS6_SCRATCH3_MASKFULL 0x00000000000000FFULL3116#define ROGUE_CR_OS6_SCRATCH3_DATA_SHIFT 0U3117#define ROGUE_CR_OS6_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3118 3119/* Register group: ROGUE_CR_OS7_SCRATCH, with 2 repeats */3120#define ROGUE_CR_OS7_SCRATCH_REPEATCOUNT 2U3121/* Register ROGUE_CR_OS7_SCRATCH0 */3122#define ROGUE_CR_OS7_SCRATCH0 0x71A80U3123#define ROGUE_CR_OS7_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL3124#define ROGUE_CR_OS7_SCRATCH0_DATA_SHIFT 0U3125#define ROGUE_CR_OS7_SCRATCH0_DATA_CLRMSK 0x00000000U3126 3127/* Register ROGUE_CR_OS7_SCRATCH1 */3128#define ROGUE_CR_OS7_SCRATCH1 0x71A88U3129#define ROGUE_CR_OS7_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL3130#define ROGUE_CR_OS7_SCRATCH1_DATA_SHIFT 0U3131#define ROGUE_CR_OS7_SCRATCH1_DATA_CLRMSK 0x00000000U3132 3133/* Register ROGUE_CR_OS7_SCRATCH2 */3134#define ROGUE_CR_OS7_SCRATCH2 0x71A90U3135#define ROGUE_CR_OS7_SCRATCH2_MASKFULL 0x00000000000000FFULL3136#define ROGUE_CR_OS7_SCRATCH2_DATA_SHIFT 0U3137#define ROGUE_CR_OS7_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U3138 3139/* Register ROGUE_CR_OS7_SCRATCH3 */3140#define ROGUE_CR_OS7_SCRATCH3 0x71A98U3141#define ROGUE_CR_OS7_SCRATCH3_MASKFULL 0x00000000000000FFULL3142#define ROGUE_CR_OS7_SCRATCH3_DATA_SHIFT 0U3143#define ROGUE_CR_OS7_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U3144 3145/* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR */3146#define ROGUE_CR_SPFILTER_SIGNAL_DESCR 0x2700U3147#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MASKFULL 0x000000000000FFFFULL3148#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_SHIFT 0U3149#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_CLRMSK 0xFFFF0000U3150#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSHIFT 4U3151#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSIZE 16U3152 3153/* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN */3154#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN 0x2708U3155#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_MASKFULL 0x000000FFFFFFFFF0ULL3156#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_SHIFT 4U3157#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_CLRMSK 0xFFFFFF000000000FULL3158#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSHIFT 4U3159#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U3160 3161/* Register group: ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats */3162#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U3163/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 */3164#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 0x3000U3165#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL 0x7FFFF7FFFFFFF000ULL3166#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U3167#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3168#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_EN 0x4000000000000000ULL3169#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U3170#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3171#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN 0x2000000000000000ULL3172#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U3173#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3174#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN 0x1000000000000000ULL3175#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U3176#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3177#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U3178#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3179#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U3180#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3181#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U3182#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U3183 3184/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 */3185#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 0x3008U3186#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL 0x7FFFF7FFFFFFF000ULL3187#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U3188#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3189#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_EN 0x4000000000000000ULL3190#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U3191#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3192#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN 0x2000000000000000ULL3193#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U3194#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3195#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN 0x1000000000000000ULL3196#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U3197#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3198#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U3199#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3200#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U3201#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3202#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U3203#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U3204 3205/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 */3206#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 0x3010U3207#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL 0x7FFFF7FFFFFFF000ULL3208#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U3209#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3210#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_EN 0x4000000000000000ULL3211#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U3212#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3213#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN 0x2000000000000000ULL3214#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U3215#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3216#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN 0x1000000000000000ULL3217#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U3218#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3219#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U3220#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3221#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U3222#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3223#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U3224#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U3225 3226/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 */3227#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 0x3018U3228#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL 0x7FFFF7FFFFFFF000ULL3229#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U3230#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3231#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_EN 0x4000000000000000ULL3232#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U3233#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3234#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN 0x2000000000000000ULL3235#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U3236#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3237#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN 0x1000000000000000ULL3238#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U3239#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3240#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U3241#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3242#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U3243#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3244#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U3245#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U3246 3247/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 */3248#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 0x3020U3249#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL 0x7FFFF7FFFFFFF000ULL3250#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U3251#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3252#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_EN 0x4000000000000000ULL3253#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U3254#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3255#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN 0x2000000000000000ULL3256#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U3257#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3258#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN 0x1000000000000000ULL3259#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U3260#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3261#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U3262#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3263#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U3264#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3265#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U3266#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U3267 3268/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 */3269#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 0x3028U3270#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL 0x7FFFF7FFFFFFF000ULL3271#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U3272#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3273#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_EN 0x4000000000000000ULL3274#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U3275#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3276#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN 0x2000000000000000ULL3277#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U3278#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3279#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN 0x1000000000000000ULL3280#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U3281#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3282#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U3283#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3284#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U3285#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3286#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U3287#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U3288 3289/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 */3290#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 0x3030U3291#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL 0x7FFFF7FFFFFFF000ULL3292#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U3293#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3294#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_EN 0x4000000000000000ULL3295#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U3296#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3297#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN 0x2000000000000000ULL3298#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U3299#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3300#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN 0x1000000000000000ULL3301#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U3302#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3303#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U3304#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3305#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U3306#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3307#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U3308#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U3309 3310/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 */3311#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 0x3038U3312#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL 0x7FFFF7FFFFFFF000ULL3313#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U3314#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3315#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_EN 0x4000000000000000ULL3316#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U3317#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3318#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN 0x2000000000000000ULL3319#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U3320#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3321#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN 0x1000000000000000ULL3322#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U3323#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3324#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U3325#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3326#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U3327#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3328#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U3329#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U3330 3331/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 */3332#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 0x3040U3333#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL 0x7FFFF7FFFFFFF000ULL3334#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U3335#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3336#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_EN 0x4000000000000000ULL3337#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U3338#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3339#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN 0x2000000000000000ULL3340#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U3341#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3342#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN 0x1000000000000000ULL3343#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U3344#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3345#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U3346#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3347#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U3348#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3349#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U3350#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U3351 3352/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 */3353#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 0x3048U3354#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL 0x7FFFF7FFFFFFF000ULL3355#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U3356#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3357#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_EN 0x4000000000000000ULL3358#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U3359#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3360#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN 0x2000000000000000ULL3361#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U3362#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3363#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN 0x1000000000000000ULL3364#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U3365#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3366#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U3367#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3368#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U3369#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3370#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U3371#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U3372 3373/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 */3374#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 0x3050U3375#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL 0x7FFFF7FFFFFFF000ULL3376#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U3377#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3378#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_EN 0x4000000000000000ULL3379#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U3380#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3381#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN 0x2000000000000000ULL3382#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U3383#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3384#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN 0x1000000000000000ULL3385#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U3386#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3387#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U3388#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3389#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U3390#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3391#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U3392#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U3393 3394/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 */3395#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 0x3058U3396#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL 0x7FFFF7FFFFFFF000ULL3397#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U3398#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3399#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_EN 0x4000000000000000ULL3400#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U3401#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3402#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN 0x2000000000000000ULL3403#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U3404#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3405#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN 0x1000000000000000ULL3406#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U3407#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3408#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U3409#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3410#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U3411#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3412#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U3413#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U3414 3415/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 */3416#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 0x3060U3417#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL 0x7FFFF7FFFFFFF000ULL3418#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U3419#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3420#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_EN 0x4000000000000000ULL3421#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U3422#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3423#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN 0x2000000000000000ULL3424#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U3425#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3426#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN 0x1000000000000000ULL3427#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U3428#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3429#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U3430#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3431#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U3432#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3433#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U3434#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U3435 3436/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 */3437#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 0x3068U3438#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL 0x7FFFF7FFFFFFF000ULL3439#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U3440#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3441#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_EN 0x4000000000000000ULL3442#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U3443#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3444#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN 0x2000000000000000ULL3445#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U3446#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3447#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN 0x1000000000000000ULL3448#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U3449#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3450#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U3451#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3452#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U3453#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3454#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U3455#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U3456 3457/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 */3458#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 0x3070U3459#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL 0x7FFFF7FFFFFFF000ULL3460#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U3461#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3462#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_EN 0x4000000000000000ULL3463#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U3464#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3465#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN 0x2000000000000000ULL3466#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U3467#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3468#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN 0x1000000000000000ULL3469#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U3470#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3471#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U3472#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3473#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U3474#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3475#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U3476#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U3477 3478/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 */3479#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 0x3078U3480#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL 0x7FFFF7FFFFFFF000ULL3481#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U3482#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL3483#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_EN 0x4000000000000000ULL3484#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U3485#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL3486#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN 0x2000000000000000ULL3487#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U3488#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL3489#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN 0x1000000000000000ULL3490#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U3491#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL3492#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U3493#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL3494#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U3495#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL3496#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U3497#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U3498 3499/* Register ROGUE_CR_FWCORE_BOOT */3500#define ROGUE_CR_FWCORE_BOOT 0x3090U3501#define ROGUE_CR_FWCORE_BOOT_MASKFULL 0x0000000000000001ULL3502#define ROGUE_CR_FWCORE_BOOT_ENABLE_SHIFT 0U3503#define ROGUE_CR_FWCORE_BOOT_ENABLE_CLRMSK 0xFFFFFFFEU3504#define ROGUE_CR_FWCORE_BOOT_ENABLE_EN 0x00000001U3505 3506/* Register ROGUE_CR_FWCORE_RESET_ADDR */3507#define ROGUE_CR_FWCORE_RESET_ADDR 0x3098U3508#define ROGUE_CR_FWCORE_RESET_ADDR_MASKFULL 0x00000000FFFFFFFEULL3509#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_SHIFT 1U3510#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_CLRMSK 0x00000001U3511#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSHIFT 1U3512#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSIZE 2U3513 3514/* Register ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR */3515#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR 0x30A0U3516#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_MASKFULL 0x00000000FFFFFFFEULL3517#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_SHIFT 1U3518#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_CLRMSK 0x00000001U3519#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSHIFT 1U3520#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSIZE 2U3521 3522/* Register ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT */3523#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT 0x30A8U3524#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL3525#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT 0U3526#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_CLRMSK 0xFFFFFFFEU3527#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_EN 0x00000001U3528 3529/* Register ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS */3530#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS 0x30B0U3531#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_MASKFULL 0x000000000000F771ULL3532#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_SHIFT 12U3533#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU3534#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_SHIFT 8U3535#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU3536#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_SHIFT 5U3537#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU3538#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_SHIFT 4U3539#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU3540#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_EN 0x00000010U3541#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_SHIFT 0U3542#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU3543#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_EN 0x00000001U3544 3545/* Register ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS */3546#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS 0x30B8U3547#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_MASKFULL 0x001FFFFFFFFFFFF0ULL3548#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_SHIFT 52U3549#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL3550#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_EN 0x0010000000000000ULL3551#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_SHIFT 46U3552#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL3553#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_SHIFT 40U3554#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL3555#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_SHIFT 4U3556#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL3557#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U3558#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSIZE 16U3559 3560/* Register ROGUE_CR_FWCORE_MEM_CTRL_INVAL */3561#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL 0x30C0U3562#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_MASKFULL 0x000000000000000FULL3563#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_SHIFT 3U3564#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_CLRMSK 0xFFFFFFF7U3565#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_EN 0x00000008U3566#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_SHIFT 2U3567#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU3568#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_EN 0x00000004U3569#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_SHIFT 1U3570#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU3571#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_EN 0x00000002U3572#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_SHIFT 0U3573#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU3574#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_EN 0x00000001U3575 3576/* Register ROGUE_CR_FWCORE_MEM_MMU_STATUS */3577#define ROGUE_CR_FWCORE_MEM_MMU_STATUS 0x30C8U3578#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL3579#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_SHIFT 20U3580#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU3581#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_SHIFT 12U3582#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU3583#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_SHIFT 4U3584#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU3585#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_SHIFT 2U3586#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU3587#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_EN 0x00000004U3588#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_SHIFT 1U3589#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU3590#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_EN 0x00000002U3591#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_SHIFT 0U3592#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU3593#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_EN 0x00000001U3594 3595/* Register ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS */3596#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS 0x30D8U3597#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MASKFULL 0x0000000000000FFFULL3598#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_SHIFT 0U3599#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_CLRMSK 0xFFFFF000U3600 3601/* Register ROGUE_CR_FWCORE_MEM_READS_INT_STATUS */3602#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS 0x30E0U3603#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MASKFULL 0x00000000000007FFULL3604#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_SHIFT 0U3605#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_CLRMSK 0xFFFFF800U3606 3607/* Register ROGUE_CR_FWCORE_WRAPPER_FENCE */3608#define ROGUE_CR_FWCORE_WRAPPER_FENCE 0x30E8U3609#define ROGUE_CR_FWCORE_WRAPPER_FENCE_MASKFULL 0x0000000000000001ULL3610#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_SHIFT 0U3611#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_CLRMSK 0xFFFFFFFEU3612#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_EN 0x00000001U3613 3614/* Register group: ROGUE_CR_FWCORE_MEM_CAT_BASE, with 8 repeats */3615#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U3616/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE0 */3617#define ROGUE_CR_FWCORE_MEM_CAT_BASE0 0x30F0U3618#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL3619#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U3620#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3621#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U3622#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U3623 3624/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE1 */3625#define ROGUE_CR_FWCORE_MEM_CAT_BASE1 0x30F8U3626#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL3627#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U3628#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3629#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U3630#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U3631 3632/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE2 */3633#define ROGUE_CR_FWCORE_MEM_CAT_BASE2 0x3100U3634#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL3635#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U3636#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3637#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U3638#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U3639 3640/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE3 */3641#define ROGUE_CR_FWCORE_MEM_CAT_BASE3 0x3108U3642#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL3643#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U3644#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3645#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U3646#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U3647 3648/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE4 */3649#define ROGUE_CR_FWCORE_MEM_CAT_BASE4 0x3110U3650#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL3651#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U3652#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3653#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U3654#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U3655 3656/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE5 */3657#define ROGUE_CR_FWCORE_MEM_CAT_BASE5 0x3118U3658#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL3659#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U3660#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3661#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U3662#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U3663 3664/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE6 */3665#define ROGUE_CR_FWCORE_MEM_CAT_BASE6 0x3120U3666#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL3667#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U3668#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3669#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U3670#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U3671 3672/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE7 */3673#define ROGUE_CR_FWCORE_MEM_CAT_BASE7 0x3128U3674#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL3675#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U3676#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL3677#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U3678#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U3679 3680/* Register ROGUE_CR_FWCORE_WDT_RESET */3681#define ROGUE_CR_FWCORE_WDT_RESET 0x3130U3682#define ROGUE_CR_FWCORE_WDT_RESET_MASKFULL 0x0000000000000001ULL3683#define ROGUE_CR_FWCORE_WDT_RESET_EN_SHIFT 0U3684#define ROGUE_CR_FWCORE_WDT_RESET_EN_CLRMSK 0xFFFFFFFEU3685#define ROGUE_CR_FWCORE_WDT_RESET_EN_EN 0x00000001U3686 3687/* Register ROGUE_CR_FWCORE_WDT_CTRL */3688#define ROGUE_CR_FWCORE_WDT_CTRL 0x3138U3689#define ROGUE_CR_FWCORE_WDT_CTRL_MASKFULL 0x00000000FFFF1F01ULL3690#define ROGUE_CR_FWCORE_WDT_CTRL_PROT_SHIFT 16U3691#define ROGUE_CR_FWCORE_WDT_CTRL_PROT_CLRMSK 0x0000FFFFU3692#define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT 8U3693#define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_CLRMSK 0xFFFFE0FFU3694#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT 0U3695#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU3696#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_EN 0x00000001U3697 3698/* Register ROGUE_CR_FWCORE_WDT_COUNT */3699#define ROGUE_CR_FWCORE_WDT_COUNT 0x3140U3700#define ROGUE_CR_FWCORE_WDT_COUNT_MASKFULL 0x00000000FFFFFFFFULL3701#define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_SHIFT 0U3702#define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK 0x00000000U3703 3704/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED0, with 4 repeats */3705#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U3706/* Register ROGUE_CR_FWCORE_DMI_RESERVED00 */3707#define ROGUE_CR_FWCORE_DMI_RESERVED00 0x3400U3708#define ROGUE_CR_FWCORE_DMI_RESERVED00_MASKFULL 0x0000000000000000ULL3709 3710/* Register ROGUE_CR_FWCORE_DMI_RESERVED01 */3711#define ROGUE_CR_FWCORE_DMI_RESERVED01 0x3408U3712#define ROGUE_CR_FWCORE_DMI_RESERVED01_MASKFULL 0x0000000000000000ULL3713 3714/* Register ROGUE_CR_FWCORE_DMI_RESERVED02 */3715#define ROGUE_CR_FWCORE_DMI_RESERVED02 0x3410U3716#define ROGUE_CR_FWCORE_DMI_RESERVED02_MASKFULL 0x0000000000000000ULL3717 3718/* Register ROGUE_CR_FWCORE_DMI_RESERVED03 */3719#define ROGUE_CR_FWCORE_DMI_RESERVED03 0x3418U3720#define ROGUE_CR_FWCORE_DMI_RESERVED03_MASKFULL 0x0000000000000000ULL3721 3722/* Register ROGUE_CR_FWCORE_DMI_DATA0 */3723#define ROGUE_CR_FWCORE_DMI_DATA0 0x3420U3724#define ROGUE_CR_FWCORE_DMI_DATA0_MASKFULL 0x0000000000000000ULL3725 3726/* Register ROGUE_CR_FWCORE_DMI_DATA1 */3727#define ROGUE_CR_FWCORE_DMI_DATA1 0x3428U3728#define ROGUE_CR_FWCORE_DMI_DATA1_MASKFULL 0x0000000000000000ULL3729 3730/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED1, with 5 repeats */3731#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U3732/* Register ROGUE_CR_FWCORE_DMI_RESERVED10 */3733#define ROGUE_CR_FWCORE_DMI_RESERVED10 0x3430U3734#define ROGUE_CR_FWCORE_DMI_RESERVED10_MASKFULL 0x0000000000000000ULL3735 3736/* Register ROGUE_CR_FWCORE_DMI_RESERVED11 */3737#define ROGUE_CR_FWCORE_DMI_RESERVED11 0x3438U3738#define ROGUE_CR_FWCORE_DMI_RESERVED11_MASKFULL 0x0000000000000000ULL3739 3740/* Register ROGUE_CR_FWCORE_DMI_RESERVED12 */3741#define ROGUE_CR_FWCORE_DMI_RESERVED12 0x3440U3742#define ROGUE_CR_FWCORE_DMI_RESERVED12_MASKFULL 0x0000000000000000ULL3743 3744/* Register ROGUE_CR_FWCORE_DMI_RESERVED13 */3745#define ROGUE_CR_FWCORE_DMI_RESERVED13 0x3448U3746#define ROGUE_CR_FWCORE_DMI_RESERVED13_MASKFULL 0x0000000000000000ULL3747 3748/* Register ROGUE_CR_FWCORE_DMI_RESERVED14 */3749#define ROGUE_CR_FWCORE_DMI_RESERVED14 0x3450U3750#define ROGUE_CR_FWCORE_DMI_RESERVED14_MASKFULL 0x0000000000000000ULL3751 3752/* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */3753#define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U3754#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL3755 3756/* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */3757#define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U3758#define ROGUE_CR_FWCORE_DMI_DMSTATUS_MASKFULL 0x0000000000000000ULL3759 3760/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED2, with 4 repeats */3761#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U3762/* Register ROGUE_CR_FWCORE_DMI_RESERVED20 */3763#define ROGUE_CR_FWCORE_DMI_RESERVED20 0x3490U3764#define ROGUE_CR_FWCORE_DMI_RESERVED20_MASKFULL 0x0000000000000000ULL3765 3766/* Register ROGUE_CR_FWCORE_DMI_RESERVED21 */3767#define ROGUE_CR_FWCORE_DMI_RESERVED21 0x3498U3768#define ROGUE_CR_FWCORE_DMI_RESERVED21_MASKFULL 0x0000000000000000ULL3769 3770/* Register ROGUE_CR_FWCORE_DMI_RESERVED22 */3771#define ROGUE_CR_FWCORE_DMI_RESERVED22 0x34A0U3772#define ROGUE_CR_FWCORE_DMI_RESERVED22_MASKFULL 0x0000000000000000ULL3773 3774/* Register ROGUE_CR_FWCORE_DMI_RESERVED23 */3775#define ROGUE_CR_FWCORE_DMI_RESERVED23 0x34A8U3776#define ROGUE_CR_FWCORE_DMI_RESERVED23_MASKFULL 0x0000000000000000ULL3777 3778/* Register ROGUE_CR_FWCORE_DMI_ABSTRACTCS */3779#define ROGUE_CR_FWCORE_DMI_ABSTRACTCS 0x34B0U3780#define ROGUE_CR_FWCORE_DMI_ABSTRACTCS_MASKFULL 0x0000000000000000ULL3781 3782/* Register ROGUE_CR_FWCORE_DMI_COMMAND */3783#define ROGUE_CR_FWCORE_DMI_COMMAND 0x34B8U3784#define ROGUE_CR_FWCORE_DMI_COMMAND_MASKFULL 0x0000000000000000ULL3785 3786/* Register ROGUE_CR_FWCORE_DMI_SBCS */3787#define ROGUE_CR_FWCORE_DMI_SBCS 0x35C0U3788#define ROGUE_CR_FWCORE_DMI_SBCS_MASKFULL 0x0000000000000000ULL3789 3790/* Register ROGUE_CR_FWCORE_DMI_SBADDRESS0 */3791#define ROGUE_CR_FWCORE_DMI_SBADDRESS0 0x35C8U3792#define ROGUE_CR_FWCORE_DMI_SBADDRESS0_MASKFULL 0x0000000000000000ULL3793 3794/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED3, with 2 repeats */3795#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U3796/* Register ROGUE_CR_FWCORE_DMI_RESERVED30 */3797#define ROGUE_CR_FWCORE_DMI_RESERVED30 0x34D0U3798#define ROGUE_CR_FWCORE_DMI_RESERVED30_MASKFULL 0x0000000000000000ULL3799 3800/* Register ROGUE_CR_FWCORE_DMI_RESERVED31 */3801#define ROGUE_CR_FWCORE_DMI_RESERVED31 0x34D8U3802#define ROGUE_CR_FWCORE_DMI_RESERVED31_MASKFULL 0x0000000000000000ULL3803 3804/* Register group: ROGUE_CR_FWCORE_DMI_SBDATA, with 4 repeats */3805#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U3806/* Register ROGUE_CR_FWCORE_DMI_SBDATA0 */3807#define ROGUE_CR_FWCORE_DMI_SBDATA0 0x35E0U3808#define ROGUE_CR_FWCORE_DMI_SBDATA0_MASKFULL 0x0000000000000000ULL3809 3810/* Register ROGUE_CR_FWCORE_DMI_SBDATA1 */3811#define ROGUE_CR_FWCORE_DMI_SBDATA1 0x35E8U3812#define ROGUE_CR_FWCORE_DMI_SBDATA1_MASKFULL 0x0000000000000000ULL3813 3814/* Register ROGUE_CR_FWCORE_DMI_SBDATA2 */3815#define ROGUE_CR_FWCORE_DMI_SBDATA2 0x35F0U3816#define ROGUE_CR_FWCORE_DMI_SBDATA2_MASKFULL 0x0000000000000000ULL3817 3818/* Register ROGUE_CR_FWCORE_DMI_SBDATA3 */3819#define ROGUE_CR_FWCORE_DMI_SBDATA3 0x35F8U3820#define ROGUE_CR_FWCORE_DMI_SBDATA3_MASKFULL 0x0000000000000000ULL3821 3822/* Register ROGUE_CR_FWCORE_DMI_HALTSUM0 */3823#define ROGUE_CR_FWCORE_DMI_HALTSUM0 0x3600U3824#define ROGUE_CR_FWCORE_DMI_HALTSUM0_MASKFULL 0x0000000000000000ULL3825 3826/* Register ROGUE_CR_SLC_CTRL_MISC */3827#define ROGUE_CR_SLC_CTRL_MISC 0x3800U3828#define ROGUE_CR_SLC_CTRL_MISC_MASKFULL 0xFFFFFFFF01FF010FULL3829#define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_SHIFT 32U3830#define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_CLRMSK 0x00000000FFFFFFFFULL3831#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_SHIFT 24U3832#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_CLRMSK 0xFFFFFFFFFEFFFFFFULL3833#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN 0x0000000001000000ULL3834#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 16U3835#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFFFFF00FFFFULL3836#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_64_BYTE 0x0000000000000000ULL3837#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_128_BYTE 0x0000000000010000ULL3838#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH1 0x0000000000100000ULL3839#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH2 0x0000000000110000ULL3840#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1 0x0000000000200000ULL3841#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH2_SCRAMBLE 0x0000000000210000ULL3842#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_SHIFT 8U3843#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_CLRMSK 0xFFFFFFFFFFFFFEFFULL3844#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_EN 0x0000000000000100ULL3845#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_SHIFT 3U3846#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_CLRMSK 0xFFFFFFFFFFFFFFF7ULL3847#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_EN 0x0000000000000008ULL3848#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_SHIFT 2U3849#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_CLRMSK 0xFFFFFFFFFFFFFFFBULL3850#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_EN 0x0000000000000004ULL3851#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_SHIFT 1U3852#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_CLRMSK 0xFFFFFFFFFFFFFFFDULL3853#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN 0x0000000000000002ULL3854#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_SHIFT 0U3855#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_CLRMSK 0xFFFFFFFFFFFFFFFEULL3856#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN 0x0000000000000001ULL3857 3858/* Register ROGUE_CR_SLC_CTRL_FLUSH_INVAL */3859#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL 0x3818U3860#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_MASKFULL 0x0000000080000FFFULL3861#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_SHIFT 31U3862#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_CLRMSK 0x7FFFFFFFU3863#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_EN 0x80000000U3864#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_SHIFT 11U3865#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_CLRMSK 0xFFFFF7FFU3866#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_EN 0x00000800U3867#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_SHIFT 10U3868#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_CLRMSK 0xFFFFFBFFU3869#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_EN 0x00000400U3870#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_SHIFT 9U3871#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_CLRMSK 0xFFFFFDFFU3872#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_EN 0x00000200U3873#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_SHIFT 8U3874#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_CLRMSK 0xFFFFFEFFU3875#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_EN 0x00000100U3876#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_SHIFT 7U3877#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_CLRMSK 0xFFFFFF7FU3878#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_EN 0x00000080U3879#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_SHIFT 6U3880#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_CLRMSK 0xFFFFFFBFU3881#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_EN 0x00000040U3882#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_SHIFT 5U3883#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_CLRMSK 0xFFFFFFDFU3884#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_EN 0x00000020U3885#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_SHIFT 4U3886#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_CLRMSK 0xFFFFFFEFU3887#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_EN 0x00000010U3888#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_SHIFT 3U3889#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_CLRMSK 0xFFFFFFF7U3890#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_EN 0x00000008U3891#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_SHIFT 2U3892#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_CLRMSK 0xFFFFFFFBU3893#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_EN 0x00000004U3894#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_SHIFT 1U3895#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_CLRMSK 0xFFFFFFFDU3896#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_EN 0x00000002U3897#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_SHIFT 0U3898#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_CLRMSK 0xFFFFFFFEU3899#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_EN 0x00000001U3900 3901/* Register ROGUE_CR_SLC_STATUS0 */3902#define ROGUE_CR_SLC_STATUS0 0x3820U3903#define ROGUE_CR_SLC_STATUS0_MASKFULL 0x0000000000000007ULL3904#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_SHIFT 2U3905#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_CLRMSK 0xFFFFFFFBU3906#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_EN 0x00000004U3907#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_SHIFT 1U3908#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_CLRMSK 0xFFFFFFFDU3909#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_EN 0x00000002U3910#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_SHIFT 0U3911#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_CLRMSK 0xFFFFFFFEU3912#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_EN 0x00000001U3913 3914/* Register ROGUE_CR_SLC_CTRL_BYPASS */3915#define ROGUE_CR_SLC_CTRL_BYPASS 0x3828U3916#define ROGUE_CR_SLC_CTRL_BYPASS__XE_MEM__MASKFULL 0x0FFFFFFFFFFF7FFFULL3917#define ROGUE_CR_SLC_CTRL_BYPASS_MASKFULL 0x000000000FFFFFFFULL3918#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_SHIFT 59U3919#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_CLRMSK 0xF7FFFFFFFFFFFFFFULL3920#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_EN 0x0800000000000000ULL3921#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_SHIFT 58U3922#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_CLRMSK 0xFBFFFFFFFFFFFFFFULL3923#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_EN 0x0400000000000000ULL3924#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_SHIFT 57U3925#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_CLRMSK 0xFDFFFFFFFFFFFFFFULL3926#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_EN 0x0200000000000000ULL3927#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_SHIFT 56U3928#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_CLRMSK 0xFEFFFFFFFFFFFFFFULL3929#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_EN 0x0100000000000000ULL3930#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_SHIFT 55U3931#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_CLRMSK 0xFF7FFFFFFFFFFFFFULL3932#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_EN 0x0080000000000000ULL3933#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_SHIFT 54U3934#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_CLRMSK 0xFFBFFFFFFFFFFFFFULL3935#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_EN 0x0040000000000000ULL3936#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_SHIFT 53U3937#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_CLRMSK 0xFFDFFFFFFFFFFFFFULL3938#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_EN 0x0020000000000000ULL3939#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_SHIFT 52U3940#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_CLRMSK 0xFFEFFFFFFFFFFFFFULL3941#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_EN 0x0010000000000000ULL3942#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_SHIFT 51U3943#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_CLRMSK 0xFFF7FFFFFFFFFFFFULL3944#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_EN 0x0008000000000000ULL3945#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_SHIFT 50U3946#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_CLRMSK 0xFFFBFFFFFFFFFFFFULL3947#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_EN 0x0004000000000000ULL3948#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_SHIFT 49U3949#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_CLRMSK 0xFFFDFFFFFFFFFFFFULL3950#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_EN 0x0002000000000000ULL3951#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_SHIFT 48U3952#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_CLRMSK 0xFFFEFFFFFFFFFFFFULL3953#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_EN 0x0001000000000000ULL3954#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_SHIFT 47U3955#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_CLRMSK 0xFFFF7FFFFFFFFFFFULL3956#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_EN 0x0000800000000000ULL3957#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_SHIFT 46U3958#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_CLRMSK 0xFFFFBFFFFFFFFFFFULL3959#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_EN 0x0000400000000000ULL3960#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_SHIFT 45U3961#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_CLRMSK 0xFFFFDFFFFFFFFFFFULL3962#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_EN 0x0000200000000000ULL3963#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 44U3964#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_CLRMSK 0xFFFFEFFFFFFFFFFFULL3965#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_EN 0x0000100000000000ULL3966#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_SHIFT 43U3967#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_CLRMSK 0xFFFFF7FFFFFFFFFFULL3968#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_EN 0x0000080000000000ULL3969#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_SHIFT 42U3970#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_CLRMSK 0xFFFFFBFFFFFFFFFFULL3971#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_EN 0x0000040000000000ULL3972#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_SHIFT 41U3973#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_CLRMSK 0xFFFFFDFFFFFFFFFFULL3974#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_EN 0x0000020000000000ULL3975#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_SHIFT 40U3976#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_CLRMSK 0xFFFFFEFFFFFFFFFFULL3977#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_EN 0x0000010000000000ULL3978#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_SHIFT 39U3979#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_CLRMSK 0xFFFFFF7FFFFFFFFFULL3980#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_EN 0x0000008000000000ULL3981#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_SHIFT 38U3982#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_CLRMSK 0xFFFFFFBFFFFFFFFFULL3983#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_EN 0x0000004000000000ULL3984#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_SHIFT 37U3985#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_CLRMSK 0xFFFFFFDFFFFFFFFFULL3986#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_EN 0x0000002000000000ULL3987#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 36U3988#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_CLRMSK 0xFFFFFFEFFFFFFFFFULL3989#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_EN 0x0000001000000000ULL3990#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_SHIFT 35U3991#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_CLRMSK 0xFFFFFFF7FFFFFFFFULL3992#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_EN 0x0000000800000000ULL3993#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_SHIFT 34U3994#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_CLRMSK 0xFFFFFFFBFFFFFFFFULL3995#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_EN 0x0000000400000000ULL3996#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_SHIFT 33U3997#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_CLRMSK 0xFFFFFFFDFFFFFFFFULL3998#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_EN 0x0000000200000000ULL3999#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_SHIFT 32U4000#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_CLRMSK 0xFFFFFFFEFFFFFFFFULL4001#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_EN 0x0000000100000000ULL4002#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_SHIFT 31U4003#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_CLRMSK 0xFFFFFFFF7FFFFFFFULL4004#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_EN 0x0000000080000000ULL4005#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_SHIFT 30U4006#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_CLRMSK 0xFFFFFFFFBFFFFFFFULL4007#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_EN 0x0000000040000000ULL4008#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_SHIFT 29U4009#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_CLRMSK 0xFFFFFFFFDFFFFFFFULL4010#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_EN 0x0000000020000000ULL4011#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_SHIFT 28U4012#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_CLRMSK 0xFFFFFFFFEFFFFFFFULL4013#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_EN 0x0000000010000000ULL4014#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_SHIFT 27U4015#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_CLRMSK 0xFFFFFFFFF7FFFFFFULL4016#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_EN 0x0000000008000000ULL4017#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_SHIFT 26U4018#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_CLRMSK 0xFFFFFFFFFBFFFFFFULL4019#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_EN 0x0000000004000000ULL4020#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_SHIFT 25U4021#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_CLRMSK 0xFFFFFFFFFDFFFFFFULL4022#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_EN 0x0000000002000000ULL4023#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_SHIFT 24U4024#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_CLRMSK 0xFFFFFFFFFEFFFFFFULL4025#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_EN 0x0000000001000000ULL4026#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_SHIFT 23U4027#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_CLRMSK 0xFFFFFFFFFF7FFFFFULL4028#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_EN 0x0000000000800000ULL4029#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_SHIFT 22U4030#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_CLRMSK 0xFFFFFFFFFFBFFFFFULL4031#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_EN 0x0000000000400000ULL4032#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 21U4033#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_CLRMSK 0xFFFFFFFFFFDFFFFFULL4034#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_EN 0x0000000000200000ULL4035#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_SHIFT 20U4036#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_CLRMSK 0xFFFFFFFFFFEFFFFFULL4037#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_EN 0x0000000000100000ULL4038#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_SHIFT 19U4039#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_CLRMSK 0xFFFFFFFFFFF7FFFFULL4040#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_EN 0x0000000000080000ULL4041#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 18U4042#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_CLRMSK 0xFFFFFFFFFFFBFFFFULL4043#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_EN 0x0000000000040000ULL4044#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 17U4045#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_CLRMSK 0xFFFFFFFFFFFDFFFFULL4046#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_EN 0x0000000000020000ULL4047#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_SHIFT 16U4048#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_CLRMSK 0xFFFFFFFFFFFEFFFFULL4049#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_EN 0x0000000000010000ULL4050#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 15U4051#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_CLRMSK 0xFFFFFFFFFFFF7FFFULL4052#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN 0x0000000000008000ULL4053#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_SHIFT 14U4054#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_CLRMSK 0xFFFFFFFFFFFFBFFFULL4055#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_EN 0x0000000000004000ULL4056#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_SHIFT 13U4057#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_CLRMSK 0xFFFFFFFFFFFFDFFFULL4058#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_EN 0x0000000000002000ULL4059#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_SHIFT 12U4060#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_CLRMSK 0xFFFFFFFFFFFFEFFFULL4061#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_EN 0x0000000000001000ULL4062#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_SHIFT 11U4063#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_CLRMSK 0xFFFFFFFFFFFFF7FFULL4064#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_EN 0x0000000000000800ULL4065#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_SHIFT 10U4066#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_CLRMSK 0xFFFFFFFFFFFFFBFFULL4067#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_EN 0x0000000000000400ULL4068#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_SHIFT 9U4069#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_CLRMSK 0xFFFFFFFFFFFFFDFFULL4070#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_EN 0x0000000000000200ULL4071#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_SHIFT 8U4072#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_CLRMSK 0xFFFFFFFFFFFFFEFFULL4073#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_EN 0x0000000000000100ULL4074#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_SHIFT 7U4075#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_CLRMSK 0xFFFFFFFFFFFFFF7FULL4076#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_EN 0x0000000000000080ULL4077#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_SHIFT 6U4078#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_CLRMSK 0xFFFFFFFFFFFFFFBFULL4079#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_EN 0x0000000000000040ULL4080#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_SHIFT 5U4081#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_CLRMSK 0xFFFFFFFFFFFFFFDFULL4082#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_EN 0x0000000000000020ULL4083#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_SHIFT 4U4084#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_CLRMSK 0xFFFFFFFFFFFFFFEFULL4085#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_EN 0x0000000000000010ULL4086#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_SHIFT 3U4087#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFFF7ULL4088#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_EN 0x0000000000000008ULL4089#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2U4090#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFFBULL4091#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_EN 0x0000000000000004ULL4092#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_SHIFT 1U4093#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_CLRMSK 0xFFFFFFFFFFFFFFFDULL4094#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_EN 0x0000000000000002ULL4095#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_SHIFT 0U4096#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_CLRMSK 0xFFFFFFFFFFFFFFFEULL4097#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_EN 0x0000000000000001ULL4098 4099/* Register ROGUE_CR_SLC_STATUS1 */4100#define ROGUE_CR_SLC_STATUS1 0x3870U4101#define ROGUE_CR_SLC_STATUS1_MASKFULL 0x800003FF03FFFFFFULL4102#define ROGUE_CR_SLC_STATUS1_PAUSED_SHIFT 63U4103#define ROGUE_CR_SLC_STATUS1_PAUSED_CLRMSK 0x7FFFFFFFFFFFFFFFULL4104#define ROGUE_CR_SLC_STATUS1_PAUSED_EN 0x8000000000000000ULL4105#define ROGUE_CR_SLC_STATUS1_READS1_SHIFT 32U4106#define ROGUE_CR_SLC_STATUS1_READS1_CLRMSK 0xFFFFFC00FFFFFFFFULL4107#define ROGUE_CR_SLC_STATUS1_READS0_SHIFT 16U4108#define ROGUE_CR_SLC_STATUS1_READS0_CLRMSK 0xFFFFFFFFFC00FFFFULL4109#define ROGUE_CR_SLC_STATUS1_READS1_EXT_SHIFT 8U4110#define ROGUE_CR_SLC_STATUS1_READS1_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL4111#define ROGUE_CR_SLC_STATUS1_READS0_EXT_SHIFT 0U4112#define ROGUE_CR_SLC_STATUS1_READS0_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL4113 4114/* Register ROGUE_CR_SLC_IDLE */4115#define ROGUE_CR_SLC_IDLE 0x3898U4116#define ROGUE_CR_SLC_IDLE__XE_MEM__MASKFULL 0x00000000000003FFULL4117#define ROGUE_CR_SLC_IDLE_MASKFULL 0x00000000000000FFULL4118#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_SHIFT 9U4119#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_CLRMSK 0xFFFFFDFFU4120#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_EN 0x00000200U4121#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_SHIFT 8U4122#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFEFFU4123#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_EN 0x00000100U4124#define ROGUE_CR_SLC_IDLE_IMGBV4_SHIFT 7U4125#define ROGUE_CR_SLC_IDLE_IMGBV4_CLRMSK 0xFFFFFF7FU4126#define ROGUE_CR_SLC_IDLE_IMGBV4_EN 0x00000080U4127#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_SHIFT 6U4128#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_CLRMSK 0xFFFFFFBFU4129#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_EN 0x00000040U4130#define ROGUE_CR_SLC_IDLE_RBOFIFO_SHIFT 5U4131#define ROGUE_CR_SLC_IDLE_RBOFIFO_CLRMSK 0xFFFFFFDFU4132#define ROGUE_CR_SLC_IDLE_RBOFIFO_EN 0x00000020U4133#define ROGUE_CR_SLC_IDLE_FRC_CONV_SHIFT 4U4134#define ROGUE_CR_SLC_IDLE_FRC_CONV_CLRMSK 0xFFFFFFEFU4135#define ROGUE_CR_SLC_IDLE_FRC_CONV_EN 0x00000010U4136#define ROGUE_CR_SLC_IDLE_VXE_CONV_SHIFT 3U4137#define ROGUE_CR_SLC_IDLE_VXE_CONV_CLRMSK 0xFFFFFFF7U4138#define ROGUE_CR_SLC_IDLE_VXE_CONV_EN 0x00000008U4139#define ROGUE_CR_SLC_IDLE_VXD_CONV_SHIFT 2U4140#define ROGUE_CR_SLC_IDLE_VXD_CONV_CLRMSK 0xFFFFFFFBU4141#define ROGUE_CR_SLC_IDLE_VXD_CONV_EN 0x00000004U4142#define ROGUE_CR_SLC_IDLE_BIF1_CONV_SHIFT 1U4143#define ROGUE_CR_SLC_IDLE_BIF1_CONV_CLRMSK 0xFFFFFFFDU4144#define ROGUE_CR_SLC_IDLE_BIF1_CONV_EN 0x00000002U4145#define ROGUE_CR_SLC_IDLE_CBAR_SHIFT 0U4146#define ROGUE_CR_SLC_IDLE_CBAR_CLRMSK 0xFFFFFFFEU4147#define ROGUE_CR_SLC_IDLE_CBAR_EN 0x00000001U4148 4149/* Register ROGUE_CR_SLC_STATUS2 */4150#define ROGUE_CR_SLC_STATUS2 0x3908U4151#define ROGUE_CR_SLC_STATUS2_MASKFULL 0x000003FF03FFFFFFULL4152#define ROGUE_CR_SLC_STATUS2_READS3_SHIFT 32U4153#define ROGUE_CR_SLC_STATUS2_READS3_CLRMSK 0xFFFFFC00FFFFFFFFULL4154#define ROGUE_CR_SLC_STATUS2_READS2_SHIFT 16U4155#define ROGUE_CR_SLC_STATUS2_READS2_CLRMSK 0xFFFFFFFFFC00FFFFULL4156#define ROGUE_CR_SLC_STATUS2_READS3_EXT_SHIFT 8U4157#define ROGUE_CR_SLC_STATUS2_READS3_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL4158#define ROGUE_CR_SLC_STATUS2_READS2_EXT_SHIFT 0U4159#define ROGUE_CR_SLC_STATUS2_READS2_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL4160 4161/* Register ROGUE_CR_SLC_CTRL_MISC2 */4162#define ROGUE_CR_SLC_CTRL_MISC2 0x3930U4163#define ROGUE_CR_SLC_CTRL_MISC2_MASKFULL 0x00000000FFFFFFFFULL4164#define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_SHIFT 0U4165#define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_CLRMSK 0x00000000U4166 4167/* Register ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE */4168#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE 0x3938U4169#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_MASKFULL 0x0000000000000001ULL4170#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_SHIFT 0U4171#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_CLRMSK 0xFFFFFFFEU4172#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_EN 0x00000001U4173 4174/* Register ROGUE_CR_USC_UVS0_CHECKSUM */4175#define ROGUE_CR_USC_UVS0_CHECKSUM 0x5000U4176#define ROGUE_CR_USC_UVS0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4177#define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_SHIFT 0U4178#define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_CLRMSK 0x00000000U4179 4180/* Register ROGUE_CR_USC_UVS1_CHECKSUM */4181#define ROGUE_CR_USC_UVS1_CHECKSUM 0x5008U4182#define ROGUE_CR_USC_UVS1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4183#define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_SHIFT 0U4184#define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_CLRMSK 0x00000000U4185 4186/* Register ROGUE_CR_USC_UVS2_CHECKSUM */4187#define ROGUE_CR_USC_UVS2_CHECKSUM 0x5010U4188#define ROGUE_CR_USC_UVS2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4189#define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_SHIFT 0U4190#define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_CLRMSK 0x00000000U4191 4192/* Register ROGUE_CR_USC_UVS3_CHECKSUM */4193#define ROGUE_CR_USC_UVS3_CHECKSUM 0x5018U4194#define ROGUE_CR_USC_UVS3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4195#define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_SHIFT 0U4196#define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_CLRMSK 0x00000000U4197 4198/* Register ROGUE_CR_PPP_SIGNATURE */4199#define ROGUE_CR_PPP_SIGNATURE 0x5020U4200#define ROGUE_CR_PPP_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL4201#define ROGUE_CR_PPP_SIGNATURE_VALUE_SHIFT 0U4202#define ROGUE_CR_PPP_SIGNATURE_VALUE_CLRMSK 0x00000000U4203 4204/* Register ROGUE_CR_TE_SIGNATURE */4205#define ROGUE_CR_TE_SIGNATURE 0x5028U4206#define ROGUE_CR_TE_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL4207#define ROGUE_CR_TE_SIGNATURE_VALUE_SHIFT 0U4208#define ROGUE_CR_TE_SIGNATURE_VALUE_CLRMSK 0x00000000U4209 4210/* Register ROGUE_CR_TE_CHECKSUM */4211#define ROGUE_CR_TE_CHECKSUM 0x5110U4212#define ROGUE_CR_TE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4213#define ROGUE_CR_TE_CHECKSUM_VALUE_SHIFT 0U4214#define ROGUE_CR_TE_CHECKSUM_VALUE_CLRMSK 0x00000000U4215 4216/* Register ROGUE_CR_USC_UVB_CHECKSUM */4217#define ROGUE_CR_USC_UVB_CHECKSUM 0x5118U4218#define ROGUE_CR_USC_UVB_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4219#define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_SHIFT 0U4220#define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_CLRMSK 0x00000000U4221 4222/* Register ROGUE_CR_VCE_CHECKSUM */4223#define ROGUE_CR_VCE_CHECKSUM 0x5030U4224#define ROGUE_CR_VCE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4225#define ROGUE_CR_VCE_CHECKSUM_VALUE_SHIFT 0U4226#define ROGUE_CR_VCE_CHECKSUM_VALUE_CLRMSK 0x00000000U4227 4228/* Register ROGUE_CR_ISP_PDS_CHECKSUM */4229#define ROGUE_CR_ISP_PDS_CHECKSUM 0x5038U4230#define ROGUE_CR_ISP_PDS_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4231#define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT 0U4232#define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_CLRMSK 0x00000000U4233 4234/* Register ROGUE_CR_ISP_TPF_CHECKSUM */4235#define ROGUE_CR_ISP_TPF_CHECKSUM 0x5040U4236#define ROGUE_CR_ISP_TPF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4237#define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT 0U4238#define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_CLRMSK 0x00000000U4239 4240/* Register ROGUE_CR_TFPU_PLANE0_CHECKSUM */4241#define ROGUE_CR_TFPU_PLANE0_CHECKSUM 0x5048U4242#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4243#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_SHIFT 0U4244#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_CLRMSK 0x00000000U4245 4246/* Register ROGUE_CR_TFPU_PLANE1_CHECKSUM */4247#define ROGUE_CR_TFPU_PLANE1_CHECKSUM 0x5050U4248#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4249#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_SHIFT 0U4250#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_CLRMSK 0x00000000U4251 4252/* Register ROGUE_CR_PBE_CHECKSUM */4253#define ROGUE_CR_PBE_CHECKSUM 0x5058U4254#define ROGUE_CR_PBE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4255#define ROGUE_CR_PBE_CHECKSUM_VALUE_SHIFT 0U4256#define ROGUE_CR_PBE_CHECKSUM_VALUE_CLRMSK 0x00000000U4257 4258/* Register ROGUE_CR_PDS_DOUTM_STM_SIGNATURE */4259#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE 0x5060U4260#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL4261#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_SHIFT 0U4262#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_CLRMSK 0x00000000U4263 4264/* Register ROGUE_CR_IFPU_ISP_CHECKSUM */4265#define ROGUE_CR_IFPU_ISP_CHECKSUM 0x5068U4266#define ROGUE_CR_IFPU_ISP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4267#define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT 0U4268#define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_CLRMSK 0x00000000U4269 4270/* Register ROGUE_CR_USC_UVS4_CHECKSUM */4271#define ROGUE_CR_USC_UVS4_CHECKSUM 0x5100U4272#define ROGUE_CR_USC_UVS4_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4273#define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_SHIFT 0U4274#define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_CLRMSK 0x00000000U4275 4276/* Register ROGUE_CR_USC_UVS5_CHECKSUM */4277#define ROGUE_CR_USC_UVS5_CHECKSUM 0x5108U4278#define ROGUE_CR_USC_UVS5_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4279#define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_SHIFT 0U4280#define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_CLRMSK 0x00000000U4281 4282/* Register ROGUE_CR_PPP_CLIP_CHECKSUM */4283#define ROGUE_CR_PPP_CLIP_CHECKSUM 0x5120U4284#define ROGUE_CR_PPP_CLIP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL4285#define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT 0U4286#define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_CLRMSK 0x00000000U4287 4288/* Register ROGUE_CR_PERF_TA_PHASE */4289#define ROGUE_CR_PERF_TA_PHASE 0x6008U4290#define ROGUE_CR_PERF_TA_PHASE_MASKFULL 0x00000000FFFFFFFFULL4291#define ROGUE_CR_PERF_TA_PHASE_COUNT_SHIFT 0U4292#define ROGUE_CR_PERF_TA_PHASE_COUNT_CLRMSK 0x00000000U4293 4294/* Register ROGUE_CR_PERF_3D_PHASE */4295#define ROGUE_CR_PERF_3D_PHASE 0x6010U4296#define ROGUE_CR_PERF_3D_PHASE_MASKFULL 0x00000000FFFFFFFFULL4297#define ROGUE_CR_PERF_3D_PHASE_COUNT_SHIFT 0U4298#define ROGUE_CR_PERF_3D_PHASE_COUNT_CLRMSK 0x00000000U4299 4300/* Register ROGUE_CR_PERF_COMPUTE_PHASE */4301#define ROGUE_CR_PERF_COMPUTE_PHASE 0x6018U4302#define ROGUE_CR_PERF_COMPUTE_PHASE_MASKFULL 0x00000000FFFFFFFFULL4303#define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_SHIFT 0U4304#define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_CLRMSK 0x00000000U4305 4306/* Register ROGUE_CR_PERF_TA_CYCLE */4307#define ROGUE_CR_PERF_TA_CYCLE 0x6020U4308#define ROGUE_CR_PERF_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL4309#define ROGUE_CR_PERF_TA_CYCLE_COUNT_SHIFT 0U4310#define ROGUE_CR_PERF_TA_CYCLE_COUNT_CLRMSK 0x00000000U4311 4312/* Register ROGUE_CR_PERF_3D_CYCLE */4313#define ROGUE_CR_PERF_3D_CYCLE 0x6028U4314#define ROGUE_CR_PERF_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL4315#define ROGUE_CR_PERF_3D_CYCLE_COUNT_SHIFT 0U4316#define ROGUE_CR_PERF_3D_CYCLE_COUNT_CLRMSK 0x00000000U4317 4318/* Register ROGUE_CR_PERF_COMPUTE_CYCLE */4319#define ROGUE_CR_PERF_COMPUTE_CYCLE 0x6030U4320#define ROGUE_CR_PERF_COMPUTE_CYCLE_MASKFULL 0x00000000FFFFFFFFULL4321#define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_SHIFT 0U4322#define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_CLRMSK 0x00000000U4323 4324/* Register ROGUE_CR_PERF_TA_OR_3D_CYCLE */4325#define ROGUE_CR_PERF_TA_OR_3D_CYCLE 0x6038U4326#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL4327#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_SHIFT 0U4328#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_CLRMSK 0x00000000U4329 4330/* Register ROGUE_CR_PERF_INITIAL_TA_CYCLE */4331#define ROGUE_CR_PERF_INITIAL_TA_CYCLE 0x6040U4332#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL4333#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_SHIFT 0U4334#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_CLRMSK 0x00000000U4335 4336/* Register ROGUE_CR_PERF_SLC0_READ_STALL */4337#define ROGUE_CR_PERF_SLC0_READ_STALL 0x60B8U4338#define ROGUE_CR_PERF_SLC0_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL4339#define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT 0U4340#define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK 0x00000000U4341 4342/* Register ROGUE_CR_PERF_SLC0_WRITE_STALL */4343#define ROGUE_CR_PERF_SLC0_WRITE_STALL 0x60C0U4344#define ROGUE_CR_PERF_SLC0_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL4345#define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT 0U4346#define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK 0x00000000U4347 4348/* Register ROGUE_CR_PERF_SLC1_READ_STALL */4349#define ROGUE_CR_PERF_SLC1_READ_STALL 0x60E0U4350#define ROGUE_CR_PERF_SLC1_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL4351#define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT 0U4352#define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_CLRMSK 0x00000000U4353 4354/* Register ROGUE_CR_PERF_SLC1_WRITE_STALL */4355#define ROGUE_CR_PERF_SLC1_WRITE_STALL 0x60E8U4356#define ROGUE_CR_PERF_SLC1_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL4357#define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT 0U4358#define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_CLRMSK 0x00000000U4359 4360/* Register ROGUE_CR_PERF_SLC2_READ_STALL */4361#define ROGUE_CR_PERF_SLC2_READ_STALL 0x6158U4362#define ROGUE_CR_PERF_SLC2_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL4363#define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT 0U4364#define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_CLRMSK 0x00000000U4365 4366/* Register ROGUE_CR_PERF_SLC2_WRITE_STALL */4367#define ROGUE_CR_PERF_SLC2_WRITE_STALL 0x6160U4368#define ROGUE_CR_PERF_SLC2_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL4369#define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT 0U4370#define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_CLRMSK 0x00000000U4371 4372/* Register ROGUE_CR_PERF_SLC3_READ_STALL */4373#define ROGUE_CR_PERF_SLC3_READ_STALL 0x6180U4374#define ROGUE_CR_PERF_SLC3_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL4375#define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT 0U4376#define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_CLRMSK 0x00000000U4377 4378/* Register ROGUE_CR_PERF_SLC3_WRITE_STALL */4379#define ROGUE_CR_PERF_SLC3_WRITE_STALL 0x6188U4380#define ROGUE_CR_PERF_SLC3_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL4381#define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT 0U4382#define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_CLRMSK 0x00000000U4383 4384/* Register ROGUE_CR_PERF_3D_SPINUP */4385#define ROGUE_CR_PERF_3D_SPINUP 0x6220U4386#define ROGUE_CR_PERF_3D_SPINUP_MASKFULL 0x00000000FFFFFFFFULL4387#define ROGUE_CR_PERF_3D_SPINUP_CYCLES_SHIFT 0U4388#define ROGUE_CR_PERF_3D_SPINUP_CYCLES_CLRMSK 0x00000000U4389 4390/* Register ROGUE_CR_AXI_ACE_LITE_CONFIGURATION */4391#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION 0x38C0U4392#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_MASKFULL 0x00003FFFFFFFFFFFULL4393#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT 45U4394#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_CLRMSK 0xFFFFDFFFFFFFFFFFULL4395#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_EN 0x0000200000000000ULL4396#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_SHIFT 37U4397#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_CLRMSK 0xFFFFE01FFFFFFFFFULL4398#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT 36U4399#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_CLRMSK \4400	0xFFFFFFEFFFFFFFFFULL4401#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_EN \4402	0x0000001000000000ULL4403#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_SHIFT 35U4404#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_CLRMSK 0xFFFFFFF7FFFFFFFFULL4405#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_EN 0x0000000800000000ULL4406#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_SHIFT 34U4407#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_CLRMSK 0xFFFFFFFBFFFFFFFFULL4408#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_EN 0x0000000400000000ULL4409#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT 30U4410#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFC3FFFFFFFULL4411#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT 26U4412#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_CLRMSK 0xFFFFFFFFC3FFFFFFULL4413#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT 22U4414#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_CLRMSK 0xFFFFFFFFFC3FFFFFULL4415#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_SHIFT 20U4416#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFCFFFFFULL4417#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_SHIFT 18U4418#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFF3FFFFULL4419#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT 16U4420#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFFFFFCFFFFULL4421#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT 14U4422#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFF3FFFULL4423#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT 12U4424#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFFCFFFULL4425#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT 10U4426#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFF3FFULL4427#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT 8U4428#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFCFFULL4429#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_SHIFT 4U4430#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFF0FULL4431#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_SHIFT 0U4432#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFFF0ULL4433 4434/* Register ROGUE_CR_POWER_ESTIMATE_RESULT */4435#define ROGUE_CR_POWER_ESTIMATE_RESULT 0x6328U4436#define ROGUE_CR_POWER_ESTIMATE_RESULT_MASKFULL 0x00000000FFFFFFFFULL4437#define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_SHIFT 0U4438#define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_CLRMSK 0x00000000U4439 4440/* Register ROGUE_CR_TA_PERF */4441#define ROGUE_CR_TA_PERF 0x7600U4442#define ROGUE_CR_TA_PERF_MASKFULL 0x000000000000001FULL4443#define ROGUE_CR_TA_PERF_CLR_3_SHIFT 4U4444#define ROGUE_CR_TA_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4445#define ROGUE_CR_TA_PERF_CLR_3_EN 0x00000010U4446#define ROGUE_CR_TA_PERF_CLR_2_SHIFT 3U4447#define ROGUE_CR_TA_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4448#define ROGUE_CR_TA_PERF_CLR_2_EN 0x00000008U4449#define ROGUE_CR_TA_PERF_CLR_1_SHIFT 2U4450#define ROGUE_CR_TA_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4451#define ROGUE_CR_TA_PERF_CLR_1_EN 0x00000004U4452#define ROGUE_CR_TA_PERF_CLR_0_SHIFT 1U4453#define ROGUE_CR_TA_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4454#define ROGUE_CR_TA_PERF_CLR_0_EN 0x00000002U4455#define ROGUE_CR_TA_PERF_CTRL_ENABLE_SHIFT 0U4456#define ROGUE_CR_TA_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4457#define ROGUE_CR_TA_PERF_CTRL_ENABLE_EN 0x00000001U4458 4459/* Register ROGUE_CR_TA_PERF_SELECT0 */4460#define ROGUE_CR_TA_PERF_SELECT0 0x7608U4461#define ROGUE_CR_TA_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4462#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_SHIFT 48U4463#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4464#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_SHIFT 32U4465#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4466#define ROGUE_CR_TA_PERF_SELECT0_MODE_SHIFT 21U4467#define ROGUE_CR_TA_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4468#define ROGUE_CR_TA_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4469#define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4470#define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4471#define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_SHIFT 0U4472#define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4473 4474/* Register ROGUE_CR_TA_PERF_SELECT1 */4475#define ROGUE_CR_TA_PERF_SELECT1 0x7610U4476#define ROGUE_CR_TA_PERF_SELECT1_MASKFULL 0x3FFF3FFF003FFFFFULL4477#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_SHIFT 48U4478#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4479#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_SHIFT 32U4480#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4481#define ROGUE_CR_TA_PERF_SELECT1_MODE_SHIFT 21U4482#define ROGUE_CR_TA_PERF_SELECT1_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4483#define ROGUE_CR_TA_PERF_SELECT1_MODE_EN 0x0000000000200000ULL4484#define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_SHIFT 16U4485#define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4486#define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_SHIFT 0U4487#define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4488 4489/* Register ROGUE_CR_TA_PERF_SELECT2 */4490#define ROGUE_CR_TA_PERF_SELECT2 0x7618U4491#define ROGUE_CR_TA_PERF_SELECT2_MASKFULL 0x3FFF3FFF003FFFFFULL4492#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_SHIFT 48U4493#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4494#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_SHIFT 32U4495#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4496#define ROGUE_CR_TA_PERF_SELECT2_MODE_SHIFT 21U4497#define ROGUE_CR_TA_PERF_SELECT2_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4498#define ROGUE_CR_TA_PERF_SELECT2_MODE_EN 0x0000000000200000ULL4499#define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_SHIFT 16U4500#define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4501#define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_SHIFT 0U4502#define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4503 4504/* Register ROGUE_CR_TA_PERF_SELECT3 */4505#define ROGUE_CR_TA_PERF_SELECT3 0x7620U4506#define ROGUE_CR_TA_PERF_SELECT3_MASKFULL 0x3FFF3FFF003FFFFFULL4507#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_SHIFT 48U4508#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4509#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_SHIFT 32U4510#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4511#define ROGUE_CR_TA_PERF_SELECT3_MODE_SHIFT 21U4512#define ROGUE_CR_TA_PERF_SELECT3_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4513#define ROGUE_CR_TA_PERF_SELECT3_MODE_EN 0x0000000000200000ULL4514#define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_SHIFT 16U4515#define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4516#define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_SHIFT 0U4517#define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4518 4519/* Register ROGUE_CR_TA_PERF_SELECTED_BITS */4520#define ROGUE_CR_TA_PERF_SELECTED_BITS 0x7648U4521#define ROGUE_CR_TA_PERF_SELECTED_BITS_MASKFULL 0xFFFFFFFFFFFFFFFFULL4522#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_SHIFT 48U4523#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_CLRMSK 0x0000FFFFFFFFFFFFULL4524#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_SHIFT 32U4525#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_CLRMSK 0xFFFF0000FFFFFFFFULL4526#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_SHIFT 16U4527#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_CLRMSK 0xFFFFFFFF0000FFFFULL4528#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_SHIFT 0U4529#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_CLRMSK 0xFFFFFFFFFFFF0000ULL4530 4531/* Register ROGUE_CR_TA_PERF_COUNTER_0 */4532#define ROGUE_CR_TA_PERF_COUNTER_0 0x7650U4533#define ROGUE_CR_TA_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4534#define ROGUE_CR_TA_PERF_COUNTER_0_REG_SHIFT 0U4535#define ROGUE_CR_TA_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4536 4537/* Register ROGUE_CR_TA_PERF_COUNTER_1 */4538#define ROGUE_CR_TA_PERF_COUNTER_1 0x7658U4539#define ROGUE_CR_TA_PERF_COUNTER_1_MASKFULL 0x00000000FFFFFFFFULL4540#define ROGUE_CR_TA_PERF_COUNTER_1_REG_SHIFT 0U4541#define ROGUE_CR_TA_PERF_COUNTER_1_REG_CLRMSK 0x00000000U4542 4543/* Register ROGUE_CR_TA_PERF_COUNTER_2 */4544#define ROGUE_CR_TA_PERF_COUNTER_2 0x7660U4545#define ROGUE_CR_TA_PERF_COUNTER_2_MASKFULL 0x00000000FFFFFFFFULL4546#define ROGUE_CR_TA_PERF_COUNTER_2_REG_SHIFT 0U4547#define ROGUE_CR_TA_PERF_COUNTER_2_REG_CLRMSK 0x00000000U4548 4549/* Register ROGUE_CR_TA_PERF_COUNTER_3 */4550#define ROGUE_CR_TA_PERF_COUNTER_3 0x7668U4551#define ROGUE_CR_TA_PERF_COUNTER_3_MASKFULL 0x00000000FFFFFFFFULL4552#define ROGUE_CR_TA_PERF_COUNTER_3_REG_SHIFT 0U4553#define ROGUE_CR_TA_PERF_COUNTER_3_REG_CLRMSK 0x00000000U4554 4555/* Register ROGUE_CR_RASTERISATION_PERF */4556#define ROGUE_CR_RASTERISATION_PERF 0x7700U4557#define ROGUE_CR_RASTERISATION_PERF_MASKFULL 0x000000000000001FULL4558#define ROGUE_CR_RASTERISATION_PERF_CLR_3_SHIFT 4U4559#define ROGUE_CR_RASTERISATION_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4560#define ROGUE_CR_RASTERISATION_PERF_CLR_3_EN 0x00000010U4561#define ROGUE_CR_RASTERISATION_PERF_CLR_2_SHIFT 3U4562#define ROGUE_CR_RASTERISATION_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4563#define ROGUE_CR_RASTERISATION_PERF_CLR_2_EN 0x00000008U4564#define ROGUE_CR_RASTERISATION_PERF_CLR_1_SHIFT 2U4565#define ROGUE_CR_RASTERISATION_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4566#define ROGUE_CR_RASTERISATION_PERF_CLR_1_EN 0x00000004U4567#define ROGUE_CR_RASTERISATION_PERF_CLR_0_SHIFT 1U4568#define ROGUE_CR_RASTERISATION_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4569#define ROGUE_CR_RASTERISATION_PERF_CLR_0_EN 0x00000002U4570#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_SHIFT 0U4571#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4572#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_EN 0x00000001U4573 4574/* Register ROGUE_CR_RASTERISATION_PERF_SELECT0 */4575#define ROGUE_CR_RASTERISATION_PERF_SELECT0 0x7708U4576#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4577#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_SHIFT 48U4578#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4579#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_SHIFT 32U4580#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4581#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_SHIFT 21U4582#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4583#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4584#define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4585#define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4586#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_SHIFT 0U4587#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4588 4589/* Register ROGUE_CR_RASTERISATION_PERF_COUNTER_0 */4590#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0 0x7750U4591#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4592#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_SHIFT 0U4593#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4594 4595/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF */4596#define ROGUE_CR_HUB_BIFPMCACHE_PERF 0x7800U4597#define ROGUE_CR_HUB_BIFPMCACHE_PERF_MASKFULL 0x000000000000001FULL4598#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_SHIFT 4U4599#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4600#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_EN 0x00000010U4601#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_SHIFT 3U4602#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4603#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_EN 0x00000008U4604#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_SHIFT 2U4605#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4606#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_EN 0x00000004U4607#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_SHIFT 1U4608#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4609#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_EN 0x00000002U4610#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_SHIFT 0U4611#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4612#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_EN 0x00000001U4613 4614/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 */4615#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 0x7808U4616#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4617#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_SHIFT 48U4618#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4619#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_SHIFT 32U4620#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4621#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_SHIFT 21U4622#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4623#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4624#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4625#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4626#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_SHIFT 0U4627#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4628 4629/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 */4630#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 0x7850U4631#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4632#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_SHIFT 0U4633#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4634 4635/* Register ROGUE_CR_TPU_MCU_L0_PERF */4636#define ROGUE_CR_TPU_MCU_L0_PERF 0x7900U4637#define ROGUE_CR_TPU_MCU_L0_PERF_MASKFULL 0x000000000000001FULL4638#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_SHIFT 4U4639#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4640#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_EN 0x00000010U4641#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_SHIFT 3U4642#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4643#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_EN 0x00000008U4644#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_SHIFT 2U4645#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4646#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_EN 0x00000004U4647#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_SHIFT 1U4648#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4649#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_EN 0x00000002U4650#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_SHIFT 0U4651#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4652#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_EN 0x00000001U4653 4654/* Register ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 */4655#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 0x7908U4656#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4657#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_SHIFT 48U4658#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4659#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_SHIFT 32U4660#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4661#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_SHIFT 21U4662#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4663#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4664#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4665#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4666#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_SHIFT 0U4667#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4668 4669/* Register ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 */4670#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 0x7950U4671#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4672#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_SHIFT 0U4673#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4674 4675/* Register ROGUE_CR_USC_PERF */4676#define ROGUE_CR_USC_PERF 0x8100U4677#define ROGUE_CR_USC_PERF_MASKFULL 0x000000000000001FULL4678#define ROGUE_CR_USC_PERF_CLR_3_SHIFT 4U4679#define ROGUE_CR_USC_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4680#define ROGUE_CR_USC_PERF_CLR_3_EN 0x00000010U4681#define ROGUE_CR_USC_PERF_CLR_2_SHIFT 3U4682#define ROGUE_CR_USC_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4683#define ROGUE_CR_USC_PERF_CLR_2_EN 0x00000008U4684#define ROGUE_CR_USC_PERF_CLR_1_SHIFT 2U4685#define ROGUE_CR_USC_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4686#define ROGUE_CR_USC_PERF_CLR_1_EN 0x00000004U4687#define ROGUE_CR_USC_PERF_CLR_0_SHIFT 1U4688#define ROGUE_CR_USC_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4689#define ROGUE_CR_USC_PERF_CLR_0_EN 0x00000002U4690#define ROGUE_CR_USC_PERF_CTRL_ENABLE_SHIFT 0U4691#define ROGUE_CR_USC_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4692#define ROGUE_CR_USC_PERF_CTRL_ENABLE_EN 0x00000001U4693 4694/* Register ROGUE_CR_USC_PERF_SELECT0 */4695#define ROGUE_CR_USC_PERF_SELECT0 0x8108U4696#define ROGUE_CR_USC_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4697#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_SHIFT 48U4698#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4699#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_SHIFT 32U4700#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4701#define ROGUE_CR_USC_PERF_SELECT0_MODE_SHIFT 21U4702#define ROGUE_CR_USC_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4703#define ROGUE_CR_USC_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4704#define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4705#define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4706#define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_SHIFT 0U4707#define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4708 4709/* Register ROGUE_CR_USC_PERF_COUNTER_0 */4710#define ROGUE_CR_USC_PERF_COUNTER_0 0x8150U4711#define ROGUE_CR_USC_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4712#define ROGUE_CR_USC_PERF_COUNTER_0_REG_SHIFT 0U4713#define ROGUE_CR_USC_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4714 4715/* Register ROGUE_CR_JONES_IDLE */4716#define ROGUE_CR_JONES_IDLE 0x8328U4717#define ROGUE_CR_JONES_IDLE_MASKFULL 0x0000000000007FFFULL4718#define ROGUE_CR_JONES_IDLE_TDM_SHIFT 14U4719#define ROGUE_CR_JONES_IDLE_TDM_CLRMSK 0xFFFFBFFFU4720#define ROGUE_CR_JONES_IDLE_TDM_EN 0x00004000U4721#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_SHIFT 13U4722#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_CLRMSK 0xFFFFDFFFU4723#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_EN 0x00002000U4724#define ROGUE_CR_JONES_IDLE_FB_CDC_SHIFT 12U4725#define ROGUE_CR_JONES_IDLE_FB_CDC_CLRMSK 0xFFFFEFFFU4726#define ROGUE_CR_JONES_IDLE_FB_CDC_EN 0x00001000U4727#define ROGUE_CR_JONES_IDLE_MMU_SHIFT 11U4728#define ROGUE_CR_JONES_IDLE_MMU_CLRMSK 0xFFFFF7FFU4729#define ROGUE_CR_JONES_IDLE_MMU_EN 0x00000800U4730#define ROGUE_CR_JONES_IDLE_TLA_SHIFT 10U4731#define ROGUE_CR_JONES_IDLE_TLA_CLRMSK 0xFFFFFBFFU4732#define ROGUE_CR_JONES_IDLE_TLA_EN 0x00000400U4733#define ROGUE_CR_JONES_IDLE_GARTEN_SHIFT 9U4734#define ROGUE_CR_JONES_IDLE_GARTEN_CLRMSK 0xFFFFFDFFU4735#define ROGUE_CR_JONES_IDLE_GARTEN_EN 0x00000200U4736#define ROGUE_CR_JONES_IDLE_HOSTIF_SHIFT 8U4737#define ROGUE_CR_JONES_IDLE_HOSTIF_CLRMSK 0xFFFFFEFFU4738#define ROGUE_CR_JONES_IDLE_HOSTIF_EN 0x00000100U4739#define ROGUE_CR_JONES_IDLE_SOCIF_SHIFT 7U4740#define ROGUE_CR_JONES_IDLE_SOCIF_CLRMSK 0xFFFFFF7FU4741#define ROGUE_CR_JONES_IDLE_SOCIF_EN 0x00000080U4742#define ROGUE_CR_JONES_IDLE_TILING_SHIFT 6U4743#define ROGUE_CR_JONES_IDLE_TILING_CLRMSK 0xFFFFFFBFU4744#define ROGUE_CR_JONES_IDLE_TILING_EN 0x00000040U4745#define ROGUE_CR_JONES_IDLE_IPP_SHIFT 5U4746#define ROGUE_CR_JONES_IDLE_IPP_CLRMSK 0xFFFFFFDFU4747#define ROGUE_CR_JONES_IDLE_IPP_EN 0x00000020U4748#define ROGUE_CR_JONES_IDLE_USCS_SHIFT 4U4749#define ROGUE_CR_JONES_IDLE_USCS_CLRMSK 0xFFFFFFEFU4750#define ROGUE_CR_JONES_IDLE_USCS_EN 0x00000010U4751#define ROGUE_CR_JONES_IDLE_PM_SHIFT 3U4752#define ROGUE_CR_JONES_IDLE_PM_CLRMSK 0xFFFFFFF7U4753#define ROGUE_CR_JONES_IDLE_PM_EN 0x00000008U4754#define ROGUE_CR_JONES_IDLE_CDM_SHIFT 2U4755#define ROGUE_CR_JONES_IDLE_CDM_CLRMSK 0xFFFFFFFBU4756#define ROGUE_CR_JONES_IDLE_CDM_EN 0x00000004U4757#define ROGUE_CR_JONES_IDLE_VDM_SHIFT 1U4758#define ROGUE_CR_JONES_IDLE_VDM_CLRMSK 0xFFFFFFFDU4759#define ROGUE_CR_JONES_IDLE_VDM_EN 0x00000002U4760#define ROGUE_CR_JONES_IDLE_BIF_SHIFT 0U4761#define ROGUE_CR_JONES_IDLE_BIF_CLRMSK 0xFFFFFFFEU4762#define ROGUE_CR_JONES_IDLE_BIF_EN 0x00000001U4763 4764/* Register ROGUE_CR_TORNADO_PERF */4765#define ROGUE_CR_TORNADO_PERF 0x8228U4766#define ROGUE_CR_TORNADO_PERF_MASKFULL 0x000000000000001FULL4767#define ROGUE_CR_TORNADO_PERF_CLR_3_SHIFT 4U4768#define ROGUE_CR_TORNADO_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4769#define ROGUE_CR_TORNADO_PERF_CLR_3_EN 0x00000010U4770#define ROGUE_CR_TORNADO_PERF_CLR_2_SHIFT 3U4771#define ROGUE_CR_TORNADO_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4772#define ROGUE_CR_TORNADO_PERF_CLR_2_EN 0x00000008U4773#define ROGUE_CR_TORNADO_PERF_CLR_1_SHIFT 2U4774#define ROGUE_CR_TORNADO_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4775#define ROGUE_CR_TORNADO_PERF_CLR_1_EN 0x00000004U4776#define ROGUE_CR_TORNADO_PERF_CLR_0_SHIFT 1U4777#define ROGUE_CR_TORNADO_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4778#define ROGUE_CR_TORNADO_PERF_CLR_0_EN 0x00000002U4779#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_SHIFT 0U4780#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4781#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_EN 0x00000001U4782 4783/* Register ROGUE_CR_TORNADO_PERF_SELECT0 */4784#define ROGUE_CR_TORNADO_PERF_SELECT0 0x8230U4785#define ROGUE_CR_TORNADO_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4786#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_SHIFT 48U4787#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4788#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_SHIFT 32U4789#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4790#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_SHIFT 21U4791#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4792#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4793#define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4794#define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4795#define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_SHIFT 0U4796#define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4797 4798/* Register ROGUE_CR_TORNADO_PERF_COUNTER_0 */4799#define ROGUE_CR_TORNADO_PERF_COUNTER_0 0x8268U4800#define ROGUE_CR_TORNADO_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4801#define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_SHIFT 0U4802#define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4803 4804/* Register ROGUE_CR_TEXAS_PERF */4805#define ROGUE_CR_TEXAS_PERF 0x8290U4806#define ROGUE_CR_TEXAS_PERF_MASKFULL 0x000000000000007FULL4807#define ROGUE_CR_TEXAS_PERF_CLR_5_SHIFT 6U4808#define ROGUE_CR_TEXAS_PERF_CLR_5_CLRMSK 0xFFFFFFBFU4809#define ROGUE_CR_TEXAS_PERF_CLR_5_EN 0x00000040U4810#define ROGUE_CR_TEXAS_PERF_CLR_4_SHIFT 5U4811#define ROGUE_CR_TEXAS_PERF_CLR_4_CLRMSK 0xFFFFFFDFU4812#define ROGUE_CR_TEXAS_PERF_CLR_4_EN 0x00000020U4813#define ROGUE_CR_TEXAS_PERF_CLR_3_SHIFT 4U4814#define ROGUE_CR_TEXAS_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4815#define ROGUE_CR_TEXAS_PERF_CLR_3_EN 0x00000010U4816#define ROGUE_CR_TEXAS_PERF_CLR_2_SHIFT 3U4817#define ROGUE_CR_TEXAS_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4818#define ROGUE_CR_TEXAS_PERF_CLR_2_EN 0x00000008U4819#define ROGUE_CR_TEXAS_PERF_CLR_1_SHIFT 2U4820#define ROGUE_CR_TEXAS_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4821#define ROGUE_CR_TEXAS_PERF_CLR_1_EN 0x00000004U4822#define ROGUE_CR_TEXAS_PERF_CLR_0_SHIFT 1U4823#define ROGUE_CR_TEXAS_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4824#define ROGUE_CR_TEXAS_PERF_CLR_0_EN 0x00000002U4825#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_SHIFT 0U4826#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4827#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_EN 0x00000001U4828 4829/* Register ROGUE_CR_TEXAS_PERF_SELECT0 */4830#define ROGUE_CR_TEXAS_PERF_SELECT0 0x8298U4831#define ROGUE_CR_TEXAS_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL4832#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_SHIFT 48U4833#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4834#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_SHIFT 32U4835#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4836#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_SHIFT 31U4837#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL4838#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_EN 0x0000000080000000ULL4839#define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4840#define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL4841#define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_SHIFT 0U4842#define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4843 4844/* Register ROGUE_CR_TEXAS_PERF_COUNTER_0 */4845#define ROGUE_CR_TEXAS_PERF_COUNTER_0 0x82D8U4846#define ROGUE_CR_TEXAS_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4847#define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_SHIFT 0U4848#define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4849 4850/* Register ROGUE_CR_JONES_PERF */4851#define ROGUE_CR_JONES_PERF 0x8330U4852#define ROGUE_CR_JONES_PERF_MASKFULL 0x000000000000001FULL4853#define ROGUE_CR_JONES_PERF_CLR_3_SHIFT 4U4854#define ROGUE_CR_JONES_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4855#define ROGUE_CR_JONES_PERF_CLR_3_EN 0x00000010U4856#define ROGUE_CR_JONES_PERF_CLR_2_SHIFT 3U4857#define ROGUE_CR_JONES_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4858#define ROGUE_CR_JONES_PERF_CLR_2_EN 0x00000008U4859#define ROGUE_CR_JONES_PERF_CLR_1_SHIFT 2U4860#define ROGUE_CR_JONES_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4861#define ROGUE_CR_JONES_PERF_CLR_1_EN 0x00000004U4862#define ROGUE_CR_JONES_PERF_CLR_0_SHIFT 1U4863#define ROGUE_CR_JONES_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4864#define ROGUE_CR_JONES_PERF_CLR_0_EN 0x00000002U4865#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_SHIFT 0U4866#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4867#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_EN 0x00000001U4868 4869/* Register ROGUE_CR_JONES_PERF_SELECT0 */4870#define ROGUE_CR_JONES_PERF_SELECT0 0x8338U4871#define ROGUE_CR_JONES_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4872#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_SHIFT 48U4873#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4874#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_SHIFT 32U4875#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4876#define ROGUE_CR_JONES_PERF_SELECT0_MODE_SHIFT 21U4877#define ROGUE_CR_JONES_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4878#define ROGUE_CR_JONES_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4879#define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4880#define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4881#define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_SHIFT 0U4882#define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4883 4884/* Register ROGUE_CR_JONES_PERF_COUNTER_0 */4885#define ROGUE_CR_JONES_PERF_COUNTER_0 0x8368U4886#define ROGUE_CR_JONES_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4887#define ROGUE_CR_JONES_PERF_COUNTER_0_REG_SHIFT 0U4888#define ROGUE_CR_JONES_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4889 4890/* Register ROGUE_CR_BLACKPEARL_PERF */4891#define ROGUE_CR_BLACKPEARL_PERF 0x8400U4892#define ROGUE_CR_BLACKPEARL_PERF_MASKFULL 0x000000000000007FULL4893#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_SHIFT 6U4894#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_CLRMSK 0xFFFFFFBFU4895#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_EN 0x00000040U4896#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_SHIFT 5U4897#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_CLRMSK 0xFFFFFFDFU4898#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_EN 0x00000020U4899#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_SHIFT 4U4900#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4901#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_EN 0x00000010U4902#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_SHIFT 3U4903#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4904#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_EN 0x00000008U4905#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_SHIFT 2U4906#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4907#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_EN 0x00000004U4908#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_SHIFT 1U4909#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4910#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_EN 0x00000002U4911#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_SHIFT 0U4912#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4913#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_EN 0x00000001U4914 4915/* Register ROGUE_CR_BLACKPEARL_PERF_SELECT0 */4916#define ROGUE_CR_BLACKPEARL_PERF_SELECT0 0x8408U4917#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL4918#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_SHIFT 48U4919#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4920#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_SHIFT 32U4921#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4922#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_SHIFT 31U4923#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL4924#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_EN 0x0000000080000000ULL4925#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4926#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL4927#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_SHIFT 0U4928#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4929 4930/* Register ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 */4931#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 0x8448U4932#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4933#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_SHIFT 0U4934#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4935 4936/* Register ROGUE_CR_PBE_PERF */4937#define ROGUE_CR_PBE_PERF 0x8478U4938#define ROGUE_CR_PBE_PERF_MASKFULL 0x000000000000001FULL4939#define ROGUE_CR_PBE_PERF_CLR_3_SHIFT 4U4940#define ROGUE_CR_PBE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU4941#define ROGUE_CR_PBE_PERF_CLR_3_EN 0x00000010U4942#define ROGUE_CR_PBE_PERF_CLR_2_SHIFT 3U4943#define ROGUE_CR_PBE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U4944#define ROGUE_CR_PBE_PERF_CLR_2_EN 0x00000008U4945#define ROGUE_CR_PBE_PERF_CLR_1_SHIFT 2U4946#define ROGUE_CR_PBE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU4947#define ROGUE_CR_PBE_PERF_CLR_1_EN 0x00000004U4948#define ROGUE_CR_PBE_PERF_CLR_0_SHIFT 1U4949#define ROGUE_CR_PBE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU4950#define ROGUE_CR_PBE_PERF_CLR_0_EN 0x00000002U4951#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_SHIFT 0U4952#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU4953#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_EN 0x00000001U4954 4955/* Register ROGUE_CR_PBE_PERF_SELECT0 */4956#define ROGUE_CR_PBE_PERF_SELECT0 0x8480U4957#define ROGUE_CR_PBE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL4958#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_SHIFT 48U4959#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL4960#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_SHIFT 32U4961#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL4962#define ROGUE_CR_PBE_PERF_SELECT0_MODE_SHIFT 21U4963#define ROGUE_CR_PBE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL4964#define ROGUE_CR_PBE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL4965#define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U4966#define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL4967#define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_SHIFT 0U4968#define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL4969 4970/* Register ROGUE_CR_PBE_PERF_COUNTER_0 */4971#define ROGUE_CR_PBE_PERF_COUNTER_0 0x84B0U4972#define ROGUE_CR_PBE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL4973#define ROGUE_CR_PBE_PERF_COUNTER_0_REG_SHIFT 0U4974#define ROGUE_CR_PBE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U4975 4976/* Register ROGUE_CR_OCP_REVINFO */4977#define ROGUE_CR_OCP_REVINFO 0x9000U4978#define ROGUE_CR_OCP_REVINFO_MASKFULL 0x00000007FFFFFFFFULL4979#define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_SHIFT 33U4980#define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_CLRMSK 0xFFFFFFF9FFFFFFFFULL4981#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_SHIFT 32U4982#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_CLRMSK 0xFFFFFFFEFFFFFFFFULL4983#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_EN 0x0000000100000000ULL4984#define ROGUE_CR_OCP_REVINFO_REVISION_SHIFT 0U4985#define ROGUE_CR_OCP_REVINFO_REVISION_CLRMSK 0xFFFFFFFF00000000ULL4986 4987/* Register ROGUE_CR_OCP_SYSCONFIG */4988#define ROGUE_CR_OCP_SYSCONFIG 0x9010U4989#define ROGUE_CR_OCP_SYSCONFIG_MASKFULL 0x0000000000000FFFULL4990#define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_SHIFT 10U4991#define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_CLRMSK 0xFFFFF3FFU4992#define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_SHIFT 8U4993#define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_CLRMSK 0xFFFFFCFFU4994#define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_SHIFT 6U4995#define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_CLRMSK 0xFFFFFF3FU4996#define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_SHIFT 4U4997#define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_CLRMSK 0xFFFFFFCFU4998#define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 2U4999#define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_CLRMSK 0xFFFFFFF3U5000#define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 0U5001#define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_CLRMSK 0xFFFFFFFCU5002 5003/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_0 */5004#define ROGUE_CR_OCP_IRQSTATUS_RAW_0 0x9020U5005#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_MASKFULL 0x0000000000000001ULL5006#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT 0U5007#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU5008#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_EN 0x00000001U5009 5010/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_1 */5011#define ROGUE_CR_OCP_IRQSTATUS_RAW_1 0x9028U5012#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_MASKFULL 0x0000000000000001ULL5013#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT 0U5014#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU5015#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_EN 0x00000001U5016 5017/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_2 */5018#define ROGUE_CR_OCP_IRQSTATUS_RAW_2 0x9030U5019#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_MASKFULL 0x0000000000000001ULL5020#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_SHIFT 0U5021#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_CLRMSK 0xFFFFFFFEU5022#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_EN 0x00000001U5023 5024/* Register ROGUE_CR_OCP_IRQSTATUS_0 */5025#define ROGUE_CR_OCP_IRQSTATUS_0 0x9038U5026#define ROGUE_CR_OCP_IRQSTATUS_0_MASKFULL 0x0000000000000001ULL5027#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT 0U5028#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU5029#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_EN 0x00000001U5030 5031/* Register ROGUE_CR_OCP_IRQSTATUS_1 */5032#define ROGUE_CR_OCP_IRQSTATUS_1 0x9040U5033#define ROGUE_CR_OCP_IRQSTATUS_1_MASKFULL 0x0000000000000001ULL5034#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT 0U5035#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU5036#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_EN 0x00000001U5037 5038/* Register ROGUE_CR_OCP_IRQSTATUS_2 */5039#define ROGUE_CR_OCP_IRQSTATUS_2 0x9048U5040#define ROGUE_CR_OCP_IRQSTATUS_2_MASKFULL 0x0000000000000001ULL5041#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_SHIFT 0U5042#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_CLRMSK 0xFFFFFFFEU5043#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_EN 0x00000001U5044 5045/* Register ROGUE_CR_OCP_IRQENABLE_SET_0 */5046#define ROGUE_CR_OCP_IRQENABLE_SET_0 0x9050U5047#define ROGUE_CR_OCP_IRQENABLE_SET_0_MASKFULL 0x0000000000000001ULL5048#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT 0U5049#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU5050#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_EN 0x00000001U5051 5052/* Register ROGUE_CR_OCP_IRQENABLE_SET_1 */5053#define ROGUE_CR_OCP_IRQENABLE_SET_1 0x9058U5054#define ROGUE_CR_OCP_IRQENABLE_SET_1_MASKFULL 0x0000000000000001ULL5055#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT 0U5056#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU5057#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_EN 0x00000001U5058 5059/* Register ROGUE_CR_OCP_IRQENABLE_SET_2 */5060#define ROGUE_CR_OCP_IRQENABLE_SET_2 0x9060U5061#define ROGUE_CR_OCP_IRQENABLE_SET_2_MASKFULL 0x0000000000000001ULL5062#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_SHIFT 0U5063#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_CLRMSK 0xFFFFFFFEU5064#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_EN 0x00000001U5065 5066/* Register ROGUE_CR_OCP_IRQENABLE_CLR_0 */5067#define ROGUE_CR_OCP_IRQENABLE_CLR_0 0x9068U5068#define ROGUE_CR_OCP_IRQENABLE_CLR_0_MASKFULL 0x0000000000000001ULL5069#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT 0U5070#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU5071#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_EN 0x00000001U5072 5073/* Register ROGUE_CR_OCP_IRQENABLE_CLR_1 */5074#define ROGUE_CR_OCP_IRQENABLE_CLR_1 0x9070U5075#define ROGUE_CR_OCP_IRQENABLE_CLR_1_MASKFULL 0x0000000000000001ULL5076#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT 0U5077#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU5078#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_EN 0x00000001U5079 5080/* Register ROGUE_CR_OCP_IRQENABLE_CLR_2 */5081#define ROGUE_CR_OCP_IRQENABLE_CLR_2 0x9078U5082#define ROGUE_CR_OCP_IRQENABLE_CLR_2_MASKFULL 0x0000000000000001ULL5083#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_SHIFT 0U5084#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_CLRMSK 0xFFFFFFFEU5085#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_EN 0x00000001U5086 5087/* Register ROGUE_CR_OCP_IRQ_EVENT */5088#define ROGUE_CR_OCP_IRQ_EVENT 0x9080U5089#define ROGUE_CR_OCP_IRQ_EVENT_MASKFULL 0x00000000000FFFFFULL5090#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_SHIFT 19U5091#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFF7FFFFULL5092#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_EN 0x0000000000080000ULL5093#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_SHIFT 18U5094#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFBFFFFULL5095#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000040000ULL5096#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_SHIFT 17U5097#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFFDFFFFULL5098#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_EN 0x0000000000020000ULL5099#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_SHIFT 16U5100#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFEFFFFULL5101#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000010000ULL5102#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_SHIFT 15U5103#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFF7FFFULL5104#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000008000ULL5105#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_SHIFT 14U5106#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFBFFFULL5107#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_EN 0x0000000000004000ULL5108#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_SHIFT 13U5109#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFDFFFULL5110#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_EN 0x0000000000002000ULL5111#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_SHIFT 12U5112#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFEFFFULL5113#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_EN 0x0000000000001000ULL5114#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_SHIFT 11U5115#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFF7FFULL5116#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000800ULL5117#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_SHIFT 10U5118#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFBFFULL5119#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_EN 0x0000000000000400ULL5120#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_SHIFT 9U5121#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFDFFULL5122#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_EN 0x0000000000000200ULL5123#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_SHIFT 8U5124#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFEFFULL5125#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_EN 0x0000000000000100ULL5126#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_SHIFT 7U5127#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFF7FULL5128#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000080ULL5129#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_SHIFT 6U5130#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFBFULL5131#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_EN 0x0000000000000040ULL5132#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_SHIFT 5U5133#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFDFULL5134#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_EN 0x0000000000000020ULL5135#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_SHIFT 4U5136#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFEFULL5137#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_EN 0x0000000000000010ULL5138#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_SHIFT 3U5139#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFFF7ULL5140#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000008ULL5141#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_SHIFT 2U5142#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFFBULL5143#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_EN 0x0000000000000004ULL5144#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_SHIFT 1U5145#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFFDULL5146#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_EN 0x0000000000000002ULL5147#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_SHIFT 0U5148#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFFEULL5149#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_EN 0x0000000000000001ULL5150 5151/* Register ROGUE_CR_OCP_DEBUG_CONFIG */5152#define ROGUE_CR_OCP_DEBUG_CONFIG 0x9088U5153#define ROGUE_CR_OCP_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL5154#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_SHIFT 0U5155#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_CLRMSK 0xFFFFFFFEU5156#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_EN 0x00000001U5157 5158/* Register ROGUE_CR_OCP_DEBUG_STATUS */5159#define ROGUE_CR_OCP_DEBUG_STATUS 0x9090U5160#define ROGUE_CR_OCP_DEBUG_STATUS_MASKFULL 0x001F1F77FFFFFFFFULL5161#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_SHIFT 51U5162#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_CLRMSK 0xFFE7FFFFFFFFFFFFULL5163#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_SHIFT 50U5164#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_CLRMSK 0xFFFBFFFFFFFFFFFFULL5165#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_EN 0x0004000000000000ULL5166#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_SHIFT 48U5167#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_CLRMSK 0xFFFCFFFFFFFFFFFFULL5168#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_SHIFT 43U5169#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_CLRMSK 0xFFFFE7FFFFFFFFFFULL5170#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_SHIFT 42U5171#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_CLRMSK 0xFFFFFBFFFFFFFFFFULL5172#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_EN 0x0000040000000000ULL5173#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_SHIFT 40U5174#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_CLRMSK 0xFFFFFCFFFFFFFFFFULL5175#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_SHIFT 38U5176#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_CLRMSK 0xFFFFFFBFFFFFFFFFULL5177#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_EN 0x0000004000000000ULL5178#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_SHIFT 37U5179#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_CLRMSK 0xFFFFFFDFFFFFFFFFULL5180#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_EN 0x0000002000000000ULL5181#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_SHIFT 36U5182#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_CLRMSK 0xFFFFFFEFFFFFFFFFULL5183#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_EN 0x0000001000000000ULL5184#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_SHIFT 34U5185#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_CLRMSK 0xFFFFFFFBFFFFFFFFULL5186#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_EN 0x0000000400000000ULL5187#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_SHIFT 33U5188#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_CLRMSK 0xFFFFFFFDFFFFFFFFULL5189#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_EN 0x0000000200000000ULL5190#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_SHIFT 32U5191#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_CLRMSK 0xFFFFFFFEFFFFFFFFULL5192#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_EN 0x0000000100000000ULL5193#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_SHIFT 31U5194#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_CLRMSK 0xFFFFFFFF7FFFFFFFULL5195#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_EN 0x0000000080000000ULL5196#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_SHIFT 30U5197#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_CLRMSK 0xFFFFFFFFBFFFFFFFULL5198#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_EN 0x0000000040000000ULL5199#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_SHIFT 29U5200#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_CLRMSK 0xFFFFFFFFDFFFFFFFULL5201#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_EN 0x0000000020000000ULL5202#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_SHIFT 27U5203#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_CLRMSK 0xFFFFFFFFE7FFFFFFULL5204#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_SHIFT 26U5205#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_CLRMSK 0xFFFFFFFFFBFFFFFFULL5206#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_EN 0x0000000004000000ULL5207#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_SHIFT 24U5208#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_CLRMSK 0xFFFFFFFFFCFFFFFFULL5209#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_SHIFT 23U5210#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_CLRMSK 0xFFFFFFFFFF7FFFFFULL5211#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_EN 0x0000000000800000ULL5212#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_SHIFT 22U5213#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_CLRMSK 0xFFFFFFFFFFBFFFFFULL5214#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_EN 0x0000000000400000ULL5215#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_SHIFT 21U5216#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_CLRMSK 0xFFFFFFFFFFDFFFFFULL5217#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_EN 0x0000000000200000ULL5218#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_SHIFT 19U5219#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_CLRMSK 0xFFFFFFFFFFE7FFFFULL5220#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_SHIFT 18U5221#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_CLRMSK 0xFFFFFFFFFFFBFFFFULL5222#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_EN 0x0000000000040000ULL5223#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_SHIFT 16U5224#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_CLRMSK 0xFFFFFFFFFFFCFFFFULL5225#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_SHIFT 15U5226#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_CLRMSK 0xFFFFFFFFFFFF7FFFULL5227#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_EN 0x0000000000008000ULL5228#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_SHIFT 14U5229#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_CLRMSK 0xFFFFFFFFFFFFBFFFULL5230#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_EN 0x0000000000004000ULL5231#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_SHIFT 13U5232#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFDFFFULL5233#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_EN 0x0000000000002000ULL5234#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_SHIFT 11U5235#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_CLRMSK 0xFFFFFFFFFFFFE7FFULL5236#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_SHIFT 10U5237#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFBFFULL5238#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_EN 0x0000000000000400ULL5239#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_SHIFT 8U5240#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFCFFULL5241#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_SHIFT 7U5242#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_CLRMSK 0xFFFFFFFFFFFFFF7FULL5243#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_EN 0x0000000000000080ULL5244#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_SHIFT 6U5245#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_CLRMSK 0xFFFFFFFFFFFFFFBFULL5246#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_EN 0x0000000000000040ULL5247#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_SHIFT 5U5248#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFFFDFULL5249#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_EN 0x0000000000000020ULL5250#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_SHIFT 3U5251#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_CLRMSK 0xFFFFFFFFFFFFFFE7ULL5252#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_SHIFT 2U5253#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFBULL5254#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_EN 0x0000000000000004ULL5255#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_SHIFT 0U5256#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFCULL5257 5258#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_SHIFT 6U5259#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_CLRMSK 0xFFFFFFBFU5260#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_EN 0x00000040U5261#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_SHIFT 5U5262#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_CLRMSK 0xFFFFFFDFU5263#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_EN 0x00000020U5264#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_SHIFT 4U5265#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_CLRMSK 0xFFFFFFEFU5266#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_EN 0x00000010U5267#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_SHIFT 3U5268#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_CLRMSK 0xFFFFFFF7U5269#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_EN 0x00000008U5270#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_SHIFT 2U5271#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_CLRMSK 0xFFFFFFFBU5272#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_EN 0x00000004U5273#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_SHIFT 1U5274#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_CLRMSK 0xFFFFFFFDU5275#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_EN 0x00000002U5276#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_SHIFT 0U5277#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_CLRMSK 0xFFFFFFFEU5278#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_EN 0x00000001U5279 5280#define ROGUE_CR_BIF_TRUST_DM_MASK 0x0000007FU5281 5282/* Register ROGUE_CR_BIF_TRUST */5283#define ROGUE_CR_BIF_TRUST 0xA000U5284#define ROGUE_CR_BIF_TRUST_MASKFULL 0x00000000001FFFFFULL5285#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_SHIFT 20U5286#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFEFFFFFU5287#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_EN 0x00100000U5288#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_SHIFT 19U5289#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFF7FFFFU5290#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_EN 0x00080000U5291#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_SHIFT 18U5292#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_CLRMSK 0xFFFBFFFFU5293#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_EN 0x00040000U5294#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_SHIFT 17U5295#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_CLRMSK 0xFFFDFFFFU5296#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_EN 0x00020000U5297#define ROGUE_CR_BIF_TRUST_ENABLE_SHIFT 16U5298#define ROGUE_CR_BIF_TRUST_ENABLE_CLRMSK 0xFFFEFFFFU5299#define ROGUE_CR_BIF_TRUST_ENABLE_EN 0x00010000U5300#define ROGUE_CR_BIF_TRUST_DM_TRUSTED_SHIFT 9U5301#define ROGUE_CR_BIF_TRUST_DM_TRUSTED_CLRMSK 0xFFFF01FFU5302#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_SHIFT 8U5303#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFEFFU5304#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_EN 0x00000100U5305#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_SHIFT 7U5306#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFF7FU5307#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_EN 0x00000080U5308#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_SHIFT 6U5309#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFFBFU5310#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_EN 0x00000040U5311#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_SHIFT 5U5312#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFDFU5313#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_EN 0x00000020U5314#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_SHIFT 4U5315#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFEFU5316#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_EN 0x00000010U5317#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_SHIFT 3U5318#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFF7U5319#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_EN 0x00000008U5320#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_SHIFT 2U5321#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFBU5322#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_EN 0x00000004U5323#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_SHIFT 1U5324#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFDU5325#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_EN 0x00000002U5326#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_SHIFT 0U5327#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFEU5328#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_EN 0x00000001U5329 5330/* Register ROGUE_CR_SYS_BUS_SECURE */5331#define ROGUE_CR_SYS_BUS_SECURE 0xA100U5332#define ROGUE_CR_SYS_BUS_SECURE__SECR__MASKFULL 0x0000000000000001ULL5333#define ROGUE_CR_SYS_BUS_SECURE_MASKFULL 0x0000000000000001ULL5334#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_SHIFT 0U5335#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_CLRMSK 0xFFFFFFFEU5336#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_EN 0x00000001U5337 5338/* Register ROGUE_CR_FBA_FC0_CHECKSUM */5339#define ROGUE_CR_FBA_FC0_CHECKSUM 0xD170U5340#define ROGUE_CR_FBA_FC0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5341#define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_SHIFT 0U5342#define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_CLRMSK 0x00000000U5343 5344/* Register ROGUE_CR_FBA_FC1_CHECKSUM */5345#define ROGUE_CR_FBA_FC1_CHECKSUM 0xD178U5346#define ROGUE_CR_FBA_FC1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5347#define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_SHIFT 0U5348#define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_CLRMSK 0x00000000U5349 5350/* Register ROGUE_CR_FBA_FC2_CHECKSUM */5351#define ROGUE_CR_FBA_FC2_CHECKSUM 0xD180U5352#define ROGUE_CR_FBA_FC2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5353#define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_SHIFT 0U5354#define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_CLRMSK 0x00000000U5355 5356/* Register ROGUE_CR_FBA_FC3_CHECKSUM */5357#define ROGUE_CR_FBA_FC3_CHECKSUM 0xD188U5358#define ROGUE_CR_FBA_FC3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5359#define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_SHIFT 0U5360#define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_CLRMSK 0x00000000U5361 5362/* Register ROGUE_CR_CLK_CTRL2 */5363#define ROGUE_CR_CLK_CTRL2 0xD200U5364#define ROGUE_CR_CLK_CTRL2_MASKFULL 0x0000000000000F33ULL5365#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_SHIFT 10U5366#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_CLRMSK 0xFFFFFFFFFFFFF3FFULL5367#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_OFF 0x0000000000000000ULL5368#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_ON 0x0000000000000400ULL5369#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_AUTO 0x0000000000000800ULL5370#define ROGUE_CR_CLK_CTRL2_VRDM_SHIFT 8U5371#define ROGUE_CR_CLK_CTRL2_VRDM_CLRMSK 0xFFFFFFFFFFFFFCFFULL5372#define ROGUE_CR_CLK_CTRL2_VRDM_OFF 0x0000000000000000ULL5373#define ROGUE_CR_CLK_CTRL2_VRDM_ON 0x0000000000000100ULL5374#define ROGUE_CR_CLK_CTRL2_VRDM_AUTO 0x0000000000000200ULL5375#define ROGUE_CR_CLK_CTRL2_SH_SHIFT 4U5376#define ROGUE_CR_CLK_CTRL2_SH_CLRMSK 0xFFFFFFFFFFFFFFCFULL5377#define ROGUE_CR_CLK_CTRL2_SH_OFF 0x0000000000000000ULL5378#define ROGUE_CR_CLK_CTRL2_SH_ON 0x0000000000000010ULL5379#define ROGUE_CR_CLK_CTRL2_SH_AUTO 0x0000000000000020ULL5380#define ROGUE_CR_CLK_CTRL2_FBA_SHIFT 0U5381#define ROGUE_CR_CLK_CTRL2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFCULL5382#define ROGUE_CR_CLK_CTRL2_FBA_OFF 0x0000000000000000ULL5383#define ROGUE_CR_CLK_CTRL2_FBA_ON 0x0000000000000001ULL5384#define ROGUE_CR_CLK_CTRL2_FBA_AUTO 0x0000000000000002ULL5385 5386/* Register ROGUE_CR_CLK_STATUS2 */5387#define ROGUE_CR_CLK_STATUS2 0xD208U5388#define ROGUE_CR_CLK_STATUS2_MASKFULL 0x0000000000000015ULL5389#define ROGUE_CR_CLK_STATUS2_VRDM_SHIFT 4U5390#define ROGUE_CR_CLK_STATUS2_VRDM_CLRMSK 0xFFFFFFFFFFFFFFEFULL5391#define ROGUE_CR_CLK_STATUS2_VRDM_GATED 0x0000000000000000ULL5392#define ROGUE_CR_CLK_STATUS2_VRDM_RUNNING 0x0000000000000010ULL5393#define ROGUE_CR_CLK_STATUS2_SH_SHIFT 2U5394#define ROGUE_CR_CLK_STATUS2_SH_CLRMSK 0xFFFFFFFFFFFFFFFBULL5395#define ROGUE_CR_CLK_STATUS2_SH_GATED 0x0000000000000000ULL5396#define ROGUE_CR_CLK_STATUS2_SH_RUNNING 0x0000000000000004ULL5397#define ROGUE_CR_CLK_STATUS2_FBA_SHIFT 0U5398#define ROGUE_CR_CLK_STATUS2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFEULL5399#define ROGUE_CR_CLK_STATUS2_FBA_GATED 0x0000000000000000ULL5400#define ROGUE_CR_CLK_STATUS2_FBA_RUNNING 0x0000000000000001ULL5401 5402/* Register ROGUE_CR_RPM_SHF_FPL */5403#define ROGUE_CR_RPM_SHF_FPL 0xD520U5404#define ROGUE_CR_RPM_SHF_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL5405#define ROGUE_CR_RPM_SHF_FPL_SIZE_SHIFT 40U5406#define ROGUE_CR_RPM_SHF_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL5407#define ROGUE_CR_RPM_SHF_FPL_BASE_SHIFT 2U5408#define ROGUE_CR_RPM_SHF_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL5409#define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSHIFT 2U5410#define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSIZE 4U5411 5412/* Register ROGUE_CR_RPM_SHF_FPL_READ */5413#define ROGUE_CR_RPM_SHF_FPL_READ 0xD528U5414#define ROGUE_CR_RPM_SHF_FPL_READ_MASKFULL 0x00000000007FFFFFULL5415#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_SHIFT 22U5416#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU5417#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_EN 0x00400000U5418#define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_SHIFT 0U5419#define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_CLRMSK 0xFFC00000U5420 5421/* Register ROGUE_CR_RPM_SHF_FPL_WRITE */5422#define ROGUE_CR_RPM_SHF_FPL_WRITE 0xD530U5423#define ROGUE_CR_RPM_SHF_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL5424#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_SHIFT 22U5425#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU5426#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_EN 0x00400000U5427#define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_SHIFT 0U5428#define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U5429 5430/* Register ROGUE_CR_RPM_SHG_FPL */5431#define ROGUE_CR_RPM_SHG_FPL 0xD538U5432#define ROGUE_CR_RPM_SHG_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL5433#define ROGUE_CR_RPM_SHG_FPL_SIZE_SHIFT 40U5434#define ROGUE_CR_RPM_SHG_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL5435#define ROGUE_CR_RPM_SHG_FPL_BASE_SHIFT 2U5436#define ROGUE_CR_RPM_SHG_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL5437#define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSHIFT 2U5438#define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSIZE 4U5439 5440/* Register ROGUE_CR_RPM_SHG_FPL_READ */5441#define ROGUE_CR_RPM_SHG_FPL_READ 0xD540U5442#define ROGUE_CR_RPM_SHG_FPL_READ_MASKFULL 0x00000000007FFFFFULL5443#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_SHIFT 22U5444#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU5445#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_EN 0x00400000U5446#define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_SHIFT 0U5447#define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_CLRMSK 0xFFC00000U5448 5449/* Register ROGUE_CR_RPM_SHG_FPL_WRITE */5450#define ROGUE_CR_RPM_SHG_FPL_WRITE 0xD548U5451#define ROGUE_CR_RPM_SHG_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL5452#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_SHIFT 22U5453#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU5454#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_EN 0x00400000U5455#define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_SHIFT 0U5456#define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U5457 5458/* Register ROGUE_CR_SH_PERF */5459#define ROGUE_CR_SH_PERF 0xD5F8U5460#define ROGUE_CR_SH_PERF_MASKFULL 0x000000000000001FULL5461#define ROGUE_CR_SH_PERF_CLR_3_SHIFT 4U5462#define ROGUE_CR_SH_PERF_CLR_3_CLRMSK 0xFFFFFFEFU5463#define ROGUE_CR_SH_PERF_CLR_3_EN 0x00000010U5464#define ROGUE_CR_SH_PERF_CLR_2_SHIFT 3U5465#define ROGUE_CR_SH_PERF_CLR_2_CLRMSK 0xFFFFFFF7U5466#define ROGUE_CR_SH_PERF_CLR_2_EN 0x00000008U5467#define ROGUE_CR_SH_PERF_CLR_1_SHIFT 2U5468#define ROGUE_CR_SH_PERF_CLR_1_CLRMSK 0xFFFFFFFBU5469#define ROGUE_CR_SH_PERF_CLR_1_EN 0x00000004U5470#define ROGUE_CR_SH_PERF_CLR_0_SHIFT 1U5471#define ROGUE_CR_SH_PERF_CLR_0_CLRMSK 0xFFFFFFFDU5472#define ROGUE_CR_SH_PERF_CLR_0_EN 0x00000002U5473#define ROGUE_CR_SH_PERF_CTRL_ENABLE_SHIFT 0U5474#define ROGUE_CR_SH_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU5475#define ROGUE_CR_SH_PERF_CTRL_ENABLE_EN 0x00000001U5476 5477/* Register ROGUE_CR_SH_PERF_SELECT0 */5478#define ROGUE_CR_SH_PERF_SELECT0 0xD600U5479#define ROGUE_CR_SH_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL5480#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_SHIFT 48U5481#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL5482#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_SHIFT 32U5483#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL5484#define ROGUE_CR_SH_PERF_SELECT0_MODE_SHIFT 21U5485#define ROGUE_CR_SH_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL5486#define ROGUE_CR_SH_PERF_SELECT0_MODE_EN 0x0000000000200000ULL5487#define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_SHIFT 16U5488#define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL5489#define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_SHIFT 0U5490#define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL5491 5492/* Register ROGUE_CR_SH_PERF_COUNTER_0 */5493#define ROGUE_CR_SH_PERF_COUNTER_0 0xD628U5494#define ROGUE_CR_SH_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL5495#define ROGUE_CR_SH_PERF_COUNTER_0_REG_SHIFT 0U5496#define ROGUE_CR_SH_PERF_COUNTER_0_REG_CLRMSK 0x00000000U5497 5498/* Register ROGUE_CR_SHF_SHG_CHECKSUM */5499#define ROGUE_CR_SHF_SHG_CHECKSUM 0xD1C0U5500#define ROGUE_CR_SHF_SHG_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5501#define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_SHIFT 0U5502#define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_CLRMSK 0x00000000U5503 5504/* Register ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM */5505#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM 0xD1C8U5506#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5507#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_SHIFT 0U5508#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U5509 5510/* Register ROGUE_CR_SHF_VARY_BIF_CHECKSUM */5511#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM 0xD1D0U5512#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5513#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_SHIFT 0U5514#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U5515 5516/* Register ROGUE_CR_RPM_BIF_CHECKSUM */5517#define ROGUE_CR_RPM_BIF_CHECKSUM 0xD1D8U5518#define ROGUE_CR_RPM_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5519#define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_SHIFT 0U5520#define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U5521 5522/* Register ROGUE_CR_SHG_BIF_CHECKSUM */5523#define ROGUE_CR_SHG_BIF_CHECKSUM 0xD1E0U5524#define ROGUE_CR_SHG_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5525#define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_SHIFT 0U5526#define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U5527 5528/* Register ROGUE_CR_SHG_FE_BE_CHECKSUM */5529#define ROGUE_CR_SHG_FE_BE_CHECKSUM 0xD1E8U5530#define ROGUE_CR_SHG_FE_BE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5531#define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_SHIFT 0U5532#define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_CLRMSK 0x00000000U5533 5534/* Register DPX_CR_BF_PERF */5535#define DPX_CR_BF_PERF 0xC458U5536#define DPX_CR_BF_PERF_MASKFULL 0x000000000000001FULL5537#define DPX_CR_BF_PERF_CLR_3_SHIFT 4U5538#define DPX_CR_BF_PERF_CLR_3_CLRMSK 0xFFFFFFEFU5539#define DPX_CR_BF_PERF_CLR_3_EN 0x00000010U5540#define DPX_CR_BF_PERF_CLR_2_SHIFT 3U5541#define DPX_CR_BF_PERF_CLR_2_CLRMSK 0xFFFFFFF7U5542#define DPX_CR_BF_PERF_CLR_2_EN 0x00000008U5543#define DPX_CR_BF_PERF_CLR_1_SHIFT 2U5544#define DPX_CR_BF_PERF_CLR_1_CLRMSK 0xFFFFFFFBU5545#define DPX_CR_BF_PERF_CLR_1_EN 0x00000004U5546#define DPX_CR_BF_PERF_CLR_0_SHIFT 1U5547#define DPX_CR_BF_PERF_CLR_0_CLRMSK 0xFFFFFFFDU5548#define DPX_CR_BF_PERF_CLR_0_EN 0x00000002U5549#define DPX_CR_BF_PERF_CTRL_ENABLE_SHIFT 0U5550#define DPX_CR_BF_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU5551#define DPX_CR_BF_PERF_CTRL_ENABLE_EN 0x00000001U5552 5553/* Register DPX_CR_BF_PERF_SELECT0 */5554#define DPX_CR_BF_PERF_SELECT0 0xC460U5555#define DPX_CR_BF_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL5556#define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_SHIFT 48U5557#define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL5558#define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_SHIFT 32U5559#define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL5560#define DPX_CR_BF_PERF_SELECT0_MODE_SHIFT 21U5561#define DPX_CR_BF_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL5562#define DPX_CR_BF_PERF_SELECT0_MODE_EN 0x0000000000200000ULL5563#define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_SHIFT 16U5564#define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL5565#define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_SHIFT 0U5566#define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL5567 5568/* Register DPX_CR_BF_PERF_COUNTER_0 */5569#define DPX_CR_BF_PERF_COUNTER_0 0xC488U5570#define DPX_CR_BF_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL5571#define DPX_CR_BF_PERF_COUNTER_0_REG_SHIFT 0U5572#define DPX_CR_BF_PERF_COUNTER_0_REG_CLRMSK 0x00000000U5573 5574/* Register DPX_CR_BT_PERF */5575#define DPX_CR_BT_PERF 0xC3D0U5576#define DPX_CR_BT_PERF_MASKFULL 0x000000000000001FULL5577#define DPX_CR_BT_PERF_CLR_3_SHIFT 4U5578#define DPX_CR_BT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU5579#define DPX_CR_BT_PERF_CLR_3_EN 0x00000010U5580#define DPX_CR_BT_PERF_CLR_2_SHIFT 3U5581#define DPX_CR_BT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U5582#define DPX_CR_BT_PERF_CLR_2_EN 0x00000008U5583#define DPX_CR_BT_PERF_CLR_1_SHIFT 2U5584#define DPX_CR_BT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU5585#define DPX_CR_BT_PERF_CLR_1_EN 0x00000004U5586#define DPX_CR_BT_PERF_CLR_0_SHIFT 1U5587#define DPX_CR_BT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU5588#define DPX_CR_BT_PERF_CLR_0_EN 0x00000002U5589#define DPX_CR_BT_PERF_CTRL_ENABLE_SHIFT 0U5590#define DPX_CR_BT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU5591#define DPX_CR_BT_PERF_CTRL_ENABLE_EN 0x00000001U5592 5593/* Register DPX_CR_BT_PERF_SELECT0 */5594#define DPX_CR_BT_PERF_SELECT0 0xC3D8U5595#define DPX_CR_BT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL5596#define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_SHIFT 48U5597#define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL5598#define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_SHIFT 32U5599#define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL5600#define DPX_CR_BT_PERF_SELECT0_MODE_SHIFT 21U5601#define DPX_CR_BT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL5602#define DPX_CR_BT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL5603#define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U5604#define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL5605#define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_SHIFT 0U5606#define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL5607 5608/* Register DPX_CR_BT_PERF_COUNTER_0 */5609#define DPX_CR_BT_PERF_COUNTER_0 0xC420U5610#define DPX_CR_BT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL5611#define DPX_CR_BT_PERF_COUNTER_0_REG_SHIFT 0U5612#define DPX_CR_BT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U5613 5614/* Register DPX_CR_RQ_USC_DEBUG */5615#define DPX_CR_RQ_USC_DEBUG 0xC110U5616#define DPX_CR_RQ_USC_DEBUG_MASKFULL 0x00000000FFFFFFFFULL5617#define DPX_CR_RQ_USC_DEBUG_CHECKSUM_SHIFT 0U5618#define DPX_CR_RQ_USC_DEBUG_CHECKSUM_CLRMSK 0xFFFFFFFF00000000ULL5619 5620/* Register DPX_CR_BIF_FAULT_BANK_MMU_STATUS */5621#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS 0xC5C8U5622#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_MASKFULL 0x000000000000F775ULL5623#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_SHIFT 12U5624#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU5625#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_SHIFT 8U5626#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU5627#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_SHIFT 5U5628#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU5629#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_SHIFT 4U5630#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU5631#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_EN 0x00000010U5632#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U5633#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU5634#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U5635#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_SHIFT 0U5636#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU5637#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_EN 0x00000001U5638 5639/* Register DPX_CR_BIF_FAULT_BANK_REQ_STATUS */5640#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS 0xC5D0U5641#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_MASKFULL 0x03FFFFFFFFFFFFF0ULL5642#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_SHIFT 57U5643#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_CLRMSK 0xFDFFFFFFFFFFFFFFULL5644#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_EN 0x0200000000000000ULL5645#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_SHIFT 44U5646#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_CLRMSK 0xFE000FFFFFFFFFFFULL5647#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_SHIFT 40U5648#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL5649#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_SHIFT 4U5650#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL5651#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U5652#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSIZE 16U5653 5654/* Register DPX_CR_BIF_MMU_STATUS */5655#define DPX_CR_BIF_MMU_STATUS 0xC5D8U5656#define DPX_CR_BIF_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL5657#define DPX_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U5658#define DPX_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU5659#define DPX_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U5660#define DPX_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU5661#define DPX_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U5662#define DPX_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU5663#define DPX_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U5664#define DPX_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU5665#define DPX_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U5666#define DPX_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U5667#define DPX_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU5668#define DPX_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U5669#define DPX_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U5670#define DPX_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU5671#define DPX_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U5672 5673/* Register DPX_CR_RT_PERF */5674#define DPX_CR_RT_PERF 0xC700U5675#define DPX_CR_RT_PERF_MASKFULL 0x000000000000001FULL5676#define DPX_CR_RT_PERF_CLR_3_SHIFT 4U5677#define DPX_CR_RT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU5678#define DPX_CR_RT_PERF_CLR_3_EN 0x00000010U5679#define DPX_CR_RT_PERF_CLR_2_SHIFT 3U5680#define DPX_CR_RT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U5681#define DPX_CR_RT_PERF_CLR_2_EN 0x00000008U5682#define DPX_CR_RT_PERF_CLR_1_SHIFT 2U5683#define DPX_CR_RT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU5684#define DPX_CR_RT_PERF_CLR_1_EN 0x00000004U5685#define DPX_CR_RT_PERF_CLR_0_SHIFT 1U5686#define DPX_CR_RT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU5687#define DPX_CR_RT_PERF_CLR_0_EN 0x00000002U5688#define DPX_CR_RT_PERF_CTRL_ENABLE_SHIFT 0U5689#define DPX_CR_RT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU5690#define DPX_CR_RT_PERF_CTRL_ENABLE_EN 0x00000001U5691 5692/* Register DPX_CR_RT_PERF_SELECT0 */5693#define DPX_CR_RT_PERF_SELECT0 0xC708U5694#define DPX_CR_RT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL5695#define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_SHIFT 48U5696#define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL5697#define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_SHIFT 32U5698#define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL5699#define DPX_CR_RT_PERF_SELECT0_MODE_SHIFT 21U5700#define DPX_CR_RT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL5701#define DPX_CR_RT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL5702#define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U5703#define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL5704#define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_SHIFT 0U5705#define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL5706 5707/* Register DPX_CR_RT_PERF_COUNTER_0 */5708#define DPX_CR_RT_PERF_COUNTER_0 0xC730U5709#define DPX_CR_RT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL5710#define DPX_CR_RT_PERF_COUNTER_0_REG_SHIFT 0U5711#define DPX_CR_RT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U5712 5713/* Register DPX_CR_BX_TU_PERF */5714#define DPX_CR_BX_TU_PERF 0xC908U5715#define DPX_CR_BX_TU_PERF_MASKFULL 0x000000000000001FULL5716#define DPX_CR_BX_TU_PERF_CLR_3_SHIFT 4U5717#define DPX_CR_BX_TU_PERF_CLR_3_CLRMSK 0xFFFFFFEFU5718#define DPX_CR_BX_TU_PERF_CLR_3_EN 0x00000010U5719#define DPX_CR_BX_TU_PERF_CLR_2_SHIFT 3U5720#define DPX_CR_BX_TU_PERF_CLR_2_CLRMSK 0xFFFFFFF7U5721#define DPX_CR_BX_TU_PERF_CLR_2_EN 0x00000008U5722#define DPX_CR_BX_TU_PERF_CLR_1_SHIFT 2U5723#define DPX_CR_BX_TU_PERF_CLR_1_CLRMSK 0xFFFFFFFBU5724#define DPX_CR_BX_TU_PERF_CLR_1_EN 0x00000004U5725#define DPX_CR_BX_TU_PERF_CLR_0_SHIFT 1U5726#define DPX_CR_BX_TU_PERF_CLR_0_CLRMSK 0xFFFFFFFDU5727#define DPX_CR_BX_TU_PERF_CLR_0_EN 0x00000002U5728#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_SHIFT 0U5729#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU5730#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_EN 0x00000001U5731 5732/* Register DPX_CR_BX_TU_PERF_SELECT0 */5733#define DPX_CR_BX_TU_PERF_SELECT0 0xC910U5734#define DPX_CR_BX_TU_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL5735#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_SHIFT 48U5736#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL5737#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_SHIFT 32U5738#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL5739#define DPX_CR_BX_TU_PERF_SELECT0_MODE_SHIFT 21U5740#define DPX_CR_BX_TU_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL5741#define DPX_CR_BX_TU_PERF_SELECT0_MODE_EN 0x0000000000200000ULL5742#define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_SHIFT 16U5743#define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL5744#define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_SHIFT 0U5745#define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL5746 5747/* Register DPX_CR_BX_TU_PERF_COUNTER_0 */5748#define DPX_CR_BX_TU_PERF_COUNTER_0 0xC938U5749#define DPX_CR_BX_TU_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL5750#define DPX_CR_BX_TU_PERF_COUNTER_0_REG_SHIFT 0U5751#define DPX_CR_BX_TU_PERF_COUNTER_0_REG_CLRMSK 0x00000000U5752 5753/* Register DPX_CR_RS_PDS_RR_CHECKSUM */5754#define DPX_CR_RS_PDS_RR_CHECKSUM 0xC0F0U5755#define DPX_CR_RS_PDS_RR_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL5756#define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_SHIFT 0U5757#define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_CLRMSK 0xFFFFFFFF00000000ULL5758 5759/* Register ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT */5760#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT 0xE140U5761#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_MASKFULL 0x00000000000000FFULL5762#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT 0U5763#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK 0xFFFFFF00U5764 5765/* Register ROGUE_CR_MMU_CBASE_MAPPING */5766#define ROGUE_CR_MMU_CBASE_MAPPING 0xE148U5767#define ROGUE_CR_MMU_CBASE_MAPPING_MASKFULL 0x000000000FFFFFFFULL5768#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT 0U5769#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK 0xF0000000U5770#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT 12U5771#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE 4096U5772 5773/* Register ROGUE_CR_MMU_FAULT_STATUS */5774#define ROGUE_CR_MMU_FAULT_STATUS 0xE150U5775#define ROGUE_CR_MMU_FAULT_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL5776#define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_SHIFT 28U5777#define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_CLRMSK 0x000000000FFFFFFFULL5778#define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_SHIFT 20U5779#define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL5780#define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_SHIFT 12U5781#define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL5782#define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_SHIFT 6U5783#define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL5784#define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_SHIFT 4U5785#define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL5786#define ROGUE_CR_MMU_FAULT_STATUS_RNW_SHIFT 3U5787#define ROGUE_CR_MMU_FAULT_STATUS_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL5788#define ROGUE_CR_MMU_FAULT_STATUS_RNW_EN 0x0000000000000008ULL5789#define ROGUE_CR_MMU_FAULT_STATUS_TYPE_SHIFT 1U5790#define ROGUE_CR_MMU_FAULT_STATUS_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL5791#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_SHIFT 0U5792#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL5793#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_EN 0x0000000000000001ULL5794 5795/* Register ROGUE_CR_MMU_FAULT_STATUS_META */5796#define ROGUE_CR_MMU_FAULT_STATUS_META 0xE158U5797#define ROGUE_CR_MMU_FAULT_STATUS_META_MASKFULL 0xFFFFFFFFFFFFFFFFULL5798#define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT 28U5799#define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK 0x000000000FFFFFFFULL5800#define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT 20U5801#define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL5802#define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_SHIFT 12U5803#define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL5804#define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT 6U5805#define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL5806#define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT 4U5807#define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL5808#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_SHIFT 3U5809#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL5810#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_EN 0x0000000000000008ULL5811#define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT 1U5812#define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL5813#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT 0U5814#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL5815#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_EN 0x0000000000000001ULL5816 5817/* Register ROGUE_CR_SLC3_CTRL_MISC */5818#define ROGUE_CR_SLC3_CTRL_MISC 0xE200U5819#define ROGUE_CR_SLC3_CTRL_MISC_MASKFULL 0x0000000000000107ULL5820#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_SHIFT 8U5821#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_CLRMSK 0xFFFFFEFFU5822#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_EN 0x00000100U5823#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 0U5824#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFF8U5825#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_LINEAR 0x00000000U5826#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_IN_PAGE_HASH 0x00000001U5827#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_FIXED_PVR_HASH 0x00000002U5828#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SCRAMBLE_PVR_HASH 0x00000003U5829#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_WEAVED_HASH 0x00000004U5830 5831/* Register ROGUE_CR_SLC3_SCRAMBLE */5832#define ROGUE_CR_SLC3_SCRAMBLE 0xE208U5833#define ROGUE_CR_SLC3_SCRAMBLE_MASKFULL 0xFFFFFFFFFFFFFFFFULL5834#define ROGUE_CR_SLC3_SCRAMBLE_BITS_SHIFT 0U5835#define ROGUE_CR_SLC3_SCRAMBLE_BITS_CLRMSK 0x0000000000000000ULL5836 5837/* Register ROGUE_CR_SLC3_SCRAMBLE2 */5838#define ROGUE_CR_SLC3_SCRAMBLE2 0xE210U5839#define ROGUE_CR_SLC3_SCRAMBLE2_MASKFULL 0xFFFFFFFFFFFFFFFFULL5840#define ROGUE_CR_SLC3_SCRAMBLE2_BITS_SHIFT 0U5841#define ROGUE_CR_SLC3_SCRAMBLE2_BITS_CLRMSK 0x0000000000000000ULL5842 5843/* Register ROGUE_CR_SLC3_SCRAMBLE3 */5844#define ROGUE_CR_SLC3_SCRAMBLE3 0xE218U5845#define ROGUE_CR_SLC3_SCRAMBLE3_MASKFULL 0xFFFFFFFFFFFFFFFFULL5846#define ROGUE_CR_SLC3_SCRAMBLE3_BITS_SHIFT 0U5847#define ROGUE_CR_SLC3_SCRAMBLE3_BITS_CLRMSK 0x0000000000000000ULL5848 5849/* Register ROGUE_CR_SLC3_SCRAMBLE4 */5850#define ROGUE_CR_SLC3_SCRAMBLE4 0xE260U5851#define ROGUE_CR_SLC3_SCRAMBLE4_MASKFULL 0xFFFFFFFFFFFFFFFFULL5852#define ROGUE_CR_SLC3_SCRAMBLE4_BITS_SHIFT 0U5853#define ROGUE_CR_SLC3_SCRAMBLE4_BITS_CLRMSK 0x0000000000000000ULL5854 5855/* Register ROGUE_CR_SLC3_STATUS */5856#define ROGUE_CR_SLC3_STATUS 0xE220U5857#define ROGUE_CR_SLC3_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL5858#define ROGUE_CR_SLC3_STATUS_WRITES1_SHIFT 48U5859#define ROGUE_CR_SLC3_STATUS_WRITES1_CLRMSK 0x0000FFFFFFFFFFFFULL5860#define ROGUE_CR_SLC3_STATUS_WRITES0_SHIFT 32U5861#define ROGUE_CR_SLC3_STATUS_WRITES0_CLRMSK 0xFFFF0000FFFFFFFFULL5862#define ROGUE_CR_SLC3_STATUS_READS1_SHIFT 16U5863#define ROGUE_CR_SLC3_STATUS_READS1_CLRMSK 0xFFFFFFFF0000FFFFULL5864#define ROGUE_CR_SLC3_STATUS_READS0_SHIFT 0U5865#define ROGUE_CR_SLC3_STATUS_READS0_CLRMSK 0xFFFFFFFFFFFF0000ULL5866 5867/* Register ROGUE_CR_SLC3_IDLE */5868#define ROGUE_CR_SLC3_IDLE 0xE228U5869#define ROGUE_CR_SLC3_IDLE_MASKFULL 0x00000000000FFFFFULL5870#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_SHIFT 18U5871#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_CLRMSK 0xFFF3FFFFU5872#define ROGUE_CR_SLC3_IDLE_MMU_SHIFT 17U5873#define ROGUE_CR_SLC3_IDLE_MMU_CLRMSK 0xFFFDFFFFU5874#define ROGUE_CR_SLC3_IDLE_MMU_EN 0x00020000U5875#define ROGUE_CR_SLC3_IDLE_RDI_SHIFT 16U5876#define ROGUE_CR_SLC3_IDLE_RDI_CLRMSK 0xFFFEFFFFU5877#define ROGUE_CR_SLC3_IDLE_RDI_EN 0x00010000U5878#define ROGUE_CR_SLC3_IDLE_IMGBV4_SHIFT 12U5879#define ROGUE_CR_SLC3_IDLE_IMGBV4_CLRMSK 0xFFFF0FFFU5880#define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_SHIFT 4U5881#define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_CLRMSK 0xFFFFF00FU5882#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_SHIFT 2U5883#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_CLRMSK 0xFFFFFFF3U5884#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_SHIFT 1U5885#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_CLRMSK 0xFFFFFFFDU5886#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_EN 0x00000002U5887#define ROGUE_CR_SLC3_IDLE_XBAR_SHIFT 0U5888#define ROGUE_CR_SLC3_IDLE_XBAR_CLRMSK 0xFFFFFFFEU5889#define ROGUE_CR_SLC3_IDLE_XBAR_EN 0x00000001U5890 5891/* Register ROGUE_CR_SLC3_FAULT_STOP_STATUS */5892#define ROGUE_CR_SLC3_FAULT_STOP_STATUS 0xE248U5893#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_MASKFULL 0x0000000000001FFFULL5894#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_SHIFT 0U5895#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_CLRMSK 0xFFFFE000U5896 5897/* Register ROGUE_CR_VDM_CONTEXT_STORE_MODE */5898#define ROGUE_CR_VDM_CONTEXT_STORE_MODE 0xF048U5899#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MASKFULL 0x0000000000000003ULL5900#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_SHIFT 0U5901#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_CLRMSK 0xFFFFFFFCU5902#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX 0x00000000U5903#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE 0x00000001U5904#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST 0x00000002U5905 5906/* Register ROGUE_CR_CONTEXT_MAPPING0 */5907#define ROGUE_CR_CONTEXT_MAPPING0 0xF078U5908#define ROGUE_CR_CONTEXT_MAPPING0_MASKFULL 0x00000000FFFFFFFFULL5909#define ROGUE_CR_CONTEXT_MAPPING0_2D_SHIFT 24U5910#define ROGUE_CR_CONTEXT_MAPPING0_2D_CLRMSK 0x00FFFFFFU5911#define ROGUE_CR_CONTEXT_MAPPING0_CDM_SHIFT 16U5912#define ROGUE_CR_CONTEXT_MAPPING0_CDM_CLRMSK 0xFF00FFFFU5913#define ROGUE_CR_CONTEXT_MAPPING0_3D_SHIFT 8U5914#define ROGUE_CR_CONTEXT_MAPPING0_3D_CLRMSK 0xFFFF00FFU5915#define ROGUE_CR_CONTEXT_MAPPING0_TA_SHIFT 0U5916#define ROGUE_CR_CONTEXT_MAPPING0_TA_CLRMSK 0xFFFFFF00U5917 5918/* Register ROGUE_CR_CONTEXT_MAPPING1 */5919#define ROGUE_CR_CONTEXT_MAPPING1 0xF080U5920#define ROGUE_CR_CONTEXT_MAPPING1_MASKFULL 0x000000000000FFFFULL5921#define ROGUE_CR_CONTEXT_MAPPING1_HOST_SHIFT 8U5922#define ROGUE_CR_CONTEXT_MAPPING1_HOST_CLRMSK 0xFFFF00FFU5923#define ROGUE_CR_CONTEXT_MAPPING1_TLA_SHIFT 0U5924#define ROGUE_CR_CONTEXT_MAPPING1_TLA_CLRMSK 0xFFFFFF00U5925 5926/* Register ROGUE_CR_CONTEXT_MAPPING2 */5927#define ROGUE_CR_CONTEXT_MAPPING2 0xF088U5928#define ROGUE_CR_CONTEXT_MAPPING2_MASKFULL 0x0000000000FFFFFFULL5929#define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_SHIFT 16U5930#define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK 0xFF00FFFFU5931#define ROGUE_CR_CONTEXT_MAPPING2_TE0_SHIFT 8U5932#define ROGUE_CR_CONTEXT_MAPPING2_TE0_CLRMSK 0xFFFF00FFU5933#define ROGUE_CR_CONTEXT_MAPPING2_VCE0_SHIFT 0U5934#define ROGUE_CR_CONTEXT_MAPPING2_VCE0_CLRMSK 0xFFFFFF00U5935 5936/* Register ROGUE_CR_CONTEXT_MAPPING3 */5937#define ROGUE_CR_CONTEXT_MAPPING3 0xF090U5938#define ROGUE_CR_CONTEXT_MAPPING3_MASKFULL 0x0000000000FFFFFFULL5939#define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_SHIFT 16U5940#define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK 0xFF00FFFFU5941#define ROGUE_CR_CONTEXT_MAPPING3_TE1_SHIFT 8U5942#define ROGUE_CR_CONTEXT_MAPPING3_TE1_CLRMSK 0xFFFF00FFU5943#define ROGUE_CR_CONTEXT_MAPPING3_VCE1_SHIFT 0U5944#define ROGUE_CR_CONTEXT_MAPPING3_VCE1_CLRMSK 0xFFFFFF00U5945 5946/* Register ROGUE_CR_BIF_JONES_OUTSTANDING_READ */5947#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ 0xF098U5948#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL5949#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_SHIFT 0U5950#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U5951 5952/* Register ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ */5953#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ 0xF0A0U5954#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL5955#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_SHIFT 0U5956#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U5957 5958/* Register ROGUE_CR_BIF_DUST_OUTSTANDING_READ */5959#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ 0xF0A8U5960#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL5961#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_SHIFT 0U5962#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U5963 5964/* Register ROGUE_CR_CONTEXT_MAPPING4 */5965#define ROGUE_CR_CONTEXT_MAPPING4 0xF210U5966#define ROGUE_CR_CONTEXT_MAPPING4_MASKFULL 0x0000FFFFFFFFFFFFULL5967#define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT 40U5968#define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_CLRMSK 0xFFFF00FFFFFFFFFFULL5969#define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT 32U5970#define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_CLRMSK 0xFFFFFF00FFFFFFFFULL5971#define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT 24U5972#define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_CLRMSK 0xFFFFFFFF00FFFFFFULL5973#define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT 16U5974#define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_CLRMSK 0xFFFFFFFFFF00FFFFULL5975#define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT 8U5976#define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_CLRMSK 0xFFFFFFFFFFFF00FFULL5977#define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT 0U5978#define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_CLRMSK 0xFFFFFFFFFFFFFF00ULL5979 5980/* Register ROGUE_CR_MULTICORE_GPU */5981#define ROGUE_CR_MULTICORE_GPU 0xF300U5982#define ROGUE_CR_MULTICORE_GPU_MASKFULL 0x000000000000007FULL5983#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_SHIFT 6U5984#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_CLRMSK 0xFFFFFFBFU5985#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_EN 0x00000040U5986#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_SHIFT 5U5987#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_CLRMSK 0xFFFFFFDFU5988#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_EN 0x00000020U5989#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_SHIFT 4U5990#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_CLRMSK 0xFFFFFFEFU5991#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_EN 0x00000010U5992#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_SHIFT 3U5993#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_CLRMSK 0xFFFFFFF7U5994#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_EN 0x00000008U5995#define ROGUE_CR_MULTICORE_GPU_ID_SHIFT 0U5996#define ROGUE_CR_MULTICORE_GPU_ID_CLRMSK 0xFFFFFFF8U5997 5998/* Register ROGUE_CR_MULTICORE_SYSTEM */5999#define ROGUE_CR_MULTICORE_SYSTEM 0xF308U6000#define ROGUE_CR_MULTICORE_SYSTEM_MASKFULL 0x000000000000000FULL6001#define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT 0U6002#define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_CLRMSK 0xFFFFFFF0U6003 6004/* Register ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON */6005#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON 0xF310U6006#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL6007#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U6008#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU6009#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U6010#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU6011#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT 0U6012#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U6013 6014/* Register ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON */6015#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON 0xF320U6016#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL6017#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U6018#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU6019#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U6020#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU6021#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_SHIFT 0U6022#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U6023 6024/* Register ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON */6025#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON 0xF330U6026#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL6027#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U6028#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU6029#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U6030#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU6031#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U6032#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U6033 6034/* Register ROGUE_CR_ECC_RAM_ERR_INJ */6035#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U6036#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL6037#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U6038#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU6039#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U6040#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U6041#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U6042#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U6043#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U6044#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU6045#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U6046#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U6047#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU6048#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U6049#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U6050#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU6051#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U6052 6053/* Register ROGUE_CR_ECC_RAM_INIT_KICK */6054#define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U6055#define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL6056#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_SHIFT 4U6057#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU6058#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_EN 0x00000010U6059#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_SHIFT 3U6060#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_CLRMSK 0xFFFFFFF7U6061#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_EN 0x00000008U6062#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_SHIFT 2U6063#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU6064#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_EN 0x00000004U6065#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_SHIFT 1U6066#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_CLRMSK 0xFFFFFFFDU6067#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_EN 0x00000002U6068#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_SHIFT 0U6069#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_CLRMSK 0xFFFFFFFEU6070#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_EN 0x00000001U6071 6072/* Register ROGUE_CR_ECC_RAM_INIT_DONE */6073#define ROGUE_CR_ECC_RAM_INIT_DONE 0xF350U6074#define ROGUE_CR_ECC_RAM_INIT_DONE_MASKFULL 0x000000000000001FULL6075#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_SHIFT 4U6076#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU6077#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_EN 0x00000010U6078#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_SHIFT 3U6079#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_CLRMSK 0xFFFFFFF7U6080#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_EN 0x00000008U6081#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_SHIFT 2U6082#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU6083#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_EN 0x00000004U6084#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_SHIFT 1U6085#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_CLRMSK 0xFFFFFFFDU6086#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_EN 0x00000002U6087#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_SHIFT 0U6088#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_CLRMSK 0xFFFFFFFEU6089#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_EN 0x00000001U6090 6091/* Register ROGUE_CR_SAFETY_EVENT_ENABLE */6092#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE 0xF390U6093#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL6094#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U6095#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU6096#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U6097#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U6098#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU6099#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U6100#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U6101#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU6102#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U6103#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U6104#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U6105#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U6106#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U6107#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU6108#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U6109#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U6110#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU6111#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U6112#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U6113#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU6114#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U6115 6116/* Register ROGUE_CR_SAFETY_EVENT_STATUS */6117#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE 0xF398U6118#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__MASKFULL 0x000000000000007FULL6119#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U6120#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU6121#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U6122#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U6123#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU6124#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U6125#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U6126#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU6127#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U6128#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_SHIFT 3U6129#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U6130#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_EN 0x00000008U6131#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_SHIFT 2U6132#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU6133#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN 0x00000004U6134#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_SHIFT 1U6135#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU6136#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_EN 0x00000002U6137#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U6138#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU6139#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U6140 6141/* Register ROGUE_CR_SAFETY_EVENT_CLEAR */6142#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE 0xF3A0U6143#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__MASKFULL 0x000000000000007FULL6144#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U6145#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU6146#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U6147#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U6148#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU6149#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U6150#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U6151#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU6152#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U6153#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_SHIFT 3U6154#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U6155#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_EN 0x00000008U6156#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_SHIFT 2U6157#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU6158#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_EN 0x00000004U6159#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_SHIFT 1U6160#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU6161#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_EN 0x00000002U6162#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U6163#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU6164#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U6165 6166/* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */6167#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U6168#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL6169#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U6170#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU6171#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U6172#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U6173#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU6174#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U6175#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U6176#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU6177#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U6178#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U6179#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U6180#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U6181#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U6182#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU6183#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U6184#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U6185#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU6186#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U6187#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U6188#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU6189#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U6190 6191/* clang-format on */6192 6193#endif /* PVR_ROGUE_CR_DEFS_H */6194