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1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */2/* Copyright (c) 2023 Imagination Technologies Ltd. */3 4#ifndef PVR_ROGUE_CR_DEFS_CLIENT_H5#define PVR_ROGUE_CR_DEFS_CLIENT_H6 7/* clang-format off */8 9/*10 * This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is11 * provided in both X & Y axis.12 * This register needs to be set based on the ISP Samples Per Pixel a core supports.13 *14 * When ISP Samples Per Pixel = 1:15 * 2xmsaa is achieved by enabling Y - TE does AA on Y plane only16 * 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane17 * 8xmsaa not supported by XE cores18 *19 * When ISP Samples Per Pixel = 2:20 * 2xmsaa is achieved by enabling X2 - does not affect TE21 * 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only22 * 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane23 * 8xmsaa not supported by XE cores24 *25 * When ISP Samples Per Pixel = 4:26 * 2xmsaa is achieved by enabling X2 - does not affect TE27 * 4xmsaa is achieved by enabling Y2 and X2 - TE does AA on Y plane only28 * 8xmsaa not supported by XE cores29 */30/* Register ROGUE_CR_TE_AA */31#define ROGUE_CR_TE_AA 0x0C00U32#define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full33/* Y234 * Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within35 * TPW.36 */37#define ROGUE_CR_TE_AA_Y2_SHIFT 338#define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF739#define ROGUE_CR_TE_AA_Y2_EN 0x0000000840/* Y41 * Anti-Aliasing in Y Plane Enabled42 */43#define ROGUE_CR_TE_AA_Y_SHIFT 244#define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB45#define ROGUE_CR_TE_AA_Y_EN 0x0000000446/* X47 * Anti-Aliasing in X Plane Enabled48 */49#define ROGUE_CR_TE_AA_X_SHIFT 150#define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD51#define ROGUE_CR_TE_AA_X_EN 0x0000000252/* X253 * 2x Anti-Aliasing Enabled, affects PPP only54 */55#define ROGUE_CR_TE_AA_X2_SHIFT (0U)56#define ROGUE_CR_TE_AA_X2_CLRMSK (0xFFFFFFFEU)57#define ROGUE_CR_TE_AA_X2_EN (0x00000001U)58 59/* MacroTile Boundaries X Plane */60/* Register ROGUE_CR_TE_MTILE1 */61#define ROGUE_CR_TE_MTILE1 0x0C0862#define ROGUE_CR_TE_MTILE1_MASKFULL 0x0000000007FFFFFFull63/* X1 default: 0x0000000464 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across65 * tile66 */67#define ROGUE_CR_TE_MTILE1_X1_SHIFT 1868#define ROGUE_CR_TE_MTILE1_X1_CLRMSK 0xF803FFFF69/* X2 default: 0x0000000870 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile71 */72#define ROGUE_CR_TE_MTILE1_X2_SHIFT 9U73#define ROGUE_CR_TE_MTILE1_X2_CLRMSK 0xFFFC01FF74/* X3 default: 0x0000000c75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile76 */77#define ROGUE_CR_TE_MTILE1_X3_SHIFT 078#define ROGUE_CR_TE_MTILE1_X3_CLRMSK 0xFFFFFE0079 80/* MacroTile Boundaries Y Plane. */81/* Register ROGUE_CR_TE_MTILE2 */82#define ROGUE_CR_TE_MTILE2 0x0C1083#define ROGUE_CR_TE_MTILE2_MASKFULL 0x0000000007FFFFFFull84/* Y1 default: 0x0000000485 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile86 * height87 */88#define ROGUE_CR_TE_MTILE2_Y1_SHIFT 1889#define ROGUE_CR_TE_MTILE2_Y1_CLRMSK 0xF803FFFF90/* Y2 default: 0x0000000891 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height92 */93#define ROGUE_CR_TE_MTILE2_Y2_SHIFT 994#define ROGUE_CR_TE_MTILE2_Y2_CLRMSK 0xFFFC01FF95/* Y3 default: 0x0000000c96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height97 */98#define ROGUE_CR_TE_MTILE2_Y3_SHIFT 099#define ROGUE_CR_TE_MTILE2_Y3_CLRMSK 0xFFFFFE00100 101/*102 * In order to perform the tiling operation and generate the display list the maximum screen size103 * must be configured in terms of the number of tiles in X & Y axis.104 */105 106/* Register ROGUE_CR_TE_SCREEN */107#define ROGUE_CR_TE_SCREEN 0x0C18U108#define ROGUE_CR_TE_SCREEN_MASKFULL 0x00000000001FF1FFull109/* YMAX default: 0x00000010110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size111 */112#define ROGUE_CR_TE_SCREEN_YMAX_SHIFT 12113#define ROGUE_CR_TE_SCREEN_YMAX_CLRMSK 0xFFE00FFF114/* XMAX default: 0x00000010115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size116 */117#define ROGUE_CR_TE_SCREEN_XMAX_SHIFT 0118#define ROGUE_CR_TE_SCREEN_XMAX_CLRMSK 0xFFFFFE00119 120/*121 * In order to perform the tiling operation and generate the display list the maximum screen size122 * must be configured in terms of the number of pixels in X & Y axis since this may not be the same123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.124 */125/* Register ROGUE_CR_PPP_SCREEN */126#define ROGUE_CR_PPP_SCREEN 0x0C98127#define ROGUE_CR_PPP_SCREEN_MASKFULL 0x000000007FFF7FFFull128/* PIXYMAX129 * Screen height in pixels. (16K x 16K max screen size)130 */131#define ROGUE_CR_PPP_SCREEN_PIXYMAX_SHIFT 16132#define ROGUE_CR_PPP_SCREEN_PIXYMAX_CLRMSK 0x8000FFFF133/* PIXXMAX134 * Screen width in pixels.(16K x 16K max screen size)135 */136#define ROGUE_CR_PPP_SCREEN_PIXXMAX_SHIFT 0137#define ROGUE_CR_PPP_SCREEN_PIXXMAX_CLRMSK 0xFFFF8000138 139/* Register ROGUE_CR_ISP_MTILE_SIZE */140#define ROGUE_CR_ISP_MTILE_SIZE 0x0F18141#define ROGUE_CR_ISP_MTILE_SIZE_MASKFULL 0x0000000003FF03FFull142/* X143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size144 */145#define ROGUE_CR_ISP_MTILE_SIZE_X_SHIFT 16146#define ROGUE_CR_ISP_MTILE_SIZE_X_CLRMSK 0xFC00FFFF147#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSHIFT 0148#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSIZE 1149/* Y150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size151 */152#define ROGUE_CR_ISP_MTILE_SIZE_Y_SHIFT 0153#define ROGUE_CR_ISP_MTILE_SIZE_Y_CLRMSK 0xFFFFFC00154#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSHIFT 0155#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSIZE 1156 157/* clang-format on */158 159#endif /* PVR_ROGUE_CR_DEFS_CLIENT_H */160