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1// SPDX-License-Identifier: GPL-2.0+2/*3 * i.MX drm driver - LVDS display bridge4 *5 * Copyright (C) 2012 Sascha Hauer, Pengutronix6 */7 8#include <linux/clk.h>9#include <linux/component.h>10#include <linux/i2c.h>11#include <linux/media-bus-format.h>12#include <linux/mfd/syscon.h>13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/of_graph.h>17#include <linux/platform_device.h>18#include <linux/property.h>19#include <linux/regmap.h>20#include <linux/videodev2.h>21 22#include <video/of_display_timing.h>23#include <video/of_videomode.h>24 25#include <drm/drm_atomic.h>26#include <drm/drm_atomic_helper.h>27#include <drm/drm_bridge.h>28#include <drm/drm_edid.h>29#include <drm/drm_managed.h>30#include <drm/drm_of.h>31#include <drm/drm_panel.h>32#include <drm/drm_print.h>33#include <drm/drm_probe_helper.h>34#include <drm/drm_simple_kms_helper.h>35 36#include "imx-drm.h"37 38#define DRIVER_NAME "imx-ldb"39 40#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)41#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)42#define LDB_CH0_MODE_EN_MASK (3 << 0)43#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)44#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)45#define LDB_CH1_MODE_EN_MASK (3 << 2)46#define LDB_SPLIT_MODE_EN (1 << 4)47#define LDB_DATA_WIDTH_CH0_24 (1 << 5)48#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)49#define LDB_DATA_WIDTH_CH1_24 (1 << 7)50#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)51#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)52#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)53#define LDB_BGREF_RMODE_INT (1 << 15)54 55struct imx_ldb_channel;56 57struct imx_ldb_encoder {58 struct drm_connector connector;59 struct drm_encoder encoder;60 struct imx_ldb_channel *channel;61};62 63struct imx_ldb;64 65struct imx_ldb_channel {66 struct imx_ldb *ldb;67 68 /* Defines what is connected to the ldb, only one at a time */69 struct drm_panel *panel;70 struct drm_bridge *bridge;71 72 struct device_node *child;73 struct i2c_adapter *ddc;74 int chno;75 const struct drm_edid *drm_edid;76 struct drm_display_mode mode;77 int mode_valid;78 u32 bus_format;79 u32 bus_flags;80};81 82static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)83{84 return container_of(c, struct imx_ldb_encoder, connector)->channel;85}86 87static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)88{89 return container_of(e, struct imx_ldb_encoder, encoder)->channel;90}91 92struct bus_mux {93 int reg;94 int shift;95 int mask;96};97 98struct imx_ldb {99 struct regmap *regmap;100 struct device *dev;101 struct imx_ldb_channel channel[2];102 struct clk *clk[2]; /* our own clock */103 struct clk *clk_sel[4]; /* parent of display clock */104 struct clk *clk_parent[4]; /* original parent of clk_sel */105 struct clk *clk_pll[2]; /* upstream clock we can adjust */106 u32 ldb_ctrl;107 const struct bus_mux *lvds_mux;108};109 110static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,111 u32 bus_format)112{113 struct imx_ldb *ldb = imx_ldb_ch->ldb;114 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;115 116 switch (bus_format) {117 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:118 break;119 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:120 if (imx_ldb_ch->chno == 0 || dual)121 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;122 if (imx_ldb_ch->chno == 1 || dual)123 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;124 break;125 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:126 if (imx_ldb_ch->chno == 0 || dual)127 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |128 LDB_BIT_MAP_CH0_JEIDA;129 if (imx_ldb_ch->chno == 1 || dual)130 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |131 LDB_BIT_MAP_CH1_JEIDA;132 break;133 }134}135 136static int imx_ldb_connector_get_modes(struct drm_connector *connector)137{138 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);139 int num_modes;140 141 num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);142 if (num_modes > 0)143 return num_modes;144 145 if (!imx_ldb_ch->drm_edid && imx_ldb_ch->ddc) {146 imx_ldb_ch->drm_edid = drm_edid_read_ddc(connector,147 imx_ldb_ch->ddc);148 drm_edid_connector_update(connector, imx_ldb_ch->drm_edid);149 }150 151 if (imx_ldb_ch->drm_edid)152 num_modes = drm_edid_connector_add_modes(connector);153 154 if (imx_ldb_ch->mode_valid) {155 struct drm_display_mode *mode;156 157 mode = drm_mode_duplicate(connector->dev, &imx_ldb_ch->mode);158 if (!mode)159 return -EINVAL;160 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;161 drm_mode_probed_add(connector, mode);162 num_modes++;163 }164 165 return num_modes;166}167 168static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,169 unsigned long serial_clk, unsigned long di_clk)170{171 int ret;172 173 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,174 clk_get_rate(ldb->clk_pll[chno]), serial_clk);175 clk_set_rate(ldb->clk_pll[chno], serial_clk);176 177 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,178 clk_get_rate(ldb->clk_pll[chno]));179 180 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,181 clk_get_rate(ldb->clk[chno]),182 (long int)di_clk);183 clk_set_rate(ldb->clk[chno], di_clk);184 185 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,186 clk_get_rate(ldb->clk[chno]));187 188 /* set display clock mux to LDB input clock */189 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);190 if (ret)191 dev_err(ldb->dev,192 "unable to set di%d parent clock to ldb_di%d\n", mux,193 chno);194}195 196static void imx_ldb_encoder_enable(struct drm_encoder *encoder)197{198 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);199 struct imx_ldb *ldb = imx_ldb_ch->ldb;200 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;201 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);202 203 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {204 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);205 return;206 }207 208 drm_panel_prepare(imx_ldb_ch->panel);209 210 if (dual) {211 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);212 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);213 214 clk_prepare_enable(ldb->clk[0]);215 clk_prepare_enable(ldb->clk[1]);216 } else {217 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);218 }219 220 if (imx_ldb_ch == &ldb->channel[0] || dual) {221 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;222 if (mux == 0 || ldb->lvds_mux)223 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;224 else if (mux == 1)225 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;226 }227 if (imx_ldb_ch == &ldb->channel[1] || dual) {228 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;229 if (mux == 1 || ldb->lvds_mux)230 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;231 else if (mux == 0)232 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;233 }234 235 if (ldb->lvds_mux) {236 const struct bus_mux *lvds_mux = NULL;237 238 if (imx_ldb_ch == &ldb->channel[0])239 lvds_mux = &ldb->lvds_mux[0];240 else if (imx_ldb_ch == &ldb->channel[1])241 lvds_mux = &ldb->lvds_mux[1];242 243 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,244 mux << lvds_mux->shift);245 }246 247 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);248 249 drm_panel_enable(imx_ldb_ch->panel);250}251 252static void253imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,254 struct drm_crtc_state *crtc_state,255 struct drm_connector_state *connector_state)256{257 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);258 struct drm_display_mode *mode = &crtc_state->adjusted_mode;259 struct imx_ldb *ldb = imx_ldb_ch->ldb;260 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;261 unsigned long serial_clk;262 unsigned long di_clk = mode->clock * 1000;263 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);264 u32 bus_format = imx_ldb_ch->bus_format;265 266 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {267 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);268 return;269 }270 271 if (mode->clock > 170000) {272 dev_warn(ldb->dev,273 "%s: mode exceeds 170 MHz pixel clock\n", __func__);274 }275 if (mode->clock > 85000 && !dual) {276 dev_warn(ldb->dev,277 "%s: mode exceeds 85 MHz pixel clock\n", __func__);278 }279 280 if (!IS_ALIGNED(mode->hdisplay, 8)) {281 dev_warn(ldb->dev,282 "%s: hdisplay does not align to 8 byte\n", __func__);283 }284 285 if (dual) {286 serial_clk = 3500UL * mode->clock;287 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);288 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);289 } else {290 serial_clk = 7000UL * mode->clock;291 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,292 di_clk);293 }294 295 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */296 if (imx_ldb_ch == &ldb->channel[0] || dual) {297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)298 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;299 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)300 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;301 }302 if (imx_ldb_ch == &ldb->channel[1] || dual) {303 if (mode->flags & DRM_MODE_FLAG_NVSYNC)304 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;305 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)306 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;307 }308 309 if (!bus_format) {310 struct drm_connector *connector = connector_state->connector;311 struct drm_display_info *di = &connector->display_info;312 313 if (di->num_bus_formats)314 bus_format = di->bus_formats[0];315 }316 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);317}318 319static void imx_ldb_encoder_disable(struct drm_encoder *encoder)320{321 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);322 struct imx_ldb *ldb = imx_ldb_ch->ldb;323 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;324 int mux, ret;325 326 drm_panel_disable(imx_ldb_ch->panel);327 328 if (imx_ldb_ch == &ldb->channel[0] || dual)329 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;330 if (imx_ldb_ch == &ldb->channel[1] || dual)331 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;332 333 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);334 335 if (dual) {336 clk_disable_unprepare(ldb->clk[0]);337 clk_disable_unprepare(ldb->clk[1]);338 }339 340 if (ldb->lvds_mux) {341 const struct bus_mux *lvds_mux = NULL;342 343 if (imx_ldb_ch == &ldb->channel[0])344 lvds_mux = &ldb->lvds_mux[0];345 else if (imx_ldb_ch == &ldb->channel[1])346 lvds_mux = &ldb->lvds_mux[1];347 348 regmap_read(ldb->regmap, lvds_mux->reg, &mux);349 mux &= lvds_mux->mask;350 mux >>= lvds_mux->shift;351 } else {352 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;353 }354 355 /* set display clock mux back to original input clock */356 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);357 if (ret)358 dev_err(ldb->dev,359 "unable to set di%d parent clock to original parent\n",360 mux);361 362 drm_panel_unprepare(imx_ldb_ch->panel);363}364 365static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,366 struct drm_crtc_state *crtc_state,367 struct drm_connector_state *conn_state)368{369 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);370 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);371 struct drm_display_info *di = &conn_state->connector->display_info;372 u32 bus_format = imx_ldb_ch->bus_format;373 374 /* Bus format description in DT overrides connector display info. */375 if (!bus_format && di->num_bus_formats) {376 bus_format = di->bus_formats[0];377 imx_crtc_state->bus_flags = di->bus_flags;378 } else {379 bus_format = imx_ldb_ch->bus_format;380 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;381 }382 switch (bus_format) {383 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:384 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;385 break;386 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:387 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:388 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;389 break;390 default:391 return -EINVAL;392 }393 394 imx_crtc_state->di_hsync_pin = 2;395 imx_crtc_state->di_vsync_pin = 3;396 397 return 0;398}399 400 401static const struct drm_connector_funcs imx_ldb_connector_funcs = {402 .fill_modes = drm_helper_probe_single_connector_modes,403 .destroy = imx_drm_connector_destroy,404 .reset = drm_atomic_helper_connector_reset,405 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,406 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,407};408 409static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {410 .get_modes = imx_ldb_connector_get_modes,411};412 413static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {414 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,415 .enable = imx_ldb_encoder_enable,416 .disable = imx_ldb_encoder_disable,417 .atomic_check = imx_ldb_encoder_atomic_check,418};419 420static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)421{422 char clkname[16];423 424 snprintf(clkname, sizeof(clkname), "di%d", chno);425 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);426 if (IS_ERR(ldb->clk[chno]))427 return PTR_ERR(ldb->clk[chno]);428 429 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);430 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);431 432 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);433}434 435static int imx_ldb_register(struct drm_device *drm,436 struct imx_ldb_channel *imx_ldb_ch)437{438 struct imx_ldb *ldb = imx_ldb_ch->ldb;439 struct imx_ldb_encoder *ldb_encoder;440 struct drm_connector *connector;441 struct drm_encoder *encoder;442 int ret;443 444 ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,445 encoder, DRM_MODE_ENCODER_LVDS);446 if (IS_ERR(ldb_encoder))447 return PTR_ERR(ldb_encoder);448 449 ldb_encoder->channel = imx_ldb_ch;450 connector = &ldb_encoder->connector;451 encoder = &ldb_encoder->encoder;452 453 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);454 if (ret)455 return ret;456 457 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);458 if (ret)459 return ret;460 461 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {462 ret = imx_ldb_get_clk(ldb, 1);463 if (ret)464 return ret;465 }466 467 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);468 469 if (imx_ldb_ch->bridge) {470 ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);471 if (ret)472 return ret;473 } else {474 /*475 * We want to add the connector whenever there is no bridge476 * that brings its own, not only when there is a panel. For477 * historical reasons, the ldb driver can also work without478 * a panel.479 */480 drm_connector_helper_add(connector,481 &imx_ldb_connector_helper_funcs);482 drm_connector_init_with_ddc(drm, connector,483 &imx_ldb_connector_funcs,484 DRM_MODE_CONNECTOR_LVDS,485 imx_ldb_ch->ddc);486 drm_connector_attach_encoder(connector, encoder);487 }488 489 return 0;490}491 492struct imx_ldb_bit_mapping {493 u32 bus_format;494 u32 datawidth;495 const char * const mapping;496};497 498static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {499 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },500 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },501 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },502};503 504static u32 of_get_bus_format(struct device *dev, struct device_node *np)505{506 const char *bm;507 u32 datawidth = 0;508 int ret, i;509 510 ret = of_property_read_string(np, "fsl,data-mapping", &bm);511 if (ret < 0)512 return ret;513 514 of_property_read_u32(np, "fsl,data-width", &datawidth);515 516 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {517 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&518 datawidth == imx_ldb_bit_mappings[i].datawidth)519 return imx_ldb_bit_mappings[i].bus_format;520 }521 522 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);523 524 return -ENOENT;525}526 527static struct bus_mux imx6q_lvds_mux[2] = {528 {529 .reg = IOMUXC_GPR3,530 .shift = 6,531 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,532 }, {533 .reg = IOMUXC_GPR3,534 .shift = 8,535 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,536 }537};538 539/*540 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",541 * of_match_device will walk through this list and take the first entry542 * matching any of its compatible values. Therefore, the more generic543 * entries (in this case fsl,imx53-ldb) need to be ordered last.544 */545static const struct of_device_id imx_ldb_dt_ids[] = {546 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },547 { .compatible = "fsl,imx53-ldb", .data = NULL, },548 { }549};550MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);551 552static int imx_ldb_panel_ddc(struct device *dev,553 struct imx_ldb_channel *channel, struct device_node *child)554{555 struct device_node *ddc_node;556 int ret;557 558 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);559 if (ddc_node) {560 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);561 of_node_put(ddc_node);562 if (!channel->ddc) {563 dev_warn(dev, "failed to get ddc i2c adapter\n");564 return -EPROBE_DEFER;565 }566 }567 568 if (!channel->ddc) {569 const void *edidp;570 int edid_len;571 572 /* if no DDC available, fallback to hardcoded EDID */573 dev_dbg(dev, "no ddc available\n");574 575 edidp = of_get_property(child, "edid", &edid_len);576 if (edidp) {577 channel->drm_edid = drm_edid_alloc(edidp, edid_len);578 if (!channel->drm_edid)579 return -ENOMEM;580 } else if (!channel->panel) {581 /* fallback to display-timings node */582 ret = of_get_drm_display_mode(child,583 &channel->mode,584 &channel->bus_flags,585 OF_USE_NATIVE_MODE);586 if (!ret)587 channel->mode_valid = 1;588 }589 }590 return 0;591}592 593static int imx_ldb_bind(struct device *dev, struct device *master, void *data)594{595 struct drm_device *drm = data;596 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);597 int ret;598 int i;599 600 for (i = 0; i < 2; i++) {601 struct imx_ldb_channel *channel = &imx_ldb->channel[i];602 603 if (!channel->ldb)604 continue;605 606 ret = imx_ldb_register(drm, channel);607 if (ret)608 return ret;609 }610 611 return 0;612}613 614static const struct component_ops imx_ldb_ops = {615 .bind = imx_ldb_bind,616};617 618static int imx_ldb_probe(struct platform_device *pdev)619{620 struct device *dev = &pdev->dev;621 struct device_node *np = dev->of_node;622 struct device_node *child;623 struct imx_ldb *imx_ldb;624 int dual;625 int ret;626 int i;627 628 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);629 if (!imx_ldb)630 return -ENOMEM;631 632 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");633 if (IS_ERR(imx_ldb->regmap)) {634 dev_err(dev, "failed to get parent regmap\n");635 return PTR_ERR(imx_ldb->regmap);636 }637 638 /* disable LDB by resetting the control register to POR default */639 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);640 641 imx_ldb->dev = dev;642 imx_ldb->lvds_mux = device_get_match_data(dev);643 644 dual = of_property_read_bool(np, "fsl,dual-channel");645 if (dual)646 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;647 648 /*649 * There are three different possible clock mux configurations:650 * i.MX53: ipu1_di0_sel, ipu1_di1_sel651 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel652 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel653 * Map them all to di0_sel...di3_sel.654 */655 for (i = 0; i < 4; i++) {656 char clkname[16];657 658 snprintf(clkname, sizeof(clkname), "di%d_sel", i);659 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);660 if (IS_ERR(imx_ldb->clk_sel[i])) {661 ret = PTR_ERR(imx_ldb->clk_sel[i]);662 imx_ldb->clk_sel[i] = NULL;663 break;664 }665 666 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);667 }668 if (i == 0)669 return ret;670 671 for_each_child_of_node(np, child) {672 struct imx_ldb_channel *channel;673 int bus_format;674 675 ret = of_property_read_u32(child, "reg", &i);676 if (ret || i < 0 || i > 1) {677 ret = -EINVAL;678 goto free_child;679 }680 681 if (!of_device_is_available(child))682 continue;683 684 if (dual && i > 0) {685 dev_warn(dev, "dual-channel mode, ignoring second output\n");686 continue;687 }688 689 channel = &imx_ldb->channel[i];690 channel->ldb = imx_ldb;691 channel->chno = i;692 693 /*694 * The output port is port@4 with an external 4-port mux or695 * port@2 with the internal 2-port mux.696 */697 ret = drm_of_find_panel_or_bridge(child,698 imx_ldb->lvds_mux ? 4 : 2, 0,699 &channel->panel, &channel->bridge);700 if (ret && ret != -ENODEV)701 goto free_child;702 703 /* panel ddc only if there is no bridge */704 if (!channel->bridge) {705 ret = imx_ldb_panel_ddc(dev, channel, child);706 if (ret)707 goto free_child;708 }709 710 bus_format = of_get_bus_format(dev, child);711 if (bus_format == -EINVAL) {712 /*713 * If no bus format was specified in the device tree,714 * we can still get it from the connected panel later.715 */716 if (channel->panel && channel->panel->funcs &&717 channel->panel->funcs->get_modes)718 bus_format = 0;719 }720 if (bus_format < 0) {721 dev_err(dev, "could not determine data mapping: %d\n",722 bus_format);723 ret = bus_format;724 goto free_child;725 }726 channel->bus_format = bus_format;727 channel->child = child;728 }729 730 platform_set_drvdata(pdev, imx_ldb);731 732 return component_add(&pdev->dev, &imx_ldb_ops);733 734free_child:735 of_node_put(child);736 return ret;737}738 739static void imx_ldb_remove(struct platform_device *pdev)740{741 struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);742 int i;743 744 for (i = 0; i < 2; i++) {745 struct imx_ldb_channel *channel = &imx_ldb->channel[i];746 747 drm_edid_free(channel->drm_edid);748 i2c_put_adapter(channel->ddc);749 }750 751 component_del(&pdev->dev, &imx_ldb_ops);752}753 754static struct platform_driver imx_ldb_driver = {755 .probe = imx_ldb_probe,756 .remove_new = imx_ldb_remove,757 .driver = {758 .of_match_table = imx_ldb_dt_ids,759 .name = DRIVER_NAME,760 },761};762 763module_platform_driver(imx_ldb_driver);764 765MODULE_DESCRIPTION("i.MX LVDS driver");766MODULE_AUTHOR("Sascha Hauer, Pengutronix");767MODULE_LICENSE("GPL");768MODULE_ALIAS("platform:" DRIVER_NAME);769