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1// SPDX-License-Identifier: GPL-2.0+2/*3 * i.MX IPUv3 Graphics driver4 *5 * Copyright (C) 2011 Sascha Hauer, Pengutronix6 */7 8#include <linux/clk.h>9#include <linux/component.h>10#include <linux/device.h>11#include <linux/dma-mapping.h>12#include <linux/errno.h>13#include <linux/export.h>14#include <linux/module.h>15#include <linux/platform_device.h>16 17#include <video/imx-ipu-v3.h>18 19#include <drm/drm_atomic.h>20#include <drm/drm_atomic_helper.h>21#include <drm/drm_gem_dma_helper.h>22#include <drm/drm_managed.h>23#include <drm/drm_probe_helper.h>24#include <drm/drm_vblank.h>25 26#include "imx-drm.h"27#include "ipuv3-plane.h"28 29#define DRIVER_DESC "i.MX IPUv3 Graphics"30 31struct ipu_crtc {32 struct device *dev;33 struct drm_crtc base;34 35 /* plane[0] is the full plane, plane[1] is the partial plane */36 struct ipu_plane *plane[2];37 38 struct ipu_dc *dc;39 struct ipu_di *di;40 int irq;41 struct drm_pending_vblank_event *event;42};43 44static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)45{46 return container_of(crtc, struct ipu_crtc, base);47}48 49static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,50 struct drm_atomic_state *state)51{52 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);53 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);54 55 ipu_prg_enable(ipu);56 ipu_dc_enable(ipu);57 ipu_dc_enable_channel(ipu_crtc->dc);58 ipu_di_enable(ipu_crtc->di);59}60 61static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,62 struct drm_crtc_state *old_crtc_state)63{64 bool disable_partial = false;65 bool disable_full = false;66 struct drm_plane *plane;67 68 drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {69 if (plane == &ipu_crtc->plane[0]->base)70 disable_full = true;71 if (ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)72 disable_partial = true;73 }74 75 if (disable_partial)76 ipu_plane_disable(ipu_crtc->plane[1], true);77 if (disable_full)78 ipu_plane_disable(ipu_crtc->plane[0], true);79}80 81static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,82 struct drm_atomic_state *state)83{84 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,85 crtc);86 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);87 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);88 89 ipu_dc_disable_channel(ipu_crtc->dc);90 ipu_di_disable(ipu_crtc->di);91 /*92 * Planes must be disabled before DC clock is removed, as otherwise the93 * attached IDMACs will be left in undefined state, possibly hanging94 * the IPU or even system.95 */96 ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);97 ipu_dc_disable(ipu);98 ipu_prg_disable(ipu);99 100 drm_crtc_vblank_off(crtc);101 102 spin_lock_irq(&crtc->dev->event_lock);103 if (crtc->state->event && !crtc->state->active) {104 drm_crtc_send_vblank_event(crtc, crtc->state->event);105 crtc->state->event = NULL;106 }107 spin_unlock_irq(&crtc->dev->event_lock);108}109 110static void imx_drm_crtc_reset(struct drm_crtc *crtc)111{112 struct imx_crtc_state *state;113 114 if (crtc->state)115 __drm_atomic_helper_crtc_destroy_state(crtc->state);116 117 kfree(to_imx_crtc_state(crtc->state));118 crtc->state = NULL;119 120 state = kzalloc(sizeof(*state), GFP_KERNEL);121 if (state)122 __drm_atomic_helper_crtc_reset(crtc, &state->base);123}124 125static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)126{127 struct imx_crtc_state *state;128 129 state = kzalloc(sizeof(*state), GFP_KERNEL);130 if (!state)131 return NULL;132 133 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);134 135 WARN_ON(state->base.crtc != crtc);136 state->base.crtc = crtc;137 138 return &state->base;139}140 141static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,142 struct drm_crtc_state *state)143{144 __drm_atomic_helper_crtc_destroy_state(state);145 kfree(to_imx_crtc_state(state));146}147 148static int ipu_enable_vblank(struct drm_crtc *crtc)149{150 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);151 152 enable_irq(ipu_crtc->irq);153 154 return 0;155}156 157static void ipu_disable_vblank(struct drm_crtc *crtc)158{159 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);160 161 disable_irq_nosync(ipu_crtc->irq);162}163 164static const struct drm_crtc_funcs ipu_crtc_funcs = {165 .set_config = drm_atomic_helper_set_config,166 .page_flip = drm_atomic_helper_page_flip,167 .reset = imx_drm_crtc_reset,168 .atomic_duplicate_state = imx_drm_crtc_duplicate_state,169 .atomic_destroy_state = imx_drm_crtc_destroy_state,170 .enable_vblank = ipu_enable_vblank,171 .disable_vblank = ipu_disable_vblank,172};173 174static irqreturn_t ipu_irq_handler(int irq, void *dev_id)175{176 struct ipu_crtc *ipu_crtc = dev_id;177 struct drm_crtc *crtc = &ipu_crtc->base;178 unsigned long flags;179 int i;180 181 drm_crtc_handle_vblank(crtc);182 183 if (ipu_crtc->event) {184 for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {185 struct ipu_plane *plane = ipu_crtc->plane[i];186 187 if (!plane)188 continue;189 190 if (ipu_plane_atomic_update_pending(&plane->base))191 break;192 }193 194 if (i == ARRAY_SIZE(ipu_crtc->plane)) {195 spin_lock_irqsave(&crtc->dev->event_lock, flags);196 drm_crtc_send_vblank_event(crtc, ipu_crtc->event);197 ipu_crtc->event = NULL;198 drm_crtc_vblank_put(crtc);199 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);200 }201 }202 203 return IRQ_HANDLED;204}205 206static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,207 const struct drm_display_mode *mode,208 struct drm_display_mode *adjusted_mode)209{210 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);211 struct videomode vm;212 int ret;213 214 drm_display_mode_to_videomode(adjusted_mode, &vm);215 216 ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);217 if (ret)218 return false;219 220 if ((vm.vsync_len == 0) || (vm.hsync_len == 0))221 return false;222 223 drm_display_mode_from_videomode(&vm, adjusted_mode);224 225 return true;226}227 228static int ipu_crtc_atomic_check(struct drm_crtc *crtc,229 struct drm_atomic_state *state)230{231 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,232 crtc);233 u32 primary_plane_mask = drm_plane_mask(crtc->primary);234 235 if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)236 return -EINVAL;237 238 return 0;239}240 241static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,242 struct drm_atomic_state *state)243{244 drm_crtc_vblank_on(crtc);245}246 247static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,248 struct drm_atomic_state *state)249{250 spin_lock_irq(&crtc->dev->event_lock);251 if (crtc->state->event) {252 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);253 254 WARN_ON(drm_crtc_vblank_get(crtc));255 ipu_crtc->event = crtc->state->event;256 crtc->state->event = NULL;257 }258 spin_unlock_irq(&crtc->dev->event_lock);259}260 261static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)262{263 struct drm_device *dev = crtc->dev;264 struct drm_encoder *encoder;265 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);266 struct drm_display_mode *mode = &crtc->state->adjusted_mode;267 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);268 struct ipu_di_signal_cfg sig_cfg = {};269 unsigned long encoder_types = 0;270 271 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,272 mode->hdisplay);273 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,274 mode->vdisplay);275 276 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {277 if (encoder->crtc == crtc)278 encoder_types |= BIT(encoder->encoder_type);279 }280 281 dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",282 __func__, encoder_types);283 284 /*285 * If we have DAC or LDB, then we need the IPU DI clock to be286 * the same as the LDB DI clock. For TVDAC, derive the IPU DI287 * clock from 27 MHz TVE_DI clock, but allow to divide it.288 */289 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |290 BIT(DRM_MODE_ENCODER_LVDS)))291 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;292 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))293 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;294 else295 sig_cfg.clkflags = 0;296 297 sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);298 /* Default to driving pixel data on negative clock edges */299 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &300 DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE);301 sig_cfg.bus_format = imx_crtc_state->bus_format;302 sig_cfg.v_to_h_sync = 0;303 sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;304 sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;305 306 drm_display_mode_to_videomode(mode, &sig_cfg.mode);307 if (!IS_ALIGNED(sig_cfg.mode.hactive, 8)) {308 unsigned int new_hactive = ALIGN(sig_cfg.mode.hactive, 8);309 310 dev_warn(ipu_crtc->dev, "8-pixel align hactive %d -> %d\n",311 sig_cfg.mode.hactive, new_hactive);312 313 sig_cfg.mode.hfront_porch -= new_hactive - sig_cfg.mode.hactive;314 sig_cfg.mode.hactive = new_hactive;315 }316 317 ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,318 mode->flags & DRM_MODE_FLAG_INTERLACE,319 imx_crtc_state->bus_format, sig_cfg.mode.hactive);320 ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);321}322 323static const struct drm_crtc_helper_funcs ipu_helper_funcs = {324 .mode_fixup = ipu_crtc_mode_fixup,325 .mode_set_nofb = ipu_crtc_mode_set_nofb,326 .atomic_check = ipu_crtc_atomic_check,327 .atomic_begin = ipu_crtc_atomic_begin,328 .atomic_flush = ipu_crtc_atomic_flush,329 .atomic_disable = ipu_crtc_atomic_disable,330 .atomic_enable = ipu_crtc_atomic_enable,331};332 333static void ipu_put_resources(struct drm_device *dev, void *ptr)334{335 struct ipu_crtc *ipu_crtc = ptr;336 337 if (!IS_ERR_OR_NULL(ipu_crtc->dc))338 ipu_dc_put(ipu_crtc->dc);339 if (!IS_ERR_OR_NULL(ipu_crtc->di))340 ipu_di_put(ipu_crtc->di);341}342 343static int ipu_get_resources(struct drm_device *dev, struct ipu_crtc *ipu_crtc,344 struct ipu_client_platformdata *pdata)345{346 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);347 int ret;348 349 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);350 if (IS_ERR(ipu_crtc->dc))351 return PTR_ERR(ipu_crtc->dc);352 353 ret = drmm_add_action_or_reset(dev, ipu_put_resources, ipu_crtc);354 if (ret)355 return ret;356 357 ipu_crtc->di = ipu_di_get(ipu, pdata->di);358 if (IS_ERR(ipu_crtc->di))359 return PTR_ERR(ipu_crtc->di);360 361 return 0;362}363 364static int ipu_drm_bind(struct device *dev, struct device *master, void *data)365{366 struct ipu_client_platformdata *pdata = dev->platform_data;367 struct ipu_soc *ipu = dev_get_drvdata(dev->parent);368 struct drm_device *drm = data;369 struct ipu_plane *primary_plane;370 struct ipu_crtc *ipu_crtc;371 struct drm_crtc *crtc;372 int dp = -EINVAL;373 int ret;374 375 if (pdata->dp >= 0)376 dp = IPU_DP_FLOW_SYNC_BG;377 primary_plane = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,378 DRM_PLANE_TYPE_PRIMARY);379 if (IS_ERR(primary_plane))380 return PTR_ERR(primary_plane);381 382 ipu_crtc = drmm_crtc_alloc_with_planes(drm, struct ipu_crtc, base,383 &primary_plane->base, NULL,384 &ipu_crtc_funcs, NULL);385 if (IS_ERR(ipu_crtc))386 return PTR_ERR(ipu_crtc);387 388 ipu_crtc->dev = dev;389 ipu_crtc->plane[0] = primary_plane;390 391 crtc = &ipu_crtc->base;392 crtc->port = pdata->of_node;393 drm_crtc_helper_add(crtc, &ipu_helper_funcs);394 395 ret = ipu_get_resources(drm, ipu_crtc, pdata);396 if (ret) {397 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",398 ret);399 return ret;400 }401 402 /* If this crtc is using the DP, add an overlay plane */403 if (pdata->dp >= 0 && pdata->dma[1] > 0) {404 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],405 IPU_DP_FLOW_SYNC_FG,406 drm_crtc_mask(&ipu_crtc->base),407 DRM_PLANE_TYPE_OVERLAY);408 if (IS_ERR(ipu_crtc->plane[1]))409 ipu_crtc->plane[1] = NULL;410 }411 412 ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);413 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,414 "imx_drm", ipu_crtc);415 if (ret < 0) {416 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);417 return ret;418 }419 /* Only enable IRQ when we actually need it to trigger work. */420 disable_irq(ipu_crtc->irq);421 422 return 0;423}424 425static const struct component_ops ipu_crtc_ops = {426 .bind = ipu_drm_bind,427};428 429static int ipu_drm_probe(struct platform_device *pdev)430{431 struct device *dev = &pdev->dev;432 int ret;433 434 if (!dev->platform_data)435 return -EINVAL;436 437 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));438 if (ret)439 return ret;440 441 return component_add(dev, &ipu_crtc_ops);442}443 444static void ipu_drm_remove(struct platform_device *pdev)445{446 component_del(&pdev->dev, &ipu_crtc_ops);447}448 449struct platform_driver ipu_drm_driver = {450 .driver = {451 .name = "imx-ipuv3-crtc",452 },453 .probe = ipu_drm_probe,454 .remove_new = ipu_drm_remove,455};456