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1/* SPDX-License-Identifier: GPL-2.0 */2//3// Ingenic JZ47xx KMS driver - Register definitions and private API4//5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H9 10#include <linux/bitops.h>11#include <linux/types.h>12 13#define JZ_REG_LCD_CFG 0x0014#define JZ_REG_LCD_VSYNC 0x0415#define JZ_REG_LCD_HSYNC 0x0816#define JZ_REG_LCD_VAT 0x0C17#define JZ_REG_LCD_DAH 0x1018#define JZ_REG_LCD_DAV 0x1419#define JZ_REG_LCD_PS 0x1820#define JZ_REG_LCD_CLS 0x1C21#define JZ_REG_LCD_SPL 0x2022#define JZ_REG_LCD_REV 0x2423#define JZ_REG_LCD_CTRL 0x3024#define JZ_REG_LCD_STATE 0x3425#define JZ_REG_LCD_IID 0x3826#define JZ_REG_LCD_DA0 0x4027#define JZ_REG_LCD_SA0 0x4428#define JZ_REG_LCD_FID0 0x4829#define JZ_REG_LCD_CMD0 0x4C30#define JZ_REG_LCD_DA1 0x5031#define JZ_REG_LCD_SA1 0x5432#define JZ_REG_LCD_FID1 0x5833#define JZ_REG_LCD_CMD1 0x5C34#define JZ_REG_LCD_RGBC 0x9035#define JZ_REG_LCD_OSDC 0x10036#define JZ_REG_LCD_OSDCTRL 0x10437#define JZ_REG_LCD_OSDS 0x10838#define JZ_REG_LCD_BGC 0x10c39#define JZ_REG_LCD_KEY0 0x11040#define JZ_REG_LCD_KEY1 0x11441#define JZ_REG_LCD_ALPHA 0x11842#define JZ_REG_LCD_IPUR 0x11c43#define JZ_REG_LCD_XYP0 0x12044#define JZ_REG_LCD_XYP1 0x12445#define JZ_REG_LCD_SIZE0 0x12846#define JZ_REG_LCD_SIZE1 0x12c47#define JZ_REG_LCD_PCFG 0x2c048 49#define JZ_LCD_CFG_SLCD BIT(31)50#define JZ_LCD_CFG_DESCRIPTOR_8 BIT(28)51#define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN BIT(25)52#define JZ_LCD_CFG_PS_DISABLE BIT(23)53#define JZ_LCD_CFG_CLS_DISABLE BIT(22)54#define JZ_LCD_CFG_SPL_DISABLE BIT(21)55#define JZ_LCD_CFG_REV_DISABLE BIT(20)56#define JZ_LCD_CFG_HSYNCM BIT(19)57#define JZ_LCD_CFG_PCLKM BIT(18)58#define JZ_LCD_CFG_INV BIT(17)59#define JZ_LCD_CFG_SYNC_DIR BIT(16)60#define JZ_LCD_CFG_PS_POLARITY BIT(15)61#define JZ_LCD_CFG_CLS_POLARITY BIT(14)62#define JZ_LCD_CFG_SPL_POLARITY BIT(13)63#define JZ_LCD_CFG_REV_POLARITY BIT(12)64#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)65#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)66#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)67#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)68#define JZ_LCD_CFG_18_BIT BIT(7)69#define JZ_LCD_CFG_24_BIT BIT(6)70#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))71 72#define JZ_LCD_CFG_MODE_GENERIC_16BIT 073#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)74#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)75 76#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 177#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 278#define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 379 80#define JZ_LCD_CFG_MODE_TV_OUT_P 481#define JZ_LCD_CFG_MODE_TV_OUT_I 682 83#define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 884#define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 985#define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 1086#define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 1187 88#define JZ_LCD_CFG_MODE_8BIT_SERIAL 1289#define JZ_LCD_CFG_MODE_LCM 1390 91#define JZ_LCD_VSYNC_VPS_OFFSET 1692#define JZ_LCD_VSYNC_VPE_OFFSET 093 94#define JZ_LCD_HSYNC_HPS_OFFSET 1695#define JZ_LCD_HSYNC_HPE_OFFSET 096 97#define JZ_LCD_VAT_HT_OFFSET 1698#define JZ_LCD_VAT_VT_OFFSET 099 100#define JZ_LCD_DAH_HDS_OFFSET 16101#define JZ_LCD_DAH_HDE_OFFSET 0102 103#define JZ_LCD_DAV_VDS_OFFSET 16104#define JZ_LCD_DAV_VDE_OFFSET 0105 106#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)107#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)108#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)109#define JZ_LCD_CTRL_BURST_32 (0x3 << 28)110#define JZ_LCD_CTRL_BURST_64 (0x4 << 28)111#define JZ_LCD_CTRL_BURST_MASK (0x7 << 28)112#define JZ_LCD_CTRL_RGB555 BIT(27)113#define JZ_LCD_CTRL_OFUP BIT(26)114#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)115#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)116#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)117#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)118#define JZ_LCD_CTRL_EOF_IRQ BIT(13)119#define JZ_LCD_CTRL_SOF_IRQ BIT(12)120#define JZ_LCD_CTRL_OFU_IRQ BIT(11)121#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)122#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)123#define JZ_LCD_CTRL_DD_IRQ BIT(8)124#define JZ_LCD_CTRL_QDD_IRQ BIT(7)125#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)126#define JZ_LCD_CTRL_LSB_FISRT BIT(5)127#define JZ_LCD_CTRL_DISABLE BIT(4)128#define JZ_LCD_CTRL_ENABLE BIT(3)129#define JZ_LCD_CTRL_BPP_1 0x0130#define JZ_LCD_CTRL_BPP_2 0x1131#define JZ_LCD_CTRL_BPP_4 0x2132#define JZ_LCD_CTRL_BPP_8 0x3133#define JZ_LCD_CTRL_BPP_15_16 0x4134#define JZ_LCD_CTRL_BPP_18_24 0x5135#define JZ_LCD_CTRL_BPP_24_COMP 0x6136#define JZ_LCD_CTRL_BPP_30 0x7137#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)138 139#define JZ_LCD_CMD_SOF_IRQ BIT(31)140#define JZ_LCD_CMD_EOF_IRQ BIT(30)141#define JZ_LCD_CMD_ENABLE_PAL BIT(28)142#define JZ_LCD_CMD_FRM_ENABLE BIT(26)143 144#define JZ_LCD_SYNC_MASK 0x3ff145 146#define JZ_LCD_STATE_EOF_IRQ BIT(5)147#define JZ_LCD_STATE_SOF_IRQ BIT(4)148#define JZ_LCD_STATE_DISABLED BIT(0)149 150#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4)151#define JZ_LCD_RGBC_ODD_RBG (0x1 << 4)152#define JZ_LCD_RGBC_ODD_GRB (0x2 << 4)153#define JZ_LCD_RGBC_ODD_GBR (0x3 << 4)154#define JZ_LCD_RGBC_ODD_BRG (0x4 << 4)155#define JZ_LCD_RGBC_ODD_BGR (0x5 << 4)156#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0)157#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0)158#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0)159#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0)160#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0)161#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0)162 163#define JZ_LCD_OSDC_OSDEN BIT(0)164#define JZ_LCD_OSDC_ALPHAEN BIT(2)165#define JZ_LCD_OSDC_F0EN BIT(3)166#define JZ_LCD_OSDC_F1EN BIT(4)167 168#define JZ_LCD_OSDCTRL_IPU BIT(15)169#define JZ_LCD_OSDCTRL_RGB555 BIT(4)170#define JZ_LCD_OSDCTRL_CHANGE BIT(3)171#define JZ_LCD_OSDCTRL_BPP_15_16 0x4172#define JZ_LCD_OSDCTRL_BPP_18_24 0x5173#define JZ_LCD_OSDCTRL_BPP_24_COMP 0x6174#define JZ_LCD_OSDCTRL_BPP_30 0x7175#define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7)176 177#define JZ_LCD_OSDS_READY BIT(0)178 179#define JZ_LCD_IPUR_IPUREN BIT(31)180#define JZ_LCD_IPUR_IPUR_LSB 0181 182#define JZ_LCD_XYP01_XPOS_LSB 0183#define JZ_LCD_XYP01_YPOS_LSB 16184 185#define JZ_LCD_SIZE01_WIDTH_LSB 0186#define JZ_LCD_SIZE01_HEIGHT_LSB 16187 188#define JZ_LCD_DESSIZE_ALPHA_OFFSET 24189#define JZ_LCD_DESSIZE_HEIGHT_MASK GENMASK(23, 12)190#define JZ_LCD_DESSIZE_WIDTH_MASK GENMASK(11, 0)191 192#define JZ_LCD_CPOS_BPP_15_16 (4 << 27)193#define JZ_LCD_CPOS_BPP_18_24 (5 << 27)194#define JZ_LCD_CPOS_BPP_30 (7 << 27)195#define JZ_LCD_CPOS_RGB555 BIT(30)196#define JZ_LCD_CPOS_PREMULTIPLY_LCD BIT(26)197#define JZ_LCD_CPOS_COEFFICIENT_OFFSET 24198#define JZ_LCD_CPOS_COEFFICIENT_0 0199#define JZ_LCD_CPOS_COEFFICIENT_1 1200#define JZ_LCD_CPOS_COEFFICIENT_ALPHA1 2201#define JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 3202 203#define JZ_LCD_RGBC_RGB_PADDING BIT(15)204#define JZ_LCD_RGBC_RGB_PADDING_FIRST BIT(14)205#define JZ_LCD_RGBC_422 BIT(8)206#define JZ_LCD_RGBC_RGB_FORMAT_ENABLE BIT(7)207 208#define JZ_LCD_PCFG_PRI_MODE BIT(31)209#define JZ_LCD_PCFG_HP_BST_4 (0 << 28)210#define JZ_LCD_PCFG_HP_BST_8 (1 << 28)211#define JZ_LCD_PCFG_HP_BST_16 (2 << 28)212#define JZ_LCD_PCFG_HP_BST_32 (3 << 28)213#define JZ_LCD_PCFG_HP_BST_64 (4 << 28)214#define JZ_LCD_PCFG_HP_BST_16_CONT (5 << 28)215#define JZ_LCD_PCFG_HP_BST_DISABLE (7 << 28)216#define JZ_LCD_PCFG_THRESHOLD2_OFFSET 18217#define JZ_LCD_PCFG_THRESHOLD1_OFFSET 9218#define JZ_LCD_PCFG_THRESHOLD0_OFFSET 0219 220struct device;221struct drm_plane;222struct drm_plane_state;223struct platform_driver;224 225void ingenic_drm_plane_config(struct device *dev,226 struct drm_plane *plane, u32 fourcc);227void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);228bool ingenic_drm_map_noncoherent(const struct device *dev);229 230extern struct platform_driver *ingenic_ipu_driver_ptr;231 232#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */233