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1/* SPDX-License-Identifier: GPL-2.0-only2 *3 * Copyright © 2018-2020 Intel Corporation4 */5 6#ifndef __KMB_PLANE_H__7#define __KMB_PLANE_H__8 9#include <drm/drm_fourcc.h>10#include <drm/drm_plane.h>11 12#define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \13 (LAYER0_DMA_FIFO_OVERFLOW) | \14 (LAYER0_DMA_CB_FIFO_OVERFLOW) | \15 (LAYER0_DMA_CB_FIFO_UNDERFLOW) | \16 (LAYER0_DMA_CR_FIFO_OVERFLOW) | \17 (LAYER0_DMA_CR_FIFO_UNDERFLOW))18 19#define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \20 (LAYER1_DMA_FIFO_OVERFLOW) | \21 (LAYER1_DMA_CB_FIFO_OVERFLOW) | \22 (LAYER1_DMA_CB_FIFO_UNDERFLOW) | \23 (LAYER1_DMA_CR_FIFO_OVERFLOW) | \24 (LAYER1_DMA_CR_FIFO_UNDERFLOW))25 26#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW)27#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW)28#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR)29#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR)30#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR)31#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)32#define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \33 | LCD_INT_GL0_ERR | LCD_INT_GL1_ERR)34 35#define POSSIBLE_CRTCS 136#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane)37 38#define POSSIBLE_CRTCS 139#define KMB_MAX_PLANES 240 41enum layer_id {42 LAYER_0,43 LAYER_1,44 LAYER_2,45 LAYER_3,46 /* KMB_MAX_PLANES */47};48 49enum sub_plane_id {50 Y_PLANE,51 U_PLANE,52 V_PLANE,53 MAX_SUB_PLANES,54};55 56struct kmb_plane {57 struct drm_plane base_plane;58 unsigned char id;59};60 61struct layer_status {62 bool disable;63 u32 ctrl;64};65 66struct disp_cfg {67 unsigned int width;68 unsigned int height;69 unsigned int format;70};71 72struct kmb_plane *kmb_plane_init(struct drm_device *drm);73void kmb_plane_destroy(struct drm_plane *plane);74#endif /* __KMB_PLANE_H__ */75