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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright 2010-2017 ARM Limited. All rights reserved.3 * Copyright 2017-2019 Qiang Yu <yuq825@gmail.com>4 */5 6#ifndef __LIMA_REGS_H__7#define __LIMA_REGS_H__8 9/* This file's register definition is collected from the10 * official ARM Mali Utgard GPU kernel driver source code11 */12 13/* PMU regs */14#define LIMA_PMU_POWER_UP 0x0015#define LIMA_PMU_POWER_DOWN 0x0416#define LIMA_PMU_POWER_GP0_MASK BIT(0)17#define LIMA_PMU_POWER_L2_MASK BIT(1)18#define LIMA_PMU_POWER_PP_MASK(i) BIT(2 + i)19 20/*21 * On Mali450 each block automatically starts up its corresponding L222 * and the PPs are not fully independent controllable.23 * Instead PP0, PP1-3 and PP4-7 can be turned on or off.24 */25#define LIMA450_PMU_POWER_PP0_MASK BIT(1)26#define LIMA450_PMU_POWER_PP13_MASK BIT(2)27#define LIMA450_PMU_POWER_PP47_MASK BIT(3)28 29#define LIMA_PMU_STATUS 0x0830#define LIMA_PMU_INT_MASK 0x0C31#define LIMA_PMU_INT_RAWSTAT 0x1032#define LIMA_PMU_INT_CLEAR 0x1833#define LIMA_PMU_INT_CMD_MASK BIT(0)34#define LIMA_PMU_SW_DELAY 0x1C35 36/* L2 cache regs */37#define LIMA_L2_CACHE_SIZE 0x000438#define LIMA_L2_CACHE_STATUS 0x000839#define LIMA_L2_CACHE_STATUS_COMMAND_BUSY BIT(0)40#define LIMA_L2_CACHE_STATUS_DATA_BUSY BIT(1)41#define LIMA_L2_CACHE_COMMAND 0x001042#define LIMA_L2_CACHE_COMMAND_CLEAR_ALL BIT(0)43#define LIMA_L2_CACHE_CLEAR_PAGE 0x001444#define LIMA_L2_CACHE_MAX_READS 0x001845#define LIMA_L2_CACHE_ENABLE 0x001C46#define LIMA_L2_CACHE_ENABLE_ACCESS BIT(0)47#define LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1)48#define LIMA_L2_CACHE_PERFCNT_SRC0 0x002049#define LIMA_L2_CACHE_PERFCNT_VAL0 0x002450#define LIMA_L2_CACHE_PERFCNT_SRC1 0x002851#define LIMA_L2_CACHE_ERFCNT_VAL1 0x002C52 53/* GP regs */54#define LIMA_GP_VSCL_START_ADDR 0x0055#define LIMA_GP_VSCL_END_ADDR 0x0456#define LIMA_GP_PLBUCL_START_ADDR 0x0857#define LIMA_GP_PLBUCL_END_ADDR 0x0c58#define LIMA_GP_PLBU_ALLOC_START_ADDR 0x1059#define LIMA_GP_PLBU_ALLOC_END_ADDR 0x1460#define LIMA_GP_CMD 0x2061#define LIMA_GP_CMD_START_VS BIT(0)62#define LIMA_GP_CMD_START_PLBU BIT(1)63#define LIMA_GP_CMD_UPDATE_PLBU_ALLOC BIT(4)64#define LIMA_GP_CMD_RESET BIT(5)65#define LIMA_GP_CMD_FORCE_HANG BIT(6)66#define LIMA_GP_CMD_STOP_BUS BIT(9)67#define LIMA_GP_CMD_SOFT_RESET BIT(10)68#define LIMA_GP_INT_RAWSTAT 0x2469#define LIMA_GP_INT_CLEAR 0x2870#define LIMA_GP_INT_MASK 0x2C71#define LIMA_GP_INT_STAT 0x3072#define LIMA_GP_IRQ_VS_END_CMD_LST BIT(0)73#define LIMA_GP_IRQ_PLBU_END_CMD_LST BIT(1)74#define LIMA_GP_IRQ_PLBU_OUT_OF_MEM BIT(2)75#define LIMA_GP_IRQ_VS_SEM_IRQ BIT(3)76#define LIMA_GP_IRQ_PLBU_SEM_IRQ BIT(4)77#define LIMA_GP_IRQ_HANG BIT(5)78#define LIMA_GP_IRQ_FORCE_HANG BIT(6)79#define LIMA_GP_IRQ_PERF_CNT_0_LIMIT BIT(7)80#define LIMA_GP_IRQ_PERF_CNT_1_LIMIT BIT(8)81#define LIMA_GP_IRQ_WRITE_BOUND_ERR BIT(9)82#define LIMA_GP_IRQ_SYNC_ERROR BIT(10)83#define LIMA_GP_IRQ_AXI_BUS_ERROR BIT(11)84#define LIMA_GP_IRQ_AXI_BUS_STOPPED BIT(12)85#define LIMA_GP_IRQ_VS_INVALID_CMD BIT(13)86#define LIMA_GP_IRQ_PLB_INVALID_CMD BIT(14)87#define LIMA_GP_IRQ_RESET_COMPLETED BIT(19)88#define LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW BIT(20)89#define LIMA_GP_IRQ_SEMAPHORE_OVERFLOW BIT(21)90#define LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS BIT(22)91#define LIMA_GP_WRITE_BOUND_LOW 0x3492#define LIMA_GP_PERF_CNT_0_ENABLE 0x3C93#define LIMA_GP_PERF_CNT_1_ENABLE 0x4094#define LIMA_GP_PERF_CNT_0_SRC 0x4495#define LIMA_GP_PERF_CNT_1_SRC 0x4896#define LIMA_GP_PERF_CNT_0_VALUE 0x4C97#define LIMA_GP_PERF_CNT_1_VALUE 0x5098#define LIMA_GP_PERF_CNT_0_LIMIT 0x5499#define LIMA_GP_STATUS 0x68100#define LIMA_GP_STATUS_VS_ACTIVE BIT(1)101#define LIMA_GP_STATUS_BUS_STOPPED BIT(2)102#define LIMA_GP_STATUS_PLBU_ACTIVE BIT(3)103#define LIMA_GP_STATUS_BUS_ERROR BIT(6)104#define LIMA_GP_STATUS_WRITE_BOUND_ERR BIT(8)105#define LIMA_GP_VERSION 0x6C106#define LIMA_GP_VSCL_START_ADDR_READ 0x80107#define LIMA_GP_PLBCL_START_ADDR_READ 0x84108#define LIMA_GP_CONTR_AXI_BUS_ERROR_STAT 0x94109 110#define LIMA_GP_IRQ_MASK_ALL \111 ( \112 LIMA_GP_IRQ_VS_END_CMD_LST | \113 LIMA_GP_IRQ_PLBU_END_CMD_LST | \114 LIMA_GP_IRQ_PLBU_OUT_OF_MEM | \115 LIMA_GP_IRQ_VS_SEM_IRQ | \116 LIMA_GP_IRQ_PLBU_SEM_IRQ | \117 LIMA_GP_IRQ_HANG | \118 LIMA_GP_IRQ_FORCE_HANG | \119 LIMA_GP_IRQ_PERF_CNT_0_LIMIT | \120 LIMA_GP_IRQ_PERF_CNT_1_LIMIT | \121 LIMA_GP_IRQ_WRITE_BOUND_ERR | \122 LIMA_GP_IRQ_SYNC_ERROR | \123 LIMA_GP_IRQ_AXI_BUS_ERROR | \124 LIMA_GP_IRQ_AXI_BUS_STOPPED | \125 LIMA_GP_IRQ_VS_INVALID_CMD | \126 LIMA_GP_IRQ_PLB_INVALID_CMD | \127 LIMA_GP_IRQ_RESET_COMPLETED | \128 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \129 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW | \130 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)131 132#define LIMA_GP_IRQ_MASK_ERROR \133 ( \134 LIMA_GP_IRQ_PLBU_OUT_OF_MEM | \135 LIMA_GP_IRQ_FORCE_HANG | \136 LIMA_GP_IRQ_WRITE_BOUND_ERR | \137 LIMA_GP_IRQ_SYNC_ERROR | \138 LIMA_GP_IRQ_AXI_BUS_ERROR | \139 LIMA_GP_IRQ_VS_INVALID_CMD | \140 LIMA_GP_IRQ_PLB_INVALID_CMD | \141 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \142 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW | \143 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)144 145#define LIMA_GP_IRQ_MASK_USED \146 ( \147 LIMA_GP_IRQ_VS_END_CMD_LST | \148 LIMA_GP_IRQ_PLBU_END_CMD_LST | \149 LIMA_GP_IRQ_MASK_ERROR)150 151/* PP regs */152#define LIMA_PP_FRAME 0x0000153#define LIMA_PP_RSW 0x0004154#define LIMA_PP_STACK 0x0030155#define LIMA_PP_STACK_SIZE 0x0034156#define LIMA_PP_ORIGIN_OFFSET_X 0x0040157#define LIMA_PP_WB(i) (0x0100 * (i + 1))158#define LIMA_PP_WB_SOURCE_SELECT 0x0000159#define LIMA_PP_WB_SOURCE_ADDR 0x0004160 161#define LIMA_PP_VERSION 0x1000162#define LIMA_PP_CURRENT_REND_LIST_ADDR 0x1004163#define LIMA_PP_STATUS 0x1008164#define LIMA_PP_STATUS_RENDERING_ACTIVE BIT(0)165#define LIMA_PP_STATUS_BUS_STOPPED BIT(4)166#define LIMA_PP_CTRL 0x100c167#define LIMA_PP_CTRL_STOP_BUS BIT(0)168#define LIMA_PP_CTRL_FLUSH_CACHES BIT(3)169#define LIMA_PP_CTRL_FORCE_RESET BIT(5)170#define LIMA_PP_CTRL_START_RENDERING BIT(6)171#define LIMA_PP_CTRL_SOFT_RESET BIT(7)172#define LIMA_PP_INT_RAWSTAT 0x1020173#define LIMA_PP_INT_CLEAR 0x1024174#define LIMA_PP_INT_MASK 0x1028175#define LIMA_PP_INT_STATUS 0x102c176#define LIMA_PP_IRQ_END_OF_FRAME BIT(0)177#define LIMA_PP_IRQ_END_OF_TILE BIT(1)178#define LIMA_PP_IRQ_HANG BIT(2)179#define LIMA_PP_IRQ_FORCE_HANG BIT(3)180#define LIMA_PP_IRQ_BUS_ERROR BIT(4)181#define LIMA_PP_IRQ_BUS_STOP BIT(5)182#define LIMA_PP_IRQ_CNT_0_LIMIT BIT(6)183#define LIMA_PP_IRQ_CNT_1_LIMIT BIT(7)184#define LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR BIT(8)185#define LIMA_PP_IRQ_INVALID_PLIST_COMMAND BIT(9)186#define LIMA_PP_IRQ_CALL_STACK_UNDERFLOW BIT(10)187#define LIMA_PP_IRQ_CALL_STACK_OVERFLOW BIT(11)188#define LIMA_PP_IRQ_RESET_COMPLETED BIT(12)189#define LIMA_PP_WRITE_BOUNDARY_LOW 0x1044190#define LIMA_PP_BUS_ERROR_STATUS 0x1050191#define LIMA_PP_PERF_CNT_0_ENABLE 0x1080192#define LIMA_PP_PERF_CNT_0_SRC 0x1084193#define LIMA_PP_PERF_CNT_0_LIMIT 0x1088194#define LIMA_PP_PERF_CNT_0_VALUE 0x108c195#define LIMA_PP_PERF_CNT_1_ENABLE 0x10a0196#define LIMA_PP_PERF_CNT_1_SRC 0x10a4197#define LIMA_PP_PERF_CNT_1_LIMIT 0x10a8198#define LIMA_PP_PERF_CNT_1_VALUE 0x10ac199#define LIMA_PP_PERFMON_CONTR 0x10b0200#define LIMA_PP_PERFMON_BASE 0x10b4201 202#define LIMA_PP_IRQ_MASK_ALL \203 ( \204 LIMA_PP_IRQ_END_OF_FRAME | \205 LIMA_PP_IRQ_END_OF_TILE | \206 LIMA_PP_IRQ_HANG | \207 LIMA_PP_IRQ_FORCE_HANG | \208 LIMA_PP_IRQ_BUS_ERROR | \209 LIMA_PP_IRQ_BUS_STOP | \210 LIMA_PP_IRQ_CNT_0_LIMIT | \211 LIMA_PP_IRQ_CNT_1_LIMIT | \212 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR | \213 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \214 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW | \215 LIMA_PP_IRQ_CALL_STACK_OVERFLOW | \216 LIMA_PP_IRQ_RESET_COMPLETED)217 218#define LIMA_PP_IRQ_MASK_ERROR \219 ( \220 LIMA_PP_IRQ_FORCE_HANG | \221 LIMA_PP_IRQ_BUS_ERROR | \222 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR | \223 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \224 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW | \225 LIMA_PP_IRQ_CALL_STACK_OVERFLOW)226 227#define LIMA_PP_IRQ_MASK_USED \228 ( \229 LIMA_PP_IRQ_END_OF_FRAME | \230 LIMA_PP_IRQ_MASK_ERROR)231 232/* MMU regs */233#define LIMA_MMU_DTE_ADDR 0x0000234#define LIMA_MMU_STATUS 0x0004235#define LIMA_MMU_STATUS_PAGING_ENABLED BIT(0)236#define LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)237#define LIMA_MMU_STATUS_STALL_ACTIVE BIT(2)238#define LIMA_MMU_STATUS_IDLE BIT(3)239#define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)240#define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)241#define LIMA_MMU_STATUS_BUS_ID(x) ((x >> 6) & 0x1F)242#define LIMA_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)243#define LIMA_MMU_COMMAND 0x0008244#define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00245#define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01246#define LIMA_MMU_COMMAND_ENABLE_STALL 0x02247#define LIMA_MMU_COMMAND_DISABLE_STALL 0x03248#define LIMA_MMU_COMMAND_ZAP_CACHE 0x04249#define LIMA_MMU_COMMAND_PAGE_FAULT_DONE 0x05250#define LIMA_MMU_COMMAND_HARD_RESET 0x06251#define LIMA_MMU_PAGE_FAULT_ADDR 0x000C252#define LIMA_MMU_ZAP_ONE_LINE 0x0010253#define LIMA_MMU_INT_RAWSTAT 0x0014254#define LIMA_MMU_INT_CLEAR 0x0018255#define LIMA_MMU_INT_MASK 0x001C256#define LIMA_MMU_INT_PAGE_FAULT BIT(0)257#define LIMA_MMU_INT_READ_BUS_ERROR BIT(1)258#define LIMA_MMU_INT_STATUS 0x0020259 260#define LIMA_VM_FLAG_PRESENT BIT(0)261#define LIMA_VM_FLAG_READ_PERMISSION BIT(1)262#define LIMA_VM_FLAG_WRITE_PERMISSION BIT(2)263#define LIMA_VM_FLAG_OVERRIDE_CACHE BIT(3)264#define LIMA_VM_FLAG_WRITE_CACHEABLE BIT(4)265#define LIMA_VM_FLAG_WRITE_ALLOCATE BIT(5)266#define LIMA_VM_FLAG_WRITE_BUFFERABLE BIT(6)267#define LIMA_VM_FLAG_READ_CACHEABLE BIT(7)268#define LIMA_VM_FLAG_READ_ALLOCATE BIT(8)269#define LIMA_VM_FLAG_MASK 0x1FF270 271#define LIMA_VM_FLAGS_CACHE ( \272 LIMA_VM_FLAG_PRESENT | \273 LIMA_VM_FLAG_READ_PERMISSION | \274 LIMA_VM_FLAG_WRITE_PERMISSION | \275 LIMA_VM_FLAG_OVERRIDE_CACHE | \276 LIMA_VM_FLAG_WRITE_CACHEABLE | \277 LIMA_VM_FLAG_WRITE_BUFFERABLE | \278 LIMA_VM_FLAG_READ_CACHEABLE | \279 LIMA_VM_FLAG_READ_ALLOCATE)280 281#define LIMA_VM_FLAGS_UNCACHE ( \282 LIMA_VM_FLAG_PRESENT | \283 LIMA_VM_FLAG_READ_PERMISSION | \284 LIMA_VM_FLAG_WRITE_PERMISSION)285 286/* DLBU regs */287#define LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR 0x0000288#define LIMA_DLBU_MASTER_TLLIST_VADDR 0x0004289#define LIMA_DLBU_TLLIST_VBASEADDR 0x0008290#define LIMA_DLBU_FB_DIM 0x000C291#define LIMA_DLBU_TLLIST_CONF 0x0010292#define LIMA_DLBU_START_TILE_POS 0x0014293#define LIMA_DLBU_PP_ENABLE_MASK 0x0018294 295/* BCAST regs */296#define LIMA_BCAST_BROADCAST_MASK 0x0297#define LIMA_BCAST_INTERRUPT_MASK 0x4298 299#endif300