119 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org>4 * Parts of this file were based on the MCDE driver by Marcus Lorentzon5 * (C) ST-Ericsson SA 20136 */7#include <drm/drm_simple_kms_helper.h>8 9#ifndef _MCDE_DRM_H_10#define _MCDE_DRM_H_11 12/* Shared basic registers */13#define MCDE_CR 0x0000000014#define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 015#define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F16#define MCDE_CR_IFIFOCTRLEN BIT(15)17#define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16)18#define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17)19#define MCDE_CR_AUTOCLKG_EN BIT(30)20#define MCDE_CR_MCDEEN BIT(31)21 22#define MCDE_CONF0 0x0000000423#define MCDE_CONF0_SYNCMUX0 BIT(0)24#define MCDE_CONF0_SYNCMUX1 BIT(1)25#define MCDE_CONF0_SYNCMUX2 BIT(2)26#define MCDE_CONF0_SYNCMUX3 BIT(3)27#define MCDE_CONF0_SYNCMUX4 BIT(4)28#define MCDE_CONF0_SYNCMUX5 BIT(5)29#define MCDE_CONF0_SYNCMUX6 BIT(6)30#define MCDE_CONF0_SYNCMUX7 BIT(7)31#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 1232#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x0000700033#define MCDE_CONF0_OUTMUX0_SHIFT 1634#define MCDE_CONF0_OUTMUX0_MASK 0x0007000035#define MCDE_CONF0_OUTMUX1_SHIFT 1936#define MCDE_CONF0_OUTMUX1_MASK 0x0038000037#define MCDE_CONF0_OUTMUX2_SHIFT 2238#define MCDE_CONF0_OUTMUX2_MASK 0x01C0000039#define MCDE_CONF0_OUTMUX3_SHIFT 2540#define MCDE_CONF0_OUTMUX3_MASK 0x0E00000041#define MCDE_CONF0_OUTMUX4_SHIFT 2842#define MCDE_CONF0_OUTMUX4_MASK 0x7000000043 44#define MCDE_SSP 0x0000000845#define MCDE_AIS 0x0000010046#define MCDE_IMSCERR 0x0000011047#define MCDE_RISERR 0x0000012048#define MCDE_MISERR 0x0000013049#define MCDE_SISERR 0x0000014050 51enum mcde_flow_mode {52 /* One-shot mode: flow stops after one frame */53 MCDE_COMMAND_ONESHOT_FLOW,54 /* Command mode with tearing effect (TE) IRQ sync */55 MCDE_COMMAND_TE_FLOW,56 /*57 * Command mode with bus turn-around (BTA) and tearing effect58 * (TE) IRQ sync.59 */60 MCDE_COMMAND_BTA_TE_FLOW,61 /* Video mode with tearing effect (TE) sync IRQ */62 MCDE_VIDEO_TE_FLOW,63 /* Video mode with the formatter itself as sync source */64 MCDE_VIDEO_FORMATTER_FLOW,65 /* DPI video with the formatter itsels as sync source */66 MCDE_DPI_FORMATTER_FLOW,67};68 69struct mcde {70 struct drm_device drm;71 struct device *dev;72 struct drm_panel *panel;73 struct drm_bridge *bridge;74 struct drm_connector *connector;75 struct drm_simple_display_pipe pipe;76 struct mipi_dsi_device *mdsi;77 bool dpi_output;78 s16 stride;79 enum mcde_flow_mode flow_mode;80 unsigned int flow_active;81 spinlock_t flow_lock; /* Locks the channel flow control */82 83 void __iomem *regs;84 85 struct clk *mcde_clk;86 struct clk *lcd_clk;87 struct clk *hdmi_clk;88 /* Handles to the clock dividers for FIFO A and B */89 struct clk *fifoa_clk;90 struct clk *fifob_clk;91 /* Locks the MCDE FIFO control register A and B */92 spinlock_t fifo_crx1_lock;93 94 struct regulator *epod;95 struct regulator *vana;96};97 98#define to_mcde(dev) container_of(dev, struct mcde, drm)99 100static inline bool mcde_flow_is_video(struct mcde *mcde)101{102 return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW ||103 mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW);104}105 106bool mcde_dsi_irq(struct mipi_dsi_device *mdsi);107void mcde_dsi_te_request(struct mipi_dsi_device *mdsi);108void mcde_dsi_enable(struct drm_bridge *bridge);109void mcde_dsi_disable(struct drm_bridge *bridge);110extern struct platform_driver mcde_dsi_driver;111 112void mcde_display_irq(struct mcde *mcde);113void mcde_display_disable_irqs(struct mcde *mcde);114int mcde_display_init(struct drm_device *drm);115 116int mcde_init_clock_divider(struct mcde *mcde);117 118#endif /* _MCDE_DRM_H_ */119