1234 lines · c
1// SPDX-License-Identifier: GPL-2.0+2#include <linux/clk.h>3#include <linux/component.h>4#include <linux/delay.h>5#include <linux/io.h>6#include <linux/mfd/syscon.h>7#include <linux/module.h>8#include <linux/of.h>9#include <linux/platform_device.h>10#include <linux/regmap.h>11#include <linux/regulator/consumer.h>12#include <video/mipi_display.h>13 14#include <drm/drm_atomic_helper.h>15#include <drm/drm_bridge.h>16#include <drm/drm_device.h>17#include <drm/drm_drv.h>18#include <drm/drm_encoder.h>19#include <drm/drm_mipi_dsi.h>20#include <drm/drm_modeset_helper_vtables.h>21#include <drm/drm_of.h>22#include <drm/drm_panel.h>23#include <drm/drm_print.h>24#include <drm/drm_probe_helper.h>25 26#include "mcde_drm.h"27#include "mcde_dsi_regs.h"28 29#define DSI_DEFAULT_LP_FREQ_HZ 1920000030#define DSI_DEFAULT_HS_FREQ_HZ 42016000031 32/* PRCMU DSI reset registers */33#define PRCM_DSI_SW_RESET 0x32434#define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)35#define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)36#define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)37 38struct mcde_dsi {39 struct device *dev;40 struct mcde *mcde;41 struct drm_bridge bridge;42 struct drm_panel *panel;43 struct drm_bridge *bridge_out;44 struct mipi_dsi_host dsi_host;45 struct mipi_dsi_device *mdsi;46 const struct drm_display_mode *mode;47 struct clk *hs_clk;48 struct clk *lp_clk;49 unsigned long hs_freq;50 unsigned long lp_freq;51 bool unused;52 53 void __iomem *regs;54 struct regmap *prcmu;55};56 57static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge)58{59 return container_of(bridge, struct mcde_dsi, bridge);60}61 62static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h)63{64 return container_of(h, struct mcde_dsi, dsi_host);65}66 67bool mcde_dsi_irq(struct mipi_dsi_device *mdsi)68{69 struct mcde_dsi *d;70 u32 val;71 bool te_received = false;72 73 d = host_to_mcde_dsi(mdsi->host);74 75 dev_dbg(d->dev, "%s called\n", __func__);76 77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);78 if (val)79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);80 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED)81 dev_dbg(d->dev, "direct command write completed\n");82 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) {83 te_received = true;84 dev_dbg(d->dev, "direct command TE received\n");85 }86 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED)87 dev_err(d->dev, "direct command ACK ERR received\n");88 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)89 dev_err(d->dev, "direct command read ERR received\n");90 /* Mask off the ACK value and clear status */91 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);92 93 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);94 if (val)95 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);96 if (val & DSI_CMD_MODE_STS_ERR_NO_TE)97 /* This happens all the time (safe to ignore) */98 dev_dbg(d->dev, "CMD mode no TE\n");99 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS)100 /* This happens all the time (safe to ignore) */101 dev_dbg(d->dev, "CMD mode TE miss\n");102 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN)103 dev_err(d->dev, "CMD mode SD1 underrun\n");104 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN)105 dev_err(d->dev, "CMD mode SD2 underrun\n");106 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD)107 dev_err(d->dev, "CMD mode unwanted RD\n");108 writel(val, d->regs + DSI_CMD_MODE_STS_CLR);109 110 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);111 if (val)112 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);113 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);114 115 val = readl(d->regs + DSI_TG_STS_FLAG);116 if (val)117 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);118 writel(val, d->regs + DSI_TG_STS_CLR);119 120 val = readl(d->regs + DSI_VID_MODE_STS_FLAG);121 if (val)122 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val);123 if (val & DSI_VID_MODE_STS_VSG_RUNNING)124 dev_dbg(d->dev, "VID mode VSG running\n");125 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA)126 dev_err(d->dev, "VID mode missing data\n");127 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC)128 dev_err(d->dev, "VID mode missing HSYNC\n");129 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC)130 dev_err(d->dev, "VID mode missing VSYNC\n");131 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH)132 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n");133 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT)134 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n");135 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE |136 DSI_VID_MODE_STS_ERR_LINEWRITE |137 DSI_VID_MODE_STS_ERR_LONGREAD))138 dev_err(d->dev, "VID mode read/write error\n");139 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH)140 dev_err(d->dev, "VID mode received packets differ from expected size\n");141 if (val & DSI_VID_MODE_STS_VSG_RECOVERY)142 dev_err(d->dev, "VID mode VSG in recovery mode\n");143 writel(val, d->regs + DSI_VID_MODE_STS_CLR);144 145 return te_received;146}147 148static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d)149{150 d->mcde->mdsi = d->mdsi;151 152 /*153 * Select the way the DSI data flow is pushing to the display:154 * currently we just support video or command mode depending155 * on the type of display. Video mode defaults to using the156 * formatter itself for synchronization (stateless video panel).157 *158 * FIXME: add flags to struct mipi_dsi_device .flags to indicate159 * displays that require BTA (bus turn around) so we can handle160 * such displays as well. Figure out how to properly handle161 * single frame on-demand updates with DRM for command mode162 * displays (MCDE_COMMAND_ONESHOT_FLOW).163 */164 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)165 d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW;166 else167 d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW;168}169 170static int mcde_dsi_host_attach(struct mipi_dsi_host *host,171 struct mipi_dsi_device *mdsi)172{173 struct mcde_dsi *d = host_to_mcde_dsi(host);174 175 if (mdsi->lanes < 1 || mdsi->lanes > 2) {176 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n");177 return -EINVAL;178 }179 180 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);181 /* MIPI_DSI_FMT_RGB88 etc */182 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format,183 mipi_dsi_pixel_format_to_bpp(mdsi->format));184 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags);185 186 d->mdsi = mdsi;187 if (d->mcde)188 mcde_dsi_attach_to_mcde(d);189 190 return 0;191}192 193static int mcde_dsi_host_detach(struct mipi_dsi_host *host,194 struct mipi_dsi_device *mdsi)195{196 struct mcde_dsi *d = host_to_mcde_dsi(host);197 198 d->mdsi = NULL;199 if (d->mcde)200 d->mcde->mdsi = NULL;201 202 return 0;203}204 205#define MCDE_DSI_HOST_IS_READ(type) \206 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \207 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \208 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \209 (type == MIPI_DSI_DCS_READ))210 211static int mcde_dsi_execute_transfer(struct mcde_dsi *d,212 const struct mipi_dsi_msg *msg)213{214 const u32 loop_delay_us = 10; /* us */215 u32 loop_counter;216 size_t txlen = msg->tx_len;217 size_t rxlen = msg->rx_len;218 int i;219 u32 val;220 int ret;221 222 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);223 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);224 /* Send command */225 writel(1, d->regs + DSI_DIRECT_CMD_SEND);226 227 loop_counter = 1000 * 1000 / loop_delay_us;228 if (MCDE_DSI_HOST_IS_READ(msg->type)) {229 /* Read command */230 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &231 (DSI_DIRECT_CMD_STS_READ_COMPLETED |232 DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))233 && --loop_counter)234 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);235 if (!loop_counter) {236 dev_err(d->dev, "DSI read timeout!\n");237 /* Set exit code and retry */238 return -ETIME;239 }240 } else {241 /* Writing only */242 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &243 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)244 && --loop_counter)245 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);246 247 if (!loop_counter) {248 /* Set exit code and retry */249 dev_err(d->dev, "DSI write timeout!\n");250 return -ETIME;251 }252 }253 254 val = readl(d->regs + DSI_DIRECT_CMD_STS);255 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {256 dev_err(d->dev, "read completed with error\n");257 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);258 return -EIO;259 }260 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {261 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;262 dev_err(d->dev, "error during transmission: %04x\n",263 val);264 return -EIO;265 }266 267 if (!MCDE_DSI_HOST_IS_READ(msg->type)) {268 /* Return number of bytes written */269 ret = txlen;270 } else {271 /* OK this is a read command, get the response */272 u32 rdsz;273 u32 rddat;274 u8 *rx = msg->rx_buf;275 276 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);277 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;278 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);279 if (rdsz < rxlen) {280 dev_err(d->dev, "read error, requested %zd got %d\n",281 rxlen, rdsz);282 return -EIO;283 }284 /* FIXME: read more than 4 bytes */285 for (i = 0; i < 4 && i < rxlen; i++)286 rx[i] = (rddat >> (i * 8)) & 0xff;287 ret = rdsz;288 }289 290 /* Successful transmission */291 return ret;292}293 294static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,295 const struct mipi_dsi_msg *msg)296{297 struct mcde_dsi *d = host_to_mcde_dsi(host);298 const u8 *tx = msg->tx_buf;299 size_t txlen = msg->tx_len;300 size_t rxlen = msg->rx_len;301 unsigned int retries = 0;302 u32 val;303 int ret;304 int i;305 306 if (txlen > 16) {307 dev_err(d->dev,308 "dunno how to write more than 16 bytes yet\n");309 return -EIO;310 }311 if (rxlen > 4) {312 dev_err(d->dev,313 "dunno how to read more than 4 bytes yet\n");314 return -EIO;315 }316 317 dev_dbg(d->dev,318 "message to channel %d, write %zd bytes read %zd bytes\n",319 msg->channel, txlen, rxlen);320 321 /* Command "nature" */322 if (MCDE_DSI_HOST_IS_READ(msg->type))323 /* MCTL_MAIN_DATA_CTL already set up */324 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;325 else326 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;327 /*328 * More than 2 bytes will not fit in a single packet, so it's329 * time to set the "long not short" bit. One byte is used by330 * the MIPI DCS command leaving just one byte for the payload331 * in a short package.332 */333 if (mipi_dsi_packet_format_is_long(msg->type))334 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;335 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;336 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;337 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;338 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;339 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);340 341 /* MIPI DCS command is part of the data */342 if (txlen > 0) {343 val = 0;344 for (i = 0; i < 4 && i < txlen; i++)345 val |= tx[i] << (i * 8);346 }347 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);348 if (txlen > 4) {349 val = 0;350 for (i = 0; i < 4 && (i + 4) < txlen; i++)351 val |= tx[i + 4] << (i * 8);352 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);353 }354 if (txlen > 8) {355 val = 0;356 for (i = 0; i < 4 && (i + 8) < txlen; i++)357 val |= tx[i + 8] << (i * 8);358 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);359 }360 if (txlen > 12) {361 val = 0;362 for (i = 0; i < 4 && (i + 12) < txlen; i++)363 val |= tx[i + 12] << (i * 8);364 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);365 }366 367 while (retries < 3) {368 ret = mcde_dsi_execute_transfer(d, msg);369 if (ret >= 0)370 break;371 retries++;372 }373 if (ret < 0 && retries)374 dev_err(d->dev, "gave up after %d retries\n", retries);375 376 /* Clear any errors */377 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);378 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);379 380 return ret;381}382 383static const struct mipi_dsi_host_ops mcde_dsi_host_ops = {384 .attach = mcde_dsi_host_attach,385 .detach = mcde_dsi_host_detach,386 .transfer = mcde_dsi_host_transfer,387};388 389/* This sends a direct (short) command to request TE */390void mcde_dsi_te_request(struct mipi_dsi_device *mdsi)391{392 struct mcde_dsi *d;393 u32 val;394 395 d = host_to_mcde_dsi(mdsi->host);396 397 /* Command "nature" TE request */398 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ;399 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;400 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;401 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;402 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM <<403 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;404 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);405 406 /* Clear TE reveived and error status bits and enables them */407 writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR |408 DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR,409 d->regs + DSI_DIRECT_CMD_STS_CLR);410 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);411 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN;412 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN;413 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);414 415 /* Clear and enable no TE or TE missing status */416 writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR |417 DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR,418 d->regs + DSI_CMD_MODE_STS_CLR);419 val = readl(d->regs + DSI_CMD_MODE_STS_CTL);420 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN;421 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN;422 writel(val, d->regs + DSI_CMD_MODE_STS_CTL);423 424 /* Send this TE request command */425 writel(1, d->regs + DSI_DIRECT_CMD_SEND);426}427 428static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,429 const struct drm_display_mode *mode)430{431 /* cpp, characters per pixel, number of bytes per pixel */432 u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8;433 u64 pclk;434 u64 bpl;435 int hfp;436 int hbp;437 int hsa;438 u32 blkline_pck, line_duration;439 u32 val;440 441 val = 0;442 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)443 val |= DSI_VID_MAIN_CTL_BURST_MODE;444 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {445 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE;446 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL;447 }448 /* RGB header and pixel mode */449 switch (d->mdsi->format) {450 case MIPI_DSI_FMT_RGB565:451 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 <<452 DSI_VID_MAIN_CTL_HEADER_SHIFT;453 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS;454 break;455 case MIPI_DSI_FMT_RGB666_PACKED:456 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 <<457 DSI_VID_MAIN_CTL_HEADER_SHIFT;458 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS;459 break;460 case MIPI_DSI_FMT_RGB666:461 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18462 << DSI_VID_MAIN_CTL_HEADER_SHIFT;463 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE;464 break;465 case MIPI_DSI_FMT_RGB888:466 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 <<467 DSI_VID_MAIN_CTL_HEADER_SHIFT;468 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS;469 break;470 default:471 dev_err(d->dev, "unknown pixel mode\n");472 return;473 }474 475 /* TODO: TVG (test video generator) could be enabled here */476 477 /*478 * During vertical blanking: go to LP mode479 * Like with the EOL setting, if this is not set, the EOL area will be480 * filled with NULL or blanking packets in the vblank area.481 * FIXME: some Samsung phones and display panels such as s6e63m0 use482 * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead,483 * figure out how to properly configure that from the panel.484 */485 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0;486 /*487 * During EOL: go to LP mode. If this is not set, the EOL area will be488 * filled with NULL or blanking packets.489 */490 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0;491 /* Recovery mode 1 */492 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT;493 /* All other fields zero */494 writel(val, d->regs + DSI_VID_MAIN_CTL);495 496 /* Vertical frame parameters are pretty straight-forward */497 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;498 /* vertical front porch */499 val |= (mode->vsync_start - mode->vdisplay)500 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT;501 /* vertical sync active */502 val |= (mode->vsync_end - mode->vsync_start)503 << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;504 /* vertical back porch */505 val |= (mode->vtotal - mode->vsync_end)506 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT;507 writel(val, d->regs + DSI_VID_VSIZE);508 509 /*510 * Horizontal frame parameters:511 * horizontal resolution is given in pixels but must be re-calculated512 * into bytes since this is what the hardware expects, these registers513 * define the payload size of the packet.514 *515 * hfp = horizontal front porch in bytes516 * hbp = horizontal back porch in bytes517 * hsa = horizontal sync active in bytes518 *519 * 6 + 2 is HFP header + checksum520 */521 hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2;522 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {523 /*524 * Use sync pulse for sync: explicit HSA time525 * 6 is HBP header + checksum526 * 4 is RGB header + checksum527 */528 hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6;529 /*530 * 6 is HBP header + checksum531 * 4 is HSW packet bytes532 * 4 is RGB header + checksum533 */534 hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6;535 } else {536 /*537 * Use event for sync: HBP includes both back porch and sync538 * 6 is HBP header + checksum539 * 4 is HSW packet bytes540 * 4 is RGB header + checksum541 */542 hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6;543 /* HSA is not present in this mode and set to 0 */544 hsa = 0;545 }546 if (hfp < 0) {547 dev_info(d->dev, "hfp negative, set to 0\n");548 hfp = 0;549 }550 if (hbp < 0) {551 dev_info(d->dev, "hbp negative, set to 0\n");552 hbp = 0;553 }554 if (hsa < 0) {555 dev_info(d->dev, "hsa negative, set to 0\n");556 hsa = 0;557 }558 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n",559 hfp, hbp, hsa);560 561 /* Frame parameters: horizontal sync active */562 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT;563 /* horizontal back porch */564 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT;565 /* horizontal front porch */566 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT;567 writel(val, d->regs + DSI_VID_HSIZE1);568 569 /* RGB data length (visible bytes on one scanline) */570 val = mode->hdisplay * cpp;571 writel(val, d->regs + DSI_VID_HSIZE2);572 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val);573 574 /*575 * Calculate the time between two pixels in picoseconds using576 * the supplied refresh rate and total resolution including577 * porches and sync.578 */579 /* (ps/s) / (pixels/s) = ps/pixels */580 pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000));581 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",582 pclk);583 584 /*585 * How many bytes per line will this update frequency yield?586 *587 * Calculate the number of picoseconds for one scanline (1), then588 * divide by 1000000000000 (2) to get in pixels per second we589 * want to output.590 *591 * Multiply with number of bytes per second at this video display592 * frequency (3) to get number of bytes transferred during this593 * time. Notice that we use the frequency the display wants,594 * not what we actually get from the DSI PLL, which is hs_freq.595 *596 * These arithmetics are done in a different order to avoid597 * overflow.598 */599 bpl = pclk * mode->htotal; /* (1) picoseconds per line */600 dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl);601 /* Multiply with bytes per second (3) */602 bpl *= (d->mdsi->hs_rate / 8);603 /* Pixels per second (2) */604 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */605 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */606 /* parallel transactions in all lanes */607 bpl *= d->mdsi->lanes;608 dev_dbg(d->dev,609 "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n",610 bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate);611 612 /*613 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes614 * 4 is short packet for vsync/hsync615 */616 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {617 /* Set the event packet size to 0 (not used) */618 writel(0, d->regs + DSI_VID_BLKSIZE1);619 /*620 * FIXME: isn't the hsync width in pixels? The porch and621 * sync area size is in pixels here, but this -6622 * seems to be for bytes. It looks like this in the vendor623 * code though. Is it completely untested?624 */625 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6;626 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT;627 writel(val, d->regs + DSI_VID_BLKSIZE2);628 } else {629 /* Set the sync pulse packet size to 0 (not used) */630 writel(0, d->regs + DSI_VID_BLKSIZE2);631 /* Specifying payload size in bytes (-4-6 from manual) */632 blkline_pck = bpl - 4 - 6;633 if (blkline_pck > 0x1FFF)634 dev_err(d->dev, "blkline_pck too big %d bytes\n",635 blkline_pck);636 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT;637 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK;638 writel(val, d->regs + DSI_VID_BLKSIZE1);639 }640 641 /*642 * The line duration is used to scale back the frequency from643 * the max frequency supported by the HS clock to the desired644 * update frequency in vrefresh.645 */646 line_duration = blkline_pck + 6;647 /*648 * The datasheet contains this complex condition to decreasing649 * the line duration by 1 under very specific circumstances.650 * Here we also imply that LP is used during burst EOL.651 */652 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01)653 && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))654 line_duration--;655 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes);656 dev_dbg(d->dev, "line duration %u bytes\n", line_duration);657 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;658 /*659 * This is the time to perform LP->HS on D-PHY660 * FIXME: nowhere to get this from: DT property on the DSI?661 * The manual says this is "system dependent".662 * values like 48 and 72 seen in the vendor code.663 */664 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;665 writel(val, d->regs + DSI_VID_DPHY_TIME);666 667 /*668 * See the manual figure 657 page 2203 for understanding the impact669 * of the different burst mode settings.670 */671 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {672 int blkeol_pck, blkeol_duration;673 /*674 * Packet size at EOL for burst mode, this is only used675 * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set,676 * but we instead send NULL or blanking packets at EOL.677 * This is given in number of bytes.678 *679 * See the manual page 2198 for the 13 reg_blkeol_pck bits.680 */681 blkeol_pck = bpl - (mode->htotal * cpp) - 6;682 if (blkeol_pck < 0) {683 dev_err(d->dev, "video block does not fit on line!\n");684 dev_err(d->dev,685 "calculated bytes per line: %llu @ %d Hz\n",686 bpl, drm_mode_vrefresh(mode));687 dev_err(d->dev,688 "bytes per line (blkline_pck) %u bytes\n",689 blkline_pck);690 dev_err(d->dev,691 "blkeol_pck becomes %d bytes\n", blkeol_pck);692 return;693 }694 dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck);695 696 val = readl(d->regs + DSI_VID_BLKSIZE1);697 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK;698 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;699 writel(val, d->regs + DSI_VID_BLKSIZE1);700 /* Use the same value for exact burst limit */701 val = blkeol_pck <<702 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT;703 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK;704 writel(val, d->regs + DSI_VID_VCA_SETTING2);705 /*706 * This BLKEOL duration is claimed to be the duration in clock707 * cycles of the BLLP end-of-line (EOL) period for each line if708 * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set.709 *710 * It is hard to trust the manuals' claim that this is in clock711 * cycles as we mimic the behaviour of the vendor code, which712 * appears to write a number of bytes that would have been713 * transferred on a single lane.714 *715 * See the manual figure 657 page 2203 and page 2198 for the 13716 * reg_blkeol_duration bits.717 *718 * FIXME: should this also be set up also for non-burst mode719 * according to figure 565 page 2202?720 */721 blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6,722 d->mdsi->lanes);723 dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n",724 blkeol_duration);725 726 val = readl(d->regs + DSI_VID_PCK_TIME);727 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK;728 val |= blkeol_duration <<729 DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT;730 writel(val, d->regs + DSI_VID_PCK_TIME);731 732 /* Max burst limit, this is given in bytes */733 val = readl(d->regs + DSI_VID_VCA_SETTING1);734 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK;735 val |= (blkeol_pck - 6) <<736 DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT;737 writel(val, d->regs + DSI_VID_VCA_SETTING1);738 }739 740 /* Maximum line limit */741 val = readl(d->regs + DSI_VID_VCA_SETTING2);742 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK;743 val |= (blkline_pck - 6) <<744 DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT;745 writel(val, d->regs + DSI_VID_VCA_SETTING2);746 dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6);747}748 749static void mcde_dsi_start(struct mcde_dsi *d)750{751 unsigned long hs_freq;752 u32 val;753 int i;754 755 /* No integration mode */756 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);757 758 /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */759 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN |760 DSI_MCTL_MAIN_DATA_CTL_BTA_EN |761 DSI_MCTL_MAIN_DATA_CTL_READ_EN |762 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN;763 if (!(d->mdsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))764 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN;765 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);766 767 /* Set a high command timeout, clear other fields */768 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT;769 writel(val, d->regs + DSI_CMD_MODE_CTL);770 771 /*772 * UI_X4 is described as "unit interval times four"773 * I guess since DSI packets are 4 bytes wide, one unit774 * is one byte.775 */776 hs_freq = clk_get_rate(d->hs_clk);777 hs_freq /= 1000000; /* MHz */778 val = 4000 / hs_freq;779 dev_dbg(d->dev, "UI value: %d\n", val);780 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT;781 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK;782 writel(val, d->regs + DSI_MCTL_DPHY_STATIC);783 784 /*785 * Enable clocking: 0x0f (something?) between each burst,786 * enable the second lane if needed, enable continuous clock if787 * needed, enable switch into ULPM (ultra-low power mode) on788 * all the lines.789 */790 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT;791 if (d->mdsi->lanes == 2)792 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN;793 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))794 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS;795 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN |796 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN |797 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN;798 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);799 800 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) |801 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT);802 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);803 804 writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,805 d->regs + DSI_DPHY_LANES_TRIM);806 807 /* High PHY timeout */808 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) |809 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) |810 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT);811 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);812 813 val = DSI_MCTL_MAIN_EN_PLL_START |814 DSI_MCTL_MAIN_EN_CKLANE_EN |815 DSI_MCTL_MAIN_EN_DAT1_EN |816 DSI_MCTL_MAIN_EN_IF1_EN;817 if (d->mdsi->lanes == 2)818 val |= DSI_MCTL_MAIN_EN_DAT2_EN;819 writel(val, d->regs + DSI_MCTL_MAIN_EN);820 821 /* Wait for the PLL to lock and the clock and data lines to come up */822 i = 0;823 val = DSI_MCTL_MAIN_STS_PLL_LOCK |824 DSI_MCTL_MAIN_STS_CLKLANE_READY |825 DSI_MCTL_MAIN_STS_DAT1_READY;826 if (d->mdsi->lanes == 2)827 val |= DSI_MCTL_MAIN_STS_DAT2_READY;828 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {829 /* Sleep for a millisecond */830 usleep_range(1000, 1500);831 if (i++ == 100) {832 dev_warn(d->dev, "DSI lanes did not start up\n");833 return;834 }835 }836 837 /* TODO needed? */838 839 /* Command mode, clear IF1 ID */840 val = readl(d->regs + DSI_CMD_MODE_CTL);841 /*842 * If we enable low-power mode here,843 * then display updates become really slow.844 */845 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM)846 val |= DSI_CMD_MODE_CTL_IF1_LP_EN;847 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;848 writel(val, d->regs + DSI_CMD_MODE_CTL);849 850 /* Wait for DSI PHY to initialize */851 usleep_range(100, 200);852 dev_info(d->dev, "DSI link enabled\n");853}854 855/*856 * Notice that this is called from inside the display controller857 * and not from the bridge callbacks.858 */859void mcde_dsi_enable(struct drm_bridge *bridge)860{861 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);862 unsigned long hs_freq, lp_freq;863 u32 val;864 int ret;865 866 /* Copy maximum clock frequencies */867 if (d->mdsi->lp_rate)868 lp_freq = d->mdsi->lp_rate;869 else870 lp_freq = DSI_DEFAULT_LP_FREQ_HZ;871 if (d->mdsi->hs_rate)872 hs_freq = d->mdsi->hs_rate;873 else874 hs_freq = DSI_DEFAULT_HS_FREQ_HZ;875 876 /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */877 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq);878 ret = clk_set_rate(d->lp_clk, d->lp_freq);879 if (ret)880 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n",881 d->lp_freq);882 883 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq);884 ret = clk_set_rate(d->hs_clk, d->hs_freq);885 if (ret)886 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n",887 d->hs_freq);888 889 /* Start clocks */890 ret = clk_prepare_enable(d->lp_clk);891 if (ret)892 dev_err(d->dev, "failed to enable LP clock\n");893 else894 dev_info(d->dev, "DSI LP clock rate %lu Hz\n",895 d->lp_freq);896 ret = clk_prepare_enable(d->hs_clk);897 if (ret)898 dev_err(d->dev, "failed to enable HS clock\n");899 else900 dev_info(d->dev, "DSI HS clock rate %lu Hz\n",901 d->hs_freq);902 903 /* Assert RESET through the PRCMU, active low */904 /* FIXME: which DSI block? */905 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,906 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);907 908 usleep_range(100, 200);909 910 /* De-assert RESET again */911 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,912 PRCM_DSI_SW_RESET_DSI0_SW_RESETN,913 PRCM_DSI_SW_RESET_DSI0_SW_RESETN);914 915 /* Start up the hardware */916 mcde_dsi_start(d);917 918 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {919 /* Set up the video mode from the DRM mode */920 mcde_dsi_setup_video_mode(d, d->mode);921 922 /* Put IF1 into video mode */923 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);924 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE;925 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);926 927 /* Disable command mode on IF1 */928 val = readl(d->regs + DSI_CMD_MODE_CTL);929 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN;930 writel(val, d->regs + DSI_CMD_MODE_CTL);931 932 /* Enable some error interrupts */933 val = readl(d->regs + DSI_VID_MODE_STS_CTL);934 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;935 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;936 writel(val, d->regs + DSI_VID_MODE_STS_CTL);937 938 /* Enable video mode */939 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);940 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;941 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);942 } else {943 /* Command mode, clear IF1 ID */944 val = readl(d->regs + DSI_CMD_MODE_CTL);945 /*946 * If we enable low-power mode here947 * the display updates become really slow.948 */949 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM)950 val |= DSI_CMD_MODE_CTL_IF1_LP_EN;951 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;952 writel(val, d->regs + DSI_CMD_MODE_CTL);953 }954 955 dev_info(d->dev, "enabled MCDE DSI master\n");956}957 958static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge,959 const struct drm_display_mode *mode,960 const struct drm_display_mode *adj)961{962 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);963 964 if (!d->mdsi) {965 dev_err(d->dev, "no DSI device attached to encoder!\n");966 return;967 }968 969 d->mode = mode;970 971 dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n",972 mode->hdisplay, mode->vdisplay, mode->clock * 1000,973 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD"974 );975}976 977static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d)978{979 u32 val;980 int i;981 982 /*983 * Wait until we get out of command mode984 * CSM = Command State Machine985 */986 i = 0;987 val = DSI_CMD_MODE_STS_CSM_RUNNING;988 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {989 /* Sleep for a millisecond */990 usleep_range(1000, 2000);991 if (i++ == 100) {992 dev_warn(d->dev,993 "could not get out of command mode\n");994 return;995 }996 }997}998 999static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d)1000{1001 u32 val;1002 int i;1003 1004 /* Wait until we get out og video mode */1005 i = 0;1006 val = DSI_VID_MODE_STS_VSG_RUNNING;1007 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {1008 /* Sleep for a millisecond */1009 usleep_range(1000, 2000);1010 if (i++ == 100) {1011 dev_warn(d->dev,1012 "could not get out of video mode\n");1013 return;1014 }1015 }1016}1017 1018/*1019 * Notice that this is called from inside the display controller1020 * and not from the bridge callbacks.1021 */1022void mcde_dsi_disable(struct drm_bridge *bridge)1023{1024 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);1025 u32 val;1026 1027 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {1028 /* Stop video mode */1029 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);1030 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN;1031 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);1032 mcde_dsi_wait_for_video_mode_stop(d);1033 } else {1034 /* Stop command mode */1035 mcde_dsi_wait_for_command_mode_stop(d);1036 }1037 1038 /*1039 * Stop clocks and terminate any DSI traffic here so the panel can1040 * send commands to shut down the display using DSI direct write until1041 * this point.1042 */1043 1044 /* Disable all error interrupts */1045 writel(0, d->regs + DSI_VID_MODE_STS_CTL);1046 clk_disable_unprepare(d->hs_clk);1047 clk_disable_unprepare(d->lp_clk);1048}1049 1050static int mcde_dsi_bridge_attach(struct drm_bridge *bridge,1051 enum drm_bridge_attach_flags flags)1052{1053 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);1054 struct drm_device *drm = bridge->dev;1055 1056 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {1057 dev_err(d->dev, "we need atomic updates\n");1058 return -ENOTSUPP;1059 }1060 1061 /* Attach the DSI bridge to the output (panel etc) bridge */1062 return drm_bridge_attach(bridge->encoder, d->bridge_out, bridge, flags);1063}1064 1065static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = {1066 .attach = mcde_dsi_bridge_attach,1067 .mode_set = mcde_dsi_bridge_mode_set,1068};1069 1070static int mcde_dsi_bind(struct device *dev, struct device *master,1071 void *data)1072{1073 struct drm_device *drm = data;1074 struct mcde *mcde = to_mcde(drm);1075 struct mcde_dsi *d = dev_get_drvdata(dev);1076 struct device_node *child;1077 struct drm_panel *panel = NULL;1078 struct drm_bridge *bridge = NULL;1079 1080 if (!of_get_available_child_count(dev->of_node)) {1081 dev_info(dev, "unused DSI interface\n");1082 d->unused = true;1083 return 0;1084 }1085 d->mcde = mcde;1086 /* If the display attached before binding, set this up */1087 if (d->mdsi)1088 mcde_dsi_attach_to_mcde(d);1089 1090 /* Obtain the clocks */1091 d->hs_clk = devm_clk_get(dev, "hs");1092 if (IS_ERR(d->hs_clk)) {1093 dev_err(dev, "unable to get HS clock\n");1094 return PTR_ERR(d->hs_clk);1095 }1096 1097 d->lp_clk = devm_clk_get(dev, "lp");1098 if (IS_ERR(d->lp_clk)) {1099 dev_err(dev, "unable to get LP clock\n");1100 return PTR_ERR(d->lp_clk);1101 }1102 1103 /* Look for a panel as a child to this node */1104 for_each_available_child_of_node(dev->of_node, child) {1105 panel = of_drm_find_panel(child);1106 if (IS_ERR(panel)) {1107 dev_err(dev, "failed to find panel try bridge (%ld)\n",1108 PTR_ERR(panel));1109 panel = NULL;1110 1111 bridge = of_drm_find_bridge(child);1112 if (!bridge) {1113 dev_err(dev, "failed to find bridge\n");1114 of_node_put(child);1115 return -EINVAL;1116 }1117 }1118 }1119 if (panel) {1120 bridge = drm_panel_bridge_add_typed(panel,1121 DRM_MODE_CONNECTOR_DSI);1122 if (IS_ERR(bridge)) {1123 dev_err(dev, "error adding panel bridge\n");1124 return PTR_ERR(bridge);1125 }1126 dev_info(dev, "connected to panel\n");1127 d->panel = panel;1128 } else if (bridge) {1129 /* TODO: AV8100 HDMI encoder goes here for example */1130 dev_info(dev, "connected to non-panel bridge (unsupported)\n");1131 return -ENODEV;1132 } else {1133 dev_err(dev, "no panel or bridge\n");1134 return -ENODEV;1135 }1136 1137 d->bridge_out = bridge;1138 1139 /* Create a bridge for this DSI channel */1140 d->bridge.funcs = &mcde_dsi_bridge_funcs;1141 d->bridge.of_node = dev->of_node;1142 drm_bridge_add(&d->bridge);1143 1144 /* TODO: first come first serve, use a list */1145 mcde->bridge = &d->bridge;1146 1147 dev_info(dev, "initialized MCDE DSI bridge\n");1148 1149 return 0;1150}1151 1152static void mcde_dsi_unbind(struct device *dev, struct device *master,1153 void *data)1154{1155 struct mcde_dsi *d = dev_get_drvdata(dev);1156 1157 if (d->panel)1158 drm_panel_bridge_remove(d->bridge_out);1159 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,1160 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);1161}1162 1163static const struct component_ops mcde_dsi_component_ops = {1164 .bind = mcde_dsi_bind,1165 .unbind = mcde_dsi_unbind,1166};1167 1168static int mcde_dsi_probe(struct platform_device *pdev)1169{1170 struct device *dev = &pdev->dev;1171 struct mcde_dsi *d;1172 struct mipi_dsi_host *host;1173 u32 dsi_id;1174 int ret;1175 1176 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);1177 if (!d)1178 return -ENOMEM;1179 d->dev = dev;1180 platform_set_drvdata(pdev, d);1181 1182 /* Get a handle on the PRCMU so we can do reset */1183 d->prcmu =1184 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu");1185 if (IS_ERR(d->prcmu)) {1186 dev_err(dev, "no PRCMU regmap\n");1187 return PTR_ERR(d->prcmu);1188 }1189 1190 d->regs = devm_platform_ioremap_resource(pdev, 0);1191 if (IS_ERR(d->regs))1192 return PTR_ERR(d->regs);1193 1194 dsi_id = readl(d->regs + DSI_ID_REG);1195 dev_info(dev, "HW revision 0x%08x\n", dsi_id);1196 1197 host = &d->dsi_host;1198 host->dev = dev;1199 host->ops = &mcde_dsi_host_ops;1200 ret = mipi_dsi_host_register(host);1201 if (ret < 0) {1202 dev_err(dev, "failed to register DSI host: %d\n", ret);1203 return ret;1204 }1205 dev_info(dev, "registered DSI host\n");1206 1207 platform_set_drvdata(pdev, d);1208 return component_add(dev, &mcde_dsi_component_ops);1209}1210 1211static void mcde_dsi_remove(struct platform_device *pdev)1212{1213 struct mcde_dsi *d = platform_get_drvdata(pdev);1214 1215 component_del(&pdev->dev, &mcde_dsi_component_ops);1216 mipi_dsi_host_unregister(&d->dsi_host);1217}1218 1219static const struct of_device_id mcde_dsi_of_match[] = {1220 {1221 .compatible = "ste,mcde-dsi",1222 },1223 {},1224};1225 1226struct platform_driver mcde_dsi_driver = {1227 .driver = {1228 .name = "mcde-dsi",1229 .of_match_table = mcde_dsi_of_match,1230 },1231 .probe = mcde_dsi_probe,1232 .remove_new = mcde_dsi_remove,1233};1234