2918 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2019-2022 MediaTek Inc.4 * Copyright (c) 2022 BayLibre5 */6 7#include <drm/display/drm_dp_aux_bus.h>8#include <drm/display/drm_dp.h>9#include <drm/display/drm_dp_helper.h>10#include <drm/drm_atomic_helper.h>11#include <drm/drm_bridge.h>12#include <drm/drm_crtc.h>13#include <drm/drm_edid.h>14#include <drm/drm_of.h>15#include <drm/drm_panel.h>16#include <drm/drm_print.h>17#include <drm/drm_probe_helper.h>18#include <linux/arm-smccc.h>19#include <linux/clk.h>20#include <linux/delay.h>21#include <linux/errno.h>22#include <linux/kernel.h>23#include <linux/media-bus-format.h>24#include <linux/nvmem-consumer.h>25#include <linux/of.h>26#include <linux/of_irq.h>27#include <linux/of_platform.h>28#include <linux/phy/phy.h>29#include <linux/platform_device.h>30#include <linux/pm_runtime.h>31#include <linux/regmap.h>32#include <linux/soc/mediatek/mtk_sip_svc.h>33#include <sound/hdmi-codec.h>34#include <video/videomode.h>35 36#include "mtk_dp_reg.h"37 38#define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523)39#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE (BIT(0) | BIT(5))40#define MTK_DP_SIP_ATF_VIDEO_UNMUTE BIT(5)41 42#define MTK_DP_THREAD_CABLE_STATE_CHG BIT(0)43#define MTK_DP_THREAD_HPD_EVENT BIT(1)44 45#define MTK_DP_4P1T 446#define MTK_DP_HDE 247#define MTK_DP_PIX_PER_ADDR 248#define MTK_DP_AUX_WAIT_REPLY_COUNT 2049#define MTK_DP_TBC_BUF_READ_START_ADDR 0x850#define MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY 551#define MTK_DP_TRAIN_DOWNSCALE_RETRY 1052#define MTK_DP_VERSION 0x1153#define MTK_DP_SDP_AUI 0x454 55enum {56 MTK_DP_CAL_GLB_BIAS_TRIM = 0,57 MTK_DP_CAL_CLKTX_IMPSE,58 MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0,59 MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1,60 MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2,61 MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3,62 MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0,63 MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1,64 MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2,65 MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3,66 MTK_DP_CAL_MAX,67};68 69struct mtk_dp_train_info {70 bool sink_ssc;71 bool cable_plugged_in;72 /* link_rate is in multiple of 0.27Gbps */73 int link_rate;74 int lane_count;75 unsigned int channel_eq_pattern;76};77 78struct mtk_dp_audio_cfg {79 bool detect_monitor;80 int sad_count;81 int sample_rate;82 int word_length_bits;83 int channels;84};85 86struct mtk_dp_info {87 enum dp_pixelformat format;88 struct videomode vm;89 struct mtk_dp_audio_cfg audio_cur_cfg;90};91 92struct mtk_dp_efuse_fmt {93 unsigned short idx;94 unsigned short shift;95 unsigned short mask;96 unsigned short min_val;97 unsigned short max_val;98 unsigned short default_val;99};100 101struct mtk_dp {102 bool enabled;103 bool need_debounce;104 int irq;105 u8 max_lanes;106 u8 max_linkrate;107 u8 rx_cap[DP_RECEIVER_CAP_SIZE];108 u32 cal_data[MTK_DP_CAL_MAX];109 u32 irq_thread_handle;110 /* irq_thread_lock is used to protect irq_thread_handle */111 spinlock_t irq_thread_lock;112 113 struct device *dev;114 struct drm_bridge bridge;115 struct drm_bridge *next_bridge;116 struct drm_connector *conn;117 struct drm_device *drm_dev;118 struct drm_dp_aux aux;119 120 const struct mtk_dp_data *data;121 struct mtk_dp_info info;122 struct mtk_dp_train_info train_info;123 124 struct platform_device *phy_dev;125 struct phy *phy;126 struct regmap *regs;127 struct timer_list debounce_timer;128 129 /* For audio */130 bool audio_enable;131 hdmi_codec_plugged_cb plugged_cb;132 struct platform_device *audio_pdev;133 134 struct device *codec_dev;135 /* protect the plugged_cb as it's used in both bridge ops and audio */136 struct mutex update_plugged_status_lock;137};138 139struct mtk_dp_data {140 int bridge_type;141 unsigned int smc_cmd;142 const struct mtk_dp_efuse_fmt *efuse_fmt;143 bool audio_supported;144 bool audio_pkt_in_hblank_area;145 u16 audio_m_div2_bit;146};147 148static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {149 [MTK_DP_CAL_GLB_BIAS_TRIM] = {150 .idx = 0,151 .shift = 10,152 .mask = 0x1f,153 .min_val = 1,154 .max_val = 0x1e,155 .default_val = 0xf,156 },157 [MTK_DP_CAL_CLKTX_IMPSE] = {158 .idx = 0,159 .shift = 15,160 .mask = 0xf,161 .min_val = 1,162 .max_val = 0xe,163 .default_val = 0x8,164 },165 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {166 .idx = 1,167 .shift = 0,168 .mask = 0xf,169 .min_val = 1,170 .max_val = 0xe,171 .default_val = 0x8,172 },173 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {174 .idx = 1,175 .shift = 8,176 .mask = 0xf,177 .min_val = 1,178 .max_val = 0xe,179 .default_val = 0x8,180 },181 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {182 .idx = 1,183 .shift = 16,184 .mask = 0xf,185 .min_val = 1,186 .max_val = 0xe,187 .default_val = 0x8,188 },189 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {190 .idx = 1,191 .shift = 24,192 .mask = 0xf,193 .min_val = 1,194 .max_val = 0xe,195 .default_val = 0x8,196 },197 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {198 .idx = 1,199 .shift = 4,200 .mask = 0xf,201 .min_val = 1,202 .max_val = 0xe,203 .default_val = 0x8,204 },205 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {206 .idx = 1,207 .shift = 12,208 .mask = 0xf,209 .min_val = 1,210 .max_val = 0xe,211 .default_val = 0x8,212 },213 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {214 .idx = 1,215 .shift = 20,216 .mask = 0xf,217 .min_val = 1,218 .max_val = 0xe,219 .default_val = 0x8,220 },221 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {222 .idx = 1,223 .shift = 28,224 .mask = 0xf,225 .min_val = 1,226 .max_val = 0xe,227 .default_val = 0x8,228 },229};230 231static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {232 [MTK_DP_CAL_GLB_BIAS_TRIM] = {233 .idx = 3,234 .shift = 27,235 .mask = 0x1f,236 .min_val = 1,237 .max_val = 0x1e,238 .default_val = 0xf,239 },240 [MTK_DP_CAL_CLKTX_IMPSE] = {241 .idx = 0,242 .shift = 9,243 .mask = 0xf,244 .min_val = 1,245 .max_val = 0xe,246 .default_val = 0x8,247 },248 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {249 .idx = 2,250 .shift = 28,251 .mask = 0xf,252 .min_val = 1,253 .max_val = 0xe,254 .default_val = 0x8,255 },256 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {257 .idx = 2,258 .shift = 20,259 .mask = 0xf,260 .min_val = 1,261 .max_val = 0xe,262 .default_val = 0x8,263 },264 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {265 .idx = 2,266 .shift = 12,267 .mask = 0xf,268 .min_val = 1,269 .max_val = 0xe,270 .default_val = 0x8,271 },272 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {273 .idx = 2,274 .shift = 4,275 .mask = 0xf,276 .min_val = 1,277 .max_val = 0xe,278 .default_val = 0x8,279 },280 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {281 .idx = 2,282 .shift = 24,283 .mask = 0xf,284 .min_val = 1,285 .max_val = 0xe,286 .default_val = 0x8,287 },288 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {289 .idx = 2,290 .shift = 16,291 .mask = 0xf,292 .min_val = 1,293 .max_val = 0xe,294 .default_val = 0x8,295 },296 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {297 .idx = 2,298 .shift = 8,299 .mask = 0xf,300 .min_val = 1,301 .max_val = 0xe,302 .default_val = 0x8,303 },304 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {305 .idx = 2,306 .shift = 0,307 .mask = 0xf,308 .min_val = 1,309 .max_val = 0xe,310 .default_val = 0x8,311 },312};313 314static const struct mtk_dp_efuse_fmt mt8195_dp_efuse_fmt[MTK_DP_CAL_MAX] = {315 [MTK_DP_CAL_GLB_BIAS_TRIM] = {316 .idx = 0,317 .shift = 27,318 .mask = 0x1f,319 .min_val = 1,320 .max_val = 0x1e,321 .default_val = 0xf,322 },323 [MTK_DP_CAL_CLKTX_IMPSE] = {324 .idx = 0,325 .shift = 13,326 .mask = 0xf,327 .min_val = 1,328 .max_val = 0xe,329 .default_val = 0x8,330 },331 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {332 .idx = 1,333 .shift = 28,334 .mask = 0xf,335 .min_val = 1,336 .max_val = 0xe,337 .default_val = 0x8,338 },339 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {340 .idx = 1,341 .shift = 20,342 .mask = 0xf,343 .min_val = 1,344 .max_val = 0xe,345 .default_val = 0x8,346 },347 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {348 .idx = 1,349 .shift = 12,350 .mask = 0xf,351 .min_val = 1,352 .max_val = 0xe,353 .default_val = 0x8,354 },355 [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {356 .idx = 1,357 .shift = 4,358 .mask = 0xf,359 .min_val = 1,360 .max_val = 0xe,361 .default_val = 0x8,362 },363 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {364 .idx = 1,365 .shift = 24,366 .mask = 0xf,367 .min_val = 1,368 .max_val = 0xe,369 .default_val = 0x8,370 },371 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {372 .idx = 1,373 .shift = 16,374 .mask = 0xf,375 .min_val = 1,376 .max_val = 0xe,377 .default_val = 0x8,378 },379 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {380 .idx = 1,381 .shift = 8,382 .mask = 0xf,383 .min_val = 1,384 .max_val = 0xe,385 .default_val = 0x8,386 },387 [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {388 .idx = 1,389 .shift = 0,390 .mask = 0xf,391 .min_val = 1,392 .max_val = 0xe,393 .default_val = 0x8,394 },395};396 397static struct regmap_config mtk_dp_regmap_config = {398 .reg_bits = 32,399 .val_bits = 32,400 .reg_stride = 4,401 .max_register = SEC_OFFSET + 0x90,402 .name = "mtk-dp-registers",403};404 405static struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b)406{407 return container_of(b, struct mtk_dp, bridge);408}409 410static u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)411{412 u32 read_val;413 int ret;414 415 ret = regmap_read(mtk_dp->regs, offset, &read_val);416 if (ret) {417 dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n",418 offset, ret);419 return 0;420 }421 422 return read_val;423}424 425static int mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)426{427 int ret = regmap_write(mtk_dp->regs, offset, val);428 429 if (ret)430 dev_err(mtk_dp->dev,431 "Failed to write register 0x%x with value 0x%x\n",432 offset, val);433 return ret;434}435 436static int mtk_dp_update_bits(struct mtk_dp *mtk_dp, u32 offset,437 u32 val, u32 mask)438{439 int ret = regmap_update_bits(mtk_dp->regs, offset, mask, val);440 441 if (ret)442 dev_err(mtk_dp->dev,443 "Failed to update register 0x%x with value 0x%x, mask 0x%x\n",444 offset, val, mask);445 return ret;446}447 448static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32 offset, u8 *buf,449 size_t length)450{451 int i;452 453 /* 2 bytes per register */454 for (i = 0; i < length; i += 2) {455 u32 val = buf[i] | (i + 1 < length ? buf[i + 1] << 8 : 0);456 457 if (mtk_dp_write(mtk_dp, offset + i * 2, val))458 return;459 }460}461 462static void mtk_dp_msa_bypass_enable(struct mtk_dp *mtk_dp, bool enable)463{464 u32 mask = HTOTAL_SEL_DP_ENC0_P0 | VTOTAL_SEL_DP_ENC0_P0 |465 HSTART_SEL_DP_ENC0_P0 | VSTART_SEL_DP_ENC0_P0 |466 HWIDTH_SEL_DP_ENC0_P0 | VHEIGHT_SEL_DP_ENC0_P0 |467 HSP_SEL_DP_ENC0_P0 | HSW_SEL_DP_ENC0_P0 |468 VSP_SEL_DP_ENC0_P0 | VSW_SEL_DP_ENC0_P0;469 470 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030, enable ? 0 : mask, mask);471}472 473static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)474{475 struct drm_display_mode mode;476 struct videomode *vm = &mtk_dp->info.vm;477 478 drm_display_mode_from_videomode(vm, &mode);479 480 /* horizontal */481 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3010,482 mode.htotal, HTOTAL_SW_DP_ENC0_P0_MASK);483 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3018,484 vm->hsync_len + vm->hback_porch,485 HSTART_SW_DP_ENC0_P0_MASK);486 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,487 vm->hsync_len, HSW_SW_DP_ENC0_P0_MASK);488 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,489 0, HSP_SW_DP_ENC0_P0_MASK);490 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3020,491 vm->hactive, HWIDTH_SW_DP_ENC0_P0_MASK);492 493 /* vertical */494 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3014,495 mode.vtotal, VTOTAL_SW_DP_ENC0_P0_MASK);496 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_301C,497 vm->vsync_len + vm->vback_porch,498 VSTART_SW_DP_ENC0_P0_MASK);499 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,500 vm->vsync_len, VSW_SW_DP_ENC0_P0_MASK);501 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,502 0, VSP_SW_DP_ENC0_P0_MASK);503 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3024,504 vm->vactive, VHEIGHT_SW_DP_ENC0_P0_MASK);505 506 /* horizontal */507 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3064,508 vm->hactive, HDE_NUM_LAST_DP_ENC0_P0_MASK);509 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3154,510 mode.htotal, PGEN_HTOTAL_DP_ENC0_P0_MASK);511 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3158,512 vm->hfront_porch,513 PGEN_HSYNC_RISING_DP_ENC0_P0_MASK);514 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C,515 vm->hsync_len,516 PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);517 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,518 vm->hback_porch + vm->hsync_len,519 PGEN_HFDE_START_DP_ENC0_P0_MASK);520 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164,521 vm->hactive,522 PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);523 524 /* vertical */525 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3168,526 mode.vtotal,527 PGEN_VTOTAL_DP_ENC0_P0_MASK);528 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_316C,529 vm->vfront_porch,530 PGEN_VSYNC_RISING_DP_ENC0_P0_MASK);531 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170,532 vm->vsync_len,533 PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);534 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,535 vm->vback_porch + vm->vsync_len,536 PGEN_VFDE_START_DP_ENC0_P0_MASK);537 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178,538 vm->vactive,539 PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);540}541 542static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,543 enum dp_pixelformat color_format)544{545 u32 val;546 547 /* update MISC0 */548 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,549 color_format << DP_TEST_COLOR_FORMAT_SHIFT,550 DP_TEST_COLOR_FORMAT_MASK);551 552 switch (color_format) {553 case DP_PIXELFORMAT_YUV422:554 val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;555 break;556 case DP_PIXELFORMAT_RGB:557 val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;558 break;559 default:560 drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",561 color_format);562 return -EINVAL;563 }564 565 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,566 val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);567 return 0;568}569 570static void mtk_dp_set_color_depth(struct mtk_dp *mtk_dp)571{572 /* Only support 8 bits currently */573 /* Update MISC0 */574 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,575 DP_MSA_MISC_8_BPC, DP_TEST_BIT_DEPTH_MASK);576 577 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,578 VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT,579 VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK);580}581 582static void mtk_dp_config_mn_mode(struct mtk_dp *mtk_dp)583{584 /* 0: hw mode, 1: sw mode */585 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,586 0, VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK);587}588 589static void mtk_dp_set_sram_read_start(struct mtk_dp *mtk_dp, u32 val)590{591 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,592 val, SRAM_START_READ_THRD_DP_ENC0_P0_MASK);593}594 595static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)596{597 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,598 VIDEO_MN_GEN_EN_DP_ENC0_P0,599 VIDEO_MN_GEN_EN_DP_ENC0_P0);600 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,601 SDP_DOWN_CNT_DP_ENC0_P0_VAL,602 SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);603 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,604 SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL,605 SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);606 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3300,607 VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL << 8,608 VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK);609 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,610 FIFO_READ_START_POINT_DP_ENC1_P0_VAL << 12,611 FIFO_READ_START_POINT_DP_ENC1_P0_MASK);612 mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368, DP_ENC1_P0_3368_VAL);613}614 615static void mtk_dp_pg_enable(struct mtk_dp *mtk_dp, bool enable)616{617 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3038,618 enable ? VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK : 0,619 VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK);620 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31B0,621 PGEN_PATTERN_SEL_VAL << 4, PGEN_PATTERN_SEL_MASK);622}623 624static void mtk_dp_audio_setup_channels(struct mtk_dp *mtk_dp,625 struct mtk_dp_audio_cfg *cfg)626{627 u32 channel_enable_bits;628 629 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3324,630 AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX,631 AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK);632 633 /* audio channel count change reset */634 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4,635 DP_ENC_DUMMY_RW_1, DP_ENC_DUMMY_RW_1);636 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304,637 AU_PRTY_REGEN_DP_ENC1_P0_MASK |638 AU_CH_STS_REGEN_DP_ENC1_P0_MASK |639 AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK,640 AU_PRTY_REGEN_DP_ENC1_P0_MASK |641 AU_CH_STS_REGEN_DP_ENC1_P0_MASK |642 AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK);643 644 switch (cfg->channels) {645 case 2:646 channel_enable_bits = AUDIO_2CH_SEL_DP_ENC0_P0_MASK |647 AUDIO_2CH_EN_DP_ENC0_P0_MASK;648 break;649 case 8:650 default:651 channel_enable_bits = AUDIO_8CH_SEL_DP_ENC0_P0_MASK |652 AUDIO_8CH_EN_DP_ENC0_P0_MASK;653 break;654 }655 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088,656 channel_enable_bits | AU_EN_DP_ENC0_P0,657 AUDIO_2CH_SEL_DP_ENC0_P0_MASK |658 AUDIO_2CH_EN_DP_ENC0_P0_MASK |659 AUDIO_8CH_SEL_DP_ENC0_P0_MASK |660 AUDIO_8CH_EN_DP_ENC0_P0_MASK |661 AU_EN_DP_ENC0_P0);662 663 /* audio channel count change reset */664 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, 0, DP_ENC_DUMMY_RW_1);665 666 /* enable audio reset */667 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4,668 DP_ENC_DUMMY_RW_1_AUDIO_RST_EN,669 DP_ENC_DUMMY_RW_1_AUDIO_RST_EN);670}671 672static void mtk_dp_audio_channel_status_set(struct mtk_dp *mtk_dp,673 struct mtk_dp_audio_cfg *cfg)674{675 struct snd_aes_iec958 iec = { 0 };676 677 switch (cfg->sample_rate) {678 case 32000:679 iec.status[3] = IEC958_AES3_CON_FS_32000;680 break;681 case 44100:682 iec.status[3] = IEC958_AES3_CON_FS_44100;683 break;684 case 48000:685 iec.status[3] = IEC958_AES3_CON_FS_48000;686 break;687 case 88200:688 iec.status[3] = IEC958_AES3_CON_FS_88200;689 break;690 case 96000:691 iec.status[3] = IEC958_AES3_CON_FS_96000;692 break;693 case 192000:694 iec.status[3] = IEC958_AES3_CON_FS_192000;695 break;696 default:697 iec.status[3] = IEC958_AES3_CON_FS_NOTID;698 break;699 }700 701 switch (cfg->word_length_bits) {702 case 16:703 iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16;704 break;705 case 20:706 iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16 |707 IEC958_AES4_CON_MAX_WORDLEN_24;708 break;709 case 24:710 iec.status[4] = IEC958_AES4_CON_WORDLEN_24_20 |711 IEC958_AES4_CON_MAX_WORDLEN_24;712 break;713 default:714 iec.status[4] = IEC958_AES4_CON_WORDLEN_NOTID;715 }716 717 /* IEC 60958 consumer channel status bits */718 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_308C,719 0, CH_STATUS_0_DP_ENC0_P0_MASK);720 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3090,721 iec.status[3] << 8, CH_STATUS_1_DP_ENC0_P0_MASK);722 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3094,723 iec.status[4], CH_STATUS_2_DP_ENC0_P0_MASK);724}725 726static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,727 int channels)728{729 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_312C,730 (min(8, channels) - 1) << 8,731 ASP_HB2_DP_ENC0_P0_MASK | ASP_HB3_DP_ENC0_P0_MASK);732}733 734static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)735{736 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,737 mtk_dp->data->audio_m_div2_bit,738 AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);739}740 741static void mtk_dp_sdp_trigger_aui(struct mtk_dp *mtk_dp)742{743 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280,744 MTK_DP_SDP_AUI, SDP_PACKET_TYPE_DP_ENC1_P0_MASK);745 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280,746 SDP_PACKET_W_DP_ENC1_P0, SDP_PACKET_W_DP_ENC1_P0);747}748 749static void mtk_dp_sdp_set_data(struct mtk_dp *mtk_dp, u8 *data_bytes)750{751 mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_ENC1_P0_3200,752 data_bytes, 0x10);753}754 755static void mtk_dp_sdp_set_header_aui(struct mtk_dp *mtk_dp,756 struct dp_sdp_header *header)757{758 u32 db_addr = MTK_DP_ENC0_P0_30D8 + (MTK_DP_SDP_AUI - 1) * 8;759 760 mtk_dp_bulk_16bit_write(mtk_dp, db_addr, (u8 *)header, 4);761}762 763static void mtk_dp_disable_sdp_aui(struct mtk_dp *mtk_dp)764{765 /* Disable periodic send */766 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A8 & 0xfffc, 0,767 0xff << ((MTK_DP_ENC0_P0_30A8 & 3) * 8));768}769 770static void mtk_dp_setup_sdp_aui(struct mtk_dp *mtk_dp,771 struct dp_sdp *sdp)772{773 u32 shift;774 775 mtk_dp_sdp_set_data(mtk_dp, sdp->db);776 mtk_dp_sdp_set_header_aui(mtk_dp, &sdp->sdp_header);777 mtk_dp_disable_sdp_aui(mtk_dp);778 779 shift = (MTK_DP_ENC0_P0_30A8 & 3) * 8;780 781 mtk_dp_sdp_trigger_aui(mtk_dp);782 /* Enable periodic sending */783 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A8 & 0xfffc,784 0x05 << shift, 0xff << shift);785}786 787static void mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp)788{789 mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3640, DP_AUX_P0_3640_VAL);790}791 792static void mtk_dp_aux_set_cmd(struct mtk_dp *mtk_dp, u8 cmd, u32 addr)793{794 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3644,795 cmd, MCU_REQUEST_COMMAND_AUX_TX_P0_MASK);796 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3648,797 addr, MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK);798 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_364C,799 addr >> 16, MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK);800}801 802static void mtk_dp_aux_clear_fifo(struct mtk_dp *mtk_dp)803{804 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,805 MCU_ACK_TRAN_COMPLETE_AUX_TX_P0,806 MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 |807 PHY_FIFO_RST_AUX_TX_P0_MASK |808 MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);809}810 811static void mtk_dp_aux_request_ready(struct mtk_dp *mtk_dp)812{813 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3630,814 AUX_TX_REQUEST_READY_AUX_TX_P0,815 AUX_TX_REQUEST_READY_AUX_TX_P0);816}817 818static void mtk_dp_aux_fill_write_fifo(struct mtk_dp *mtk_dp, u8 *buf,819 size_t length)820{821 mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_AUX_P0_3708, buf, length);822}823 824static void mtk_dp_aux_read_rx_fifo(struct mtk_dp *mtk_dp, u8 *buf,825 size_t length, int read_delay)826{827 int read_pos;828 829 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620,830 0, AUX_RD_MODE_AUX_TX_P0_MASK);831 832 for (read_pos = 0; read_pos < length; read_pos++) {833 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620,834 AUX_RX_FIFO_READ_PULSE_TX_P0,835 AUX_RX_FIFO_READ_PULSE_TX_P0);836 837 /* Hardware needs time to update the data */838 usleep_range(read_delay, read_delay * 2);839 buf[read_pos] = (u8)(mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3620) &840 AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK);841 }842}843 844static void mtk_dp_aux_set_length(struct mtk_dp *mtk_dp, size_t length)845{846 if (length > 0) {847 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,848 (length - 1) << 12,849 MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);850 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,851 0,852 AUX_NO_LENGTH_AUX_TX_P0 |853 AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |854 AUX_RESERVED_RW_0_AUX_TX_P0_MASK);855 } else {856 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,857 AUX_NO_LENGTH_AUX_TX_P0,858 AUX_NO_LENGTH_AUX_TX_P0 |859 AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |860 AUX_RESERVED_RW_0_AUX_TX_P0_MASK);861 }862}863 864static int mtk_dp_aux_wait_for_completion(struct mtk_dp *mtk_dp, bool is_read)865{866 int wait_reply = MTK_DP_AUX_WAIT_REPLY_COUNT;867 868 while (--wait_reply) {869 u32 aux_irq_status;870 871 if (is_read) {872 u32 fifo_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3618);873 874 if (fifo_status &875 (AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK |876 AUX_RX_FIFO_FULL_AUX_TX_P0_MASK)) {877 return 0;878 }879 }880 881 aux_irq_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3640);882 if (aux_irq_status & AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0)883 return 0;884 885 if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0)886 return -ETIMEDOUT;887 888 /* Give the hardware a chance to reach completion before retrying */889 usleep_range(100, 500);890 }891 892 return -ETIMEDOUT;893}894 895static int mtk_dp_aux_do_transfer(struct mtk_dp *mtk_dp, bool is_read, u8 cmd,896 u32 addr, u8 *buf, size_t length, u8 *reply_cmd)897{898 int ret;899 900 if (is_read && (length > DP_AUX_MAX_PAYLOAD_BYTES ||901 (cmd == DP_AUX_NATIVE_READ && !length)))902 return -EINVAL;903 904 if (!is_read)905 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3704,906 AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0,907 AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0);908 909 /* We need to clear fifo and irq before sending commands to the sink device. */910 mtk_dp_aux_clear_fifo(mtk_dp);911 mtk_dp_aux_irq_clear(mtk_dp);912 913 mtk_dp_aux_set_cmd(mtk_dp, cmd, addr);914 mtk_dp_aux_set_length(mtk_dp, length);915 916 if (!is_read) {917 if (length)918 mtk_dp_aux_fill_write_fifo(mtk_dp, buf, length);919 920 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3704,921 AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK,922 AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK);923 }924 925 mtk_dp_aux_request_ready(mtk_dp);926 927 /* Wait for feedback from sink device. */928 ret = mtk_dp_aux_wait_for_completion(mtk_dp, is_read);929 930 *reply_cmd = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3624) &931 AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK;932 933 if (ret) {934 u32 phy_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3628) &935 AUX_RX_PHY_STATE_AUX_TX_P0_MASK;936 if (phy_status != AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE) {937 dev_err(mtk_dp->dev,938 "AUX Rx Aux hang, need SW reset\n");939 return -EIO;940 }941 942 return -ETIMEDOUT;943 }944 945 if (!length) {946 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,947 0,948 AUX_NO_LENGTH_AUX_TX_P0 |949 AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |950 AUX_RESERVED_RW_0_AUX_TX_P0_MASK);951 } else if (is_read) {952 int read_delay;953 954 if (cmd == (DP_AUX_I2C_READ | DP_AUX_I2C_MOT) ||955 cmd == DP_AUX_I2C_READ)956 read_delay = 500;957 else958 read_delay = 100;959 960 mtk_dp_aux_read_rx_fifo(mtk_dp, buf, length, read_delay);961 }962 963 return 0;964}965 966static void mtk_dp_set_swing_pre_emphasis(struct mtk_dp *mtk_dp, int lane_num,967 int swing_val, int preemphasis)968{969 u32 lane_shift = lane_num * DP_TX1_VOLT_SWING_SHIFT;970 971 dev_dbg(mtk_dp->dev,972 "link training: swing_val = 0x%x, pre-emphasis = 0x%x\n",973 swing_val, preemphasis);974 975 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,976 swing_val << (DP_TX0_VOLT_SWING_SHIFT + lane_shift),977 DP_TX0_VOLT_SWING_MASK << lane_shift);978 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,979 preemphasis << (DP_TX0_PRE_EMPH_SHIFT + lane_shift),980 DP_TX0_PRE_EMPH_MASK << lane_shift);981}982 983static void mtk_dp_reset_swing_pre_emphasis(struct mtk_dp *mtk_dp)984{985 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,986 0,987 DP_TX0_VOLT_SWING_MASK |988 DP_TX1_VOLT_SWING_MASK |989 DP_TX2_VOLT_SWING_MASK |990 DP_TX3_VOLT_SWING_MASK |991 DP_TX0_PRE_EMPH_MASK |992 DP_TX1_PRE_EMPH_MASK |993 DP_TX2_PRE_EMPH_MASK |994 DP_TX3_PRE_EMPH_MASK);995}996 997static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp)998{999 u32 irq_status = mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_35D0) &1000 SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK;1001 1002 if (irq_status) {1003 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8,1004 irq_status, SW_IRQ_CLR_DP_TRANS_P0_MASK);1005 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8,1006 0, SW_IRQ_CLR_DP_TRANS_P0_MASK);1007 }1008 1009 return irq_status;1010}1011 1012static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)1013{1014 u32 irq_status = (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) &1015 IRQ_STATUS_DP_TRANS_P0_MASK) >> 12;1016 1017 if (irq_status) {1018 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,1019 irq_status, IRQ_CLR_DP_TRANS_P0_MASK);1020 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,1021 0, IRQ_CLR_DP_TRANS_P0_MASK);1022 }1023 1024 return irq_status;1025}1026 1027static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)1028{1029 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,1030 enable ? 0 :1031 IRQ_MASK_DP_TRANS_P0_DISC_IRQ |1032 IRQ_MASK_DP_TRANS_P0_CONN_IRQ |1033 IRQ_MASK_DP_TRANS_P0_INT_IRQ,1034 IRQ_MASK_DP_TRANS_P0_MASK);1035}1036 1037static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)1038{1039 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_342C,1040 XTAL_FREQ_DP_TRANS_P0_DEFAULT,1041 XTAL_FREQ_DP_TRANS_P0_MASK);1042 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3540,1043 FEC_CLOCK_EN_MODE_DP_TRANS_P0,1044 FEC_CLOCK_EN_MODE_DP_TRANS_P0);1045 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC,1046 AUDIO_CH_SRC_SEL_DP_ENC0_P0,1047 AUDIO_CH_SRC_SEL_DP_ENC0_P0);1048 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,1049 0, SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK);1050 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,1051 IRQ_MASK_AUX_TOP_IRQ, IRQ_MASK_AUX_TOP_IRQ);1052}1053 1054static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)1055{1056 u32 val;1057 /* Debounce threshold */1058 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,1059 8, HPD_DEB_THD_DP_TRANS_P0_MASK);1060 1061 val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US |1062 HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4;1063 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,1064 val, HPD_INT_THD_DP_TRANS_P0_MASK);1065 1066 /*1067 * Connect threshold 1.5ms + 5 x 0.1ms = 2ms1068 * Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms1069 */1070 val = (5 << 8) | (5 << 12);1071 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,1072 val,1073 HPD_DISC_THD_DP_TRANS_P0_MASK |1074 HPD_CONN_THD_DP_TRANS_P0_MASK);1075 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3430,1076 HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT,1077 HPD_INT_THD_ECO_DP_TRANS_P0_MASK);1078}1079 1080static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)1081{1082 /* modify timeout threshold = 0x1595 */1083 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_360C,1084 AUX_TIMEOUT_THR_AUX_TX_P0_VAL,1085 AUX_TIMEOUT_THR_AUX_TX_P0_MASK);1086 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3658,1087 0, AUX_TX_OV_EN_AUX_TX_P0_MASK);1088 /* 25 for 26M */1089 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3634,1090 AUX_TX_OVER_SAMPLE_RATE_FOR_26M << 8,1091 AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK);1092 /* 13 for 26M */1093 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3614,1094 AUX_RX_UI_CNT_THR_AUX_FOR_26M,1095 AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK);1096 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_37C8,1097 MTK_ATOP_EN_AUX_TX_P0,1098 MTK_ATOP_EN_AUX_TX_P0);1099 1100 /* Set complete reply mode for AUX */1101 mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3690,1102 RX_REPLY_COMPLETE_MODE_AUX_TX_P0,1103 RX_REPLY_COMPLETE_MODE_AUX_TX_P0);1104}1105 1106static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)1107{1108 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,1109 0, VBID_VIDEO_MUTE_DP_ENC0_P0_MASK);1110 1111 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,1112 BS2BS_MODE_DP_ENC1_P0_VAL << 12,1113 BS2BS_MODE_DP_ENC1_P0_MASK);1114 1115 /* dp tx encoder reset all sw */1116 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,1117 DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,1118 DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);1119 1120 /* Wait for sw reset to complete */1121 usleep_range(1000, 5000);1122 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,1123 0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);1124}1125 1126static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)1127{1128 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,1129 DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0,1130 DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);1131 1132 /* Wait for sw reset to complete */1133 usleep_range(1000, 5000);1134 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,1135 0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);1136}1137 1138static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)1139{1140 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,1141 lanes == 0 ? 0 : DP_TRANS_DUMMY_RW_0,1142 DP_TRANS_DUMMY_RW_0_MASK);1143 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,1144 lanes, LANE_NUM_DP_ENC0_P0_MASK);1145 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_34A4,1146 lanes << 2, LANE_NUM_DP_TRANS_P0_MASK);1147}1148 1149static void mtk_dp_get_calibration_data(struct mtk_dp *mtk_dp)1150{1151 const struct mtk_dp_efuse_fmt *fmt;1152 struct device *dev = mtk_dp->dev;1153 struct nvmem_cell *cell;1154 u32 *cal_data = mtk_dp->cal_data;1155 u32 *buf;1156 int i;1157 size_t len;1158 1159 cell = nvmem_cell_get(dev, "dp_calibration_data");1160 if (IS_ERR(cell)) {1161 dev_warn(dev, "Failed to get nvmem cell dp_calibration_data\n");1162 goto use_default_val;1163 }1164 1165 buf = (u32 *)nvmem_cell_read(cell, &len);1166 nvmem_cell_put(cell);1167 1168 if (IS_ERR(buf) || ((len / sizeof(u32)) != 4)) {1169 dev_warn(dev, "Failed to read nvmem_cell_read\n");1170 1171 if (!IS_ERR(buf))1172 kfree(buf);1173 1174 goto use_default_val;1175 }1176 1177 for (i = 0; i < MTK_DP_CAL_MAX; i++) {1178 fmt = &mtk_dp->data->efuse_fmt[i];1179 cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt->mask;1180 1181 if (cal_data[i] < fmt->min_val || cal_data[i] > fmt->max_val) {1182 dev_warn(mtk_dp->dev, "Invalid efuse data, idx = %d\n", i);1183 kfree(buf);1184 goto use_default_val;1185 }1186 }1187 kfree(buf);1188 1189 return;1190 1191use_default_val:1192 dev_warn(mtk_dp->dev, "Use default calibration data\n");1193 for (i = 0; i < MTK_DP_CAL_MAX; i++)1194 cal_data[i] = mtk_dp->data->efuse_fmt[i].default_val;1195}1196 1197static void mtk_dp_set_calibration_data(struct mtk_dp *mtk_dp)1198{1199 u32 *cal_data = mtk_dp->cal_data;1200 1201 mtk_dp_update_bits(mtk_dp, DP_PHY_GLB_DPAUX_TX,1202 cal_data[MTK_DP_CAL_CLKTX_IMPSE] << 20,1203 RG_CKM_PT0_CKTX_IMPSEL);1204 mtk_dp_update_bits(mtk_dp, DP_PHY_GLB_BIAS_GEN_00,1205 cal_data[MTK_DP_CAL_GLB_BIAS_TRIM] << 16,1206 RG_XTP_GLB_BIAS_INTR_CTRL);1207 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,1208 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] << 12,1209 RG_XTP_LN0_TX_IMPSEL_PMOS);1210 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,1211 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] << 16,1212 RG_XTP_LN0_TX_IMPSEL_NMOS);1213 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,1214 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] << 12,1215 RG_XTP_LN1_TX_IMPSEL_PMOS);1216 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,1217 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] << 16,1218 RG_XTP_LN1_TX_IMPSEL_NMOS);1219 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,1220 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] << 12,1221 RG_XTP_LN2_TX_IMPSEL_PMOS);1222 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,1223 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] << 16,1224 RG_XTP_LN2_TX_IMPSEL_NMOS);1225 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,1226 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] << 12,1227 RG_XTP_LN3_TX_IMPSEL_PMOS);1228 mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,1229 cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] << 16,1230 RG_XTP_LN3_TX_IMPSEL_NMOS);1231}1232 1233static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,1234 u32 link_rate, int lane_count)1235{1236 int ret;1237 union phy_configure_opts phy_opts = {1238 .dp = {1239 .link_rate = drm_dp_bw_code_to_link_rate(link_rate) / 100,1240 .set_rate = 1,1241 .lanes = lane_count,1242 .set_lanes = 1,1243 .ssc = mtk_dp->train_info.sink_ssc,1244 }1245 };1246 1247 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,1248 DP_PWR_STATE_MASK);1249 1250 ret = phy_configure(mtk_dp->phy, &phy_opts);1251 if (ret)1252 return ret;1253 1254 mtk_dp_set_calibration_data(mtk_dp);1255 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,1256 DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);1257 1258 return 0;1259}1260 1261static void mtk_dp_set_idle_pattern(struct mtk_dp *mtk_dp, bool enable)1262{1263 u32 val = POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK |1264 POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK |1265 POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK |1266 POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK;1267 1268 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3580,1269 enable ? val : 0, val);1270}1271 1272static void mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int pattern)1273{1274 /* TPS1 */1275 if (pattern == 1)1276 mtk_dp_set_idle_pattern(mtk_dp, false);1277 1278 mtk_dp_update_bits(mtk_dp,1279 MTK_DP_TRANS_P0_3400,1280 pattern ? BIT(pattern - 1) << 12 : 0,1281 PATTERN1_EN_DP_TRANS_P0_MASK |1282 PATTERN2_EN_DP_TRANS_P0_MASK |1283 PATTERN3_EN_DP_TRANS_P0_MASK |1284 PATTERN4_EN_DP_TRANS_P0_MASK);1285}1286 1287static void mtk_dp_set_enhanced_frame_mode(struct mtk_dp *mtk_dp)1288{1289 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,1290 ENHANCED_FRAME_EN_DP_ENC0_P0,1291 ENHANCED_FRAME_EN_DP_ENC0_P0);1292}1293 1294static void mtk_dp_training_set_scramble(struct mtk_dp *mtk_dp, bool enable)1295{1296 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3404,1297 enable ? DP_SCR_EN_DP_TRANS_P0_MASK : 0,1298 DP_SCR_EN_DP_TRANS_P0_MASK);1299}1300 1301static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable)1302{1303 struct arm_smccc_res res;1304 u32 val = VIDEO_MUTE_SEL_DP_ENC0_P0 |1305 (enable ? VIDEO_MUTE_SW_DP_ENC0_P0 : 0);1306 1307 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,1308 val,1309 VIDEO_MUTE_SEL_DP_ENC0_P0 |1310 VIDEO_MUTE_SW_DP_ENC0_P0);1311 1312 arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32,1313 mtk_dp->data->smc_cmd, enable,1314 0, 0, 0, 0, 0, &res);1315 1316 dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n",1317 mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1);1318}1319 1320static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute)1321{1322 u32 val[3];1323 1324 if (mute) {1325 val[0] = VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 |1326 VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0;1327 val[1] = 0;1328 val[2] = 0;1329 } else {1330 val[0] = 0;1331 val[1] = AU_EN_DP_ENC0_P0;1332 /* Send one every two frames */1333 val[2] = 0x0F;1334 }1335 1336 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030,1337 val[0],1338 VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 |1339 VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0);1340 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088,1341 val[1], AU_EN_DP_ENC0_P0);1342 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4,1343 val[2], AU_TS_CFG_DP_ENC0_P0_MASK);1344}1345 1346static void mtk_dp_aux_panel_poweron(struct mtk_dp *mtk_dp, bool pwron)1347{1348 if (pwron) {1349 /* power on aux */1350 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,1351 DP_PWR_STATE_BANDGAP_TPLL_LANE,1352 DP_PWR_STATE_MASK);1353 1354 /* power on panel */1355 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);1356 usleep_range(2000, 5000);1357 } else {1358 /* power off panel */1359 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);1360 usleep_range(2000, 3000);1361 1362 /* power off aux */1363 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,1364 DP_PWR_STATE_BANDGAP_TPLL,1365 DP_PWR_STATE_MASK);1366 }1367}1368 1369static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)1370{1371 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,1372 0, SW_RST_B_PHYD);1373 1374 /* Wait for power enable */1375 usleep_range(10, 200);1376 1377 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,1378 SW_RST_B_PHYD, SW_RST_B_PHYD);1379 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,1380 DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK);1381 mtk_dp_write(mtk_dp, MTK_DP_1040,1382 RG_DPAUX_RX_VALID_DEGLITCH_EN | RG_XTP_GLB_CKDET_EN |1383 RG_DPAUX_RX_EN);1384 mtk_dp_update_bits(mtk_dp, MTK_DP_0034, 0, DA_CKM_CKTX0_EN_FORCE_EN);1385}1386 1387static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)1388{1389 mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);1390 1391 mtk_dp_update_bits(mtk_dp, MTK_DP_0034,1392 DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);1393 1394 /* Disable RX */1395 mtk_dp_write(mtk_dp, MTK_DP_1040, 0);1396 mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,1397 0x550 | FUSE_SEL | MEM_ISO_EN);1398}1399 1400static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp)1401{1402 bool plugged_in = (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP);1403 1404 mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;1405 mtk_dp->train_info.lane_count = mtk_dp->max_lanes;1406 mtk_dp->train_info.cable_plugged_in = plugged_in;1407 1408 mtk_dp->info.format = DP_PIXELFORMAT_RGB;1409 memset(&mtk_dp->info.vm, 0, sizeof(struct videomode));1410 mtk_dp->audio_enable = false;1411}1412 1413static void mtk_dp_sdp_set_down_cnt_init(struct mtk_dp *mtk_dp,1414 u32 sram_read_start)1415{1416 u32 sdp_down_cnt_init = 0;1417 struct drm_display_mode mode;1418 struct videomode *vm = &mtk_dp->info.vm;1419 1420 drm_display_mode_from_videomode(vm, &mode);1421 1422 if (mode.clock > 0)1423 sdp_down_cnt_init = sram_read_start *1424 mtk_dp->train_info.link_rate * 2700 * 8 /1425 (mode.clock * 4);1426 1427 switch (mtk_dp->train_info.lane_count) {1428 case 1:1429 sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 0x1A);1430 break;1431 case 2:1432 /* case for LowResolution && High Audio Sample Rate */1433 sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 0x10);1434 sdp_down_cnt_init += mode.vtotal <= 525 ? 4 : 0;1435 break;1436 case 4:1437 default:1438 sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 6);1439 break;1440 }1441 1442 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,1443 sdp_down_cnt_init,1444 SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);1445}1446 1447static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)1448{1449 int pix_clk_mhz;1450 u32 dc_offset;1451 u32 spd_down_cnt_init = 0;1452 struct drm_display_mode mode;1453 struct videomode *vm = &mtk_dp->info.vm;1454 1455 drm_display_mode_from_videomode(vm, &mode);1456 1457 pix_clk_mhz = mtk_dp->info.format == DP_PIXELFORMAT_YUV420 ?1458 mode.clock / 2000 : mode.clock / 1000;1459 1460 switch (mtk_dp->train_info.lane_count) {1461 case 1:1462 spd_down_cnt_init = 0x20;1463 break;1464 case 2:1465 dc_offset = (mode.vtotal <= 525) ? 0x14 : 0x00;1466 spd_down_cnt_init = 0x18 + dc_offset;1467 break;1468 case 4:1469 default:1470 dc_offset = (mode.vtotal <= 525) ? 0x08 : 0x00;1471 if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27)1472 spd_down_cnt_init = 0x8;1473 else1474 spd_down_cnt_init = 0x10 + dc_offset;1475 break;1476 }1477 1478 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364, spd_down_cnt_init,1479 SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);1480}1481 1482static void mtk_dp_audio_sample_arrange_disable(struct mtk_dp *mtk_dp)1483{1484 /* arrange audio packets into the Hblanking and Vblanking area */1485 if (!mtk_dp->data->audio_pkt_in_hblank_area)1486 return;1487 1488 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,1489 SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK);1490 mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,1491 SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK);1492}1493 1494static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)1495{1496 u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,1497 mtk_dp->info.vm.hactive /1498 mtk_dp->train_info.lane_count /1499 MTK_DP_4P1T / MTK_DP_HDE /1500 MTK_DP_PIX_PER_ADDR);1501 mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);1502 mtk_dp_setup_encoder(mtk_dp);1503 mtk_dp_audio_sample_arrange_disable(mtk_dp);1504 mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);1505 mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);1506}1507 1508static void mtk_dp_set_tx_out(struct mtk_dp *mtk_dp)1509{1510 mtk_dp_setup_tu(mtk_dp);1511}1512 1513static void mtk_dp_train_update_swing_pre(struct mtk_dp *mtk_dp, int lanes,1514 u8 dpcd_adjust_req[2])1515{1516 int lane;1517 1518 for (lane = 0; lane < lanes; ++lane) {1519 u8 val;1520 u8 swing;1521 u8 preemphasis;1522 int index = lane / 2;1523 int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;1524 1525 swing = (dpcd_adjust_req[index] >> shift) &1526 DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;1527 preemphasis = ((dpcd_adjust_req[index] >> shift) &1528 DP_ADJUST_PRE_EMPHASIS_LANE0_MASK) >>1529 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;1530 val = swing << DP_TRAIN_VOLTAGE_SWING_SHIFT |1531 preemphasis << DP_TRAIN_PRE_EMPHASIS_SHIFT;1532 1533 if (swing == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)1534 val |= DP_TRAIN_MAX_SWING_REACHED;1535 if (preemphasis == 3)1536 val |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;1537 1538 mtk_dp_set_swing_pre_emphasis(mtk_dp, lane, swing, preemphasis);1539 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane,1540 val);1541 }1542}1543 1544static void mtk_dp_pattern(struct mtk_dp *mtk_dp, bool is_tps1)1545{1546 int pattern;1547 unsigned int aux_offset;1548 1549 if (is_tps1) {1550 pattern = 1;1551 aux_offset = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1;1552 } else {1553 aux_offset = mtk_dp->train_info.channel_eq_pattern;1554 1555 switch (mtk_dp->train_info.channel_eq_pattern) {1556 case DP_TRAINING_PATTERN_4:1557 pattern = 4;1558 break;1559 case DP_TRAINING_PATTERN_3:1560 pattern = 3;1561 aux_offset |= DP_LINK_SCRAMBLING_DISABLE;1562 break;1563 case DP_TRAINING_PATTERN_2:1564 default:1565 pattern = 2;1566 aux_offset |= DP_LINK_SCRAMBLING_DISABLE;1567 break;1568 }1569 }1570 1571 mtk_dp_train_set_pattern(mtk_dp, pattern);1572 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, aux_offset);1573}1574 1575static int mtk_dp_train_setting(struct mtk_dp *mtk_dp, u8 target_link_rate,1576 u8 target_lane_count)1577{1578 int ret;1579 1580 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate);1581 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,1582 target_lane_count | DP_LANE_COUNT_ENHANCED_FRAME_EN);1583 1584 if (mtk_dp->train_info.sink_ssc)1585 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,1586 DP_SPREAD_AMP_0_5);1587 1588 mtk_dp_set_lanes(mtk_dp, target_lane_count / 2);1589 ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, target_lane_count);1590 if (ret)1591 return ret;1592 1593 dev_dbg(mtk_dp->dev,1594 "Link train target_link_rate = 0x%x, target_lane_count = 0x%x\n",1595 target_link_rate, target_lane_count);1596 1597 return 0;1598}1599 1600static int mtk_dp_train_cr(struct mtk_dp *mtk_dp, u8 target_lane_count)1601{1602 u8 lane_adjust[2] = {};1603 u8 link_status[DP_LINK_STATUS_SIZE] = {};1604 u8 prev_lane_adjust = 0xff;1605 int train_retries = 0;1606 int voltage_retries = 0;1607 1608 mtk_dp_pattern(mtk_dp, true);1609 1610 /* In DP spec 1.4, the retry count of CR is defined as 10. */1611 do {1612 train_retries++;1613 if (!mtk_dp->train_info.cable_plugged_in) {1614 mtk_dp_train_set_pattern(mtk_dp, 0);1615 return -ENODEV;1616 }1617 1618 drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,1619 lane_adjust, sizeof(lane_adjust));1620 mtk_dp_train_update_swing_pre(mtk_dp, target_lane_count,1621 lane_adjust);1622 1623 drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux,1624 mtk_dp->rx_cap);1625 1626 /* check link status from sink device */1627 drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);1628 if (drm_dp_clock_recovery_ok(link_status,1629 target_lane_count)) {1630 dev_dbg(mtk_dp->dev, "Link train CR pass\n");1631 return 0;1632 }1633 1634 /*1635 * In DP spec 1.4, if current voltage level is the same1636 * with previous voltage level, we need to retry 5 times.1637 */1638 if (prev_lane_adjust == link_status[4]) {1639 voltage_retries++;1640 /*1641 * Condition of CR fail:1642 * 1. Failed to pass CR using the same voltage1643 * level over five times.1644 * 2. Failed to pass CR when the current voltage1645 * level is the same with previous voltage1646 * level and reach max voltage level (3).1647 */1648 if (voltage_retries > MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY ||1649 (prev_lane_adjust & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) == 3) {1650 dev_dbg(mtk_dp->dev, "Link train CR fail\n");1651 break;1652 }1653 } else {1654 /*1655 * If the voltage level is changed, we need to1656 * re-calculate this retry count.1657 */1658 voltage_retries = 0;1659 }1660 prev_lane_adjust = link_status[4];1661 } while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);1662 1663 /* Failed to train CR, and disable pattern. */1664 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,1665 DP_TRAINING_PATTERN_DISABLE);1666 mtk_dp_train_set_pattern(mtk_dp, 0);1667 1668 return -ETIMEDOUT;1669}1670 1671static int mtk_dp_train_eq(struct mtk_dp *mtk_dp, u8 target_lane_count)1672{1673 u8 lane_adjust[2] = {};1674 u8 link_status[DP_LINK_STATUS_SIZE] = {};1675 int train_retries = 0;1676 1677 mtk_dp_pattern(mtk_dp, false);1678 1679 do {1680 train_retries++;1681 if (!mtk_dp->train_info.cable_plugged_in) {1682 mtk_dp_train_set_pattern(mtk_dp, 0);1683 return -ENODEV;1684 }1685 1686 drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,1687 lane_adjust, sizeof(lane_adjust));1688 mtk_dp_train_update_swing_pre(mtk_dp, target_lane_count,1689 lane_adjust);1690 1691 drm_dp_link_train_channel_eq_delay(&mtk_dp->aux,1692 mtk_dp->rx_cap);1693 1694 /* check link status from sink device */1695 drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);1696 if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {1697 dev_dbg(mtk_dp->dev, "Link train EQ pass\n");1698 1699 /* Training done, and disable pattern. */1700 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,1701 DP_TRAINING_PATTERN_DISABLE);1702 mtk_dp_train_set_pattern(mtk_dp, 0);1703 return 0;1704 }1705 dev_dbg(mtk_dp->dev, "Link train EQ fail\n");1706 } while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);1707 1708 /* Failed to train EQ, and disable pattern. */1709 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,1710 DP_TRAINING_PATTERN_DISABLE);1711 mtk_dp_train_set_pattern(mtk_dp, 0);1712 1713 return -ETIMEDOUT;1714}1715 1716static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)1717{1718 u8 val;1719 ssize_t ret;1720 1721 /*1722 * If we're eDP and capabilities were already parsed we can skip1723 * reading again because eDP panels aren't hotpluggable hence the1724 * caps and training information won't ever change in a boot life1725 */1726 if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP &&1727 mtk_dp->rx_cap[DP_MAX_LINK_RATE] &&1728 mtk_dp->train_info.sink_ssc)1729 return 0;1730 1731 ret = drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);1732 if (ret < 0)1733 return ret;1734 1735 if (drm_dp_tps4_supported(mtk_dp->rx_cap))1736 mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_4;1737 else if (drm_dp_tps3_supported(mtk_dp->rx_cap))1738 mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_3;1739 else1740 mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_2;1741 1742 mtk_dp->train_info.sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap);1743 1744 ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);1745 if (ret < 1) {1746 drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n");1747 return ret == 0 ? -EIO : ret;1748 }1749 1750 if (val & DP_MST_CAP) {1751 /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */1752 ret = drm_dp_dpcd_readb(&mtk_dp->aux,1753 DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,1754 &val);1755 if (ret < 1) {1756 drm_err(mtk_dp->drm_dev, "Read irq vector failed\n");1757 return ret == 0 ? -EIO : ret;1758 }1759 1760 if (val) {1761 ret = drm_dp_dpcd_writeb(&mtk_dp->aux,1762 DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,1763 val);1764 if (ret < 0)1765 return ret;1766 }1767 }1768 1769 return 0;1770}1771 1772static bool mtk_dp_edid_parse_audio_capabilities(struct mtk_dp *mtk_dp,1773 struct mtk_dp_audio_cfg *cfg)1774{1775 if (!mtk_dp->data->audio_supported)1776 return false;1777 1778 if (mtk_dp->info.audio_cur_cfg.sad_count <= 0) {1779 drm_info(mtk_dp->drm_dev, "The SADs is NULL\n");1780 return false;1781 }1782 1783 return true;1784}1785 1786static void mtk_dp_train_change_mode(struct mtk_dp *mtk_dp)1787{1788 phy_reset(mtk_dp->phy);1789 mtk_dp_reset_swing_pre_emphasis(mtk_dp);1790}1791 1792static int mtk_dp_training(struct mtk_dp *mtk_dp)1793{1794 int ret;1795 u8 lane_count, link_rate, train_limit, max_link_rate;1796 1797 link_rate = min_t(u8, mtk_dp->max_linkrate,1798 mtk_dp->rx_cap[DP_MAX_LINK_RATE]);1799 max_link_rate = link_rate;1800 lane_count = min_t(u8, mtk_dp->max_lanes,1801 drm_dp_max_lane_count(mtk_dp->rx_cap));1802 1803 /*1804 * TPS are generated by the hardware pattern generator. From the1805 * hardware setting we need to disable this scramble setting before1806 * use the TPS pattern generator.1807 */1808 mtk_dp_training_set_scramble(mtk_dp, false);1809 1810 for (train_limit = 6; train_limit > 0; train_limit--) {1811 mtk_dp_train_change_mode(mtk_dp);1812 1813 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count);1814 if (ret)1815 return ret;1816 1817 ret = mtk_dp_train_cr(mtk_dp, lane_count);1818 if (ret == -ENODEV) {1819 return ret;1820 } else if (ret) {1821 /* reduce link rate */1822 switch (link_rate) {1823 case DP_LINK_BW_1_62:1824 lane_count = lane_count / 2;1825 link_rate = max_link_rate;1826 if (lane_count == 0)1827 return -EIO;1828 break;1829 case DP_LINK_BW_2_7:1830 link_rate = DP_LINK_BW_1_62;1831 break;1832 case DP_LINK_BW_5_4:1833 link_rate = DP_LINK_BW_2_7;1834 break;1835 case DP_LINK_BW_8_1:1836 link_rate = DP_LINK_BW_5_4;1837 break;1838 default:1839 return -EINVAL;1840 }1841 continue;1842 }1843 1844 ret = mtk_dp_train_eq(mtk_dp, lane_count);1845 if (ret == -ENODEV) {1846 return ret;1847 } else if (ret) {1848 /* reduce lane count */1849 if (lane_count == 0)1850 return -EIO;1851 lane_count /= 2;1852 continue;1853 }1854 1855 /* if we can run to this, training is done. */1856 break;1857 }1858 1859 if (train_limit == 0)1860 return -ETIMEDOUT;1861 1862 mtk_dp->train_info.link_rate = link_rate;1863 mtk_dp->train_info.lane_count = lane_count;1864 1865 /*1866 * After training done, we need to output normal stream instead of TPS,1867 * so we need to enable scramble.1868 */1869 mtk_dp_training_set_scramble(mtk_dp, true);1870 mtk_dp_set_enhanced_frame_mode(mtk_dp);1871 1872 return 0;1873}1874 1875static void mtk_dp_video_enable(struct mtk_dp *mtk_dp, bool enable)1876{1877 /* the mute sequence is different between enable and disable */1878 if (enable) {1879 mtk_dp_msa_bypass_enable(mtk_dp, false);1880 mtk_dp_pg_enable(mtk_dp, false);1881 mtk_dp_set_tx_out(mtk_dp);1882 mtk_dp_video_mute(mtk_dp, false);1883 } else {1884 mtk_dp_video_mute(mtk_dp, true);1885 mtk_dp_pg_enable(mtk_dp, true);1886 mtk_dp_msa_bypass_enable(mtk_dp, true);1887 }1888}1889 1890static void mtk_dp_audio_sdp_setup(struct mtk_dp *mtk_dp,1891 struct mtk_dp_audio_cfg *cfg)1892{1893 struct dp_sdp sdp;1894 struct hdmi_audio_infoframe frame;1895 1896 hdmi_audio_infoframe_init(&frame);1897 frame.coding_type = HDMI_AUDIO_CODING_TYPE_PCM;1898 frame.channels = cfg->channels;1899 frame.sample_frequency = cfg->sample_rate;1900 1901 switch (cfg->word_length_bits) {1902 case 16:1903 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;1904 break;1905 case 20:1906 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_20;1907 break;1908 case 24:1909 default:1910 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_24;1911 break;1912 }1913 1914 hdmi_audio_infoframe_pack_for_dp(&frame, &sdp, MTK_DP_VERSION);1915 1916 mtk_dp_audio_sdp_asp_set_channels(mtk_dp, cfg->channels);1917 mtk_dp_setup_sdp_aui(mtk_dp, &sdp);1918}1919 1920static void mtk_dp_audio_setup(struct mtk_dp *mtk_dp,1921 struct mtk_dp_audio_cfg *cfg)1922{1923 mtk_dp_audio_sdp_setup(mtk_dp, cfg);1924 mtk_dp_audio_channel_status_set(mtk_dp, cfg);1925 1926 mtk_dp_audio_setup_channels(mtk_dp, cfg);1927 mtk_dp_audio_set_divider(mtk_dp);1928}1929 1930static int mtk_dp_video_config(struct mtk_dp *mtk_dp)1931{1932 mtk_dp_config_mn_mode(mtk_dp);1933 mtk_dp_set_msa(mtk_dp);1934 mtk_dp_set_color_depth(mtk_dp);1935 return mtk_dp_set_color_format(mtk_dp, mtk_dp->info.format);1936}1937 1938static void mtk_dp_init_port(struct mtk_dp *mtk_dp)1939{1940 mtk_dp_set_idle_pattern(mtk_dp, true);1941 mtk_dp_initialize_priv_data(mtk_dp);1942 1943 mtk_dp_initialize_settings(mtk_dp);1944 mtk_dp_initialize_aux_settings(mtk_dp);1945 mtk_dp_initialize_digital_settings(mtk_dp);1946 mtk_dp_initialize_hpd_detect_settings(mtk_dp);1947 1948 mtk_dp_digital_sw_reset(mtk_dp);1949}1950 1951static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)1952{1953 struct mtk_dp *mtk_dp = dev;1954 unsigned long flags;1955 u32 status;1956 1957 if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)1958 msleep(100);1959 1960 spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);1961 status = mtk_dp->irq_thread_handle;1962 mtk_dp->irq_thread_handle = 0;1963 spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);1964 1965 if (status & MTK_DP_THREAD_CABLE_STATE_CHG) {1966 if (mtk_dp->bridge.dev)1967 drm_helper_hpd_irq_event(mtk_dp->bridge.dev);1968 1969 if (!mtk_dp->train_info.cable_plugged_in) {1970 mtk_dp_disable_sdp_aui(mtk_dp);1971 memset(&mtk_dp->info.audio_cur_cfg, 0,1972 sizeof(mtk_dp->info.audio_cur_cfg));1973 1974 mtk_dp->need_debounce = false;1975 mod_timer(&mtk_dp->debounce_timer,1976 jiffies + msecs_to_jiffies(100) - 1);1977 }1978 }1979 1980 if (status & MTK_DP_THREAD_HPD_EVENT)1981 dev_dbg(mtk_dp->dev, "Receive IRQ from sink devices\n");1982 1983 return IRQ_HANDLED;1984}1985 1986static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)1987{1988 struct mtk_dp *mtk_dp = dev;1989 bool cable_sta_chg = false;1990 unsigned long flags;1991 u32 irq_status = mtk_dp_swirq_get_clear(mtk_dp) |1992 mtk_dp_hwirq_get_clear(mtk_dp);1993 1994 if (!irq_status)1995 return IRQ_HANDLED;1996 1997 spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);1998 1999 if (irq_status & MTK_DP_HPD_INTERRUPT)2000 mtk_dp->irq_thread_handle |= MTK_DP_THREAD_HPD_EVENT;2001 2002 /* Cable state is changed. */2003 if (irq_status != MTK_DP_HPD_INTERRUPT) {2004 mtk_dp->irq_thread_handle |= MTK_DP_THREAD_CABLE_STATE_CHG;2005 cable_sta_chg = true;2006 }2007 2008 spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);2009 2010 if (cable_sta_chg) {2011 if (!!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) &2012 HPD_DB_DP_TRANS_P0_MASK))2013 mtk_dp->train_info.cable_plugged_in = true;2014 else2015 mtk_dp->train_info.cable_plugged_in = false;2016 }2017 2018 return IRQ_WAKE_THREAD;2019}2020 2021static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wait_us)2022{2023 struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);2024 u32 val;2025 int ret;2026 2027 ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,2028 val, !!(val & HPD_DB_DP_TRANS_P0_MASK),2029 wait_us / 100, wait_us);2030 if (ret) {2031 mtk_dp->train_info.cable_plugged_in = false;2032 return ret;2033 }2034 2035 mtk_dp->train_info.cable_plugged_in = true;2036 2037 ret = mtk_dp_parse_capabilities(mtk_dp);2038 if (ret) {2039 drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");2040 return ret;2041 }2042 2043 return 0;2044}2045 2046static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,2047 struct platform_device *pdev)2048{2049 struct device_node *endpoint;2050 struct device *dev = &pdev->dev;2051 int ret;2052 void __iomem *base;2053 u32 linkrate;2054 int len;2055 2056 base = devm_platform_ioremap_resource(pdev, 0);2057 if (IS_ERR(base))2058 return PTR_ERR(base);2059 2060 mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_config);2061 if (IS_ERR(mtk_dp->regs))2062 return PTR_ERR(mtk_dp->regs);2063 2064 endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 1, -1);2065 len = of_property_count_elems_of_size(endpoint,2066 "data-lanes", sizeof(u32));2067 if (len < 0 || len > 4 || len == 3) {2068 dev_err(dev, "invalid data lane size: %d\n", len);2069 return -EINVAL;2070 }2071 2072 mtk_dp->max_lanes = len;2073 2074 ret = device_property_read_u32(dev, "max-linkrate-mhz", &linkrate);2075 if (ret) {2076 dev_err(dev, "failed to read max linkrate: %d\n", ret);2077 return ret;2078 }2079 2080 mtk_dp->max_linkrate = drm_dp_link_rate_to_bw_code(linkrate * 100);2081 2082 return 0;2083}2084 2085static void mtk_dp_update_plugged_status(struct mtk_dp *mtk_dp)2086{2087 if (!mtk_dp->data->audio_supported || !mtk_dp->audio_enable)2088 return;2089 2090 mutex_lock(&mtk_dp->update_plugged_status_lock);2091 if (mtk_dp->plugged_cb && mtk_dp->codec_dev)2092 mtk_dp->plugged_cb(mtk_dp->codec_dev,2093 mtk_dp->enabled &2094 mtk_dp->info.audio_cur_cfg.detect_monitor);2095 mutex_unlock(&mtk_dp->update_plugged_status_lock);2096}2097 2098static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge)2099{2100 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2101 enum drm_connector_status ret = connector_status_disconnected;2102 bool enabled = mtk_dp->enabled;2103 u8 sink_count = 0;2104 2105 if (!mtk_dp->train_info.cable_plugged_in)2106 return ret;2107 2108 if (!enabled)2109 mtk_dp_aux_panel_poweron(mtk_dp, true);2110 2111 /*2112 * Some dongles still source HPD when they do not connect to any2113 * sink device. To avoid this, we need to read the sink count2114 * to make sure we do connect to sink devices. After this detect2115 * function, we just need to check the HPD connection to check2116 * whether we connect to a sink device.2117 */2118 drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count);2119 if (DP_GET_SINK_COUNT(sink_count))2120 ret = connector_status_connected;2121 2122 if (!enabled)2123 mtk_dp_aux_panel_poweron(mtk_dp, false);2124 2125 return ret;2126}2127 2128static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,2129 struct drm_connector *connector)2130{2131 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2132 bool enabled = mtk_dp->enabled;2133 const struct drm_edid *drm_edid;2134 struct mtk_dp_audio_cfg *audio_caps = &mtk_dp->info.audio_cur_cfg;2135 2136 if (!enabled) {2137 drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state);2138 mtk_dp_aux_panel_poweron(mtk_dp, true);2139 }2140 2141 drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);2142 2143 /*2144 * Parse capability here to let atomic_get_input_bus_fmts and2145 * mode_valid use the capability to calculate sink bitrates.2146 */2147 if (mtk_dp_parse_capabilities(mtk_dp)) {2148 drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");2149 drm_edid_free(drm_edid);2150 drm_edid = NULL;2151 }2152 2153 if (drm_edid) {2154 /*2155 * FIXME: get rid of drm_edid_raw()2156 */2157 const struct edid *edid = drm_edid_raw(drm_edid);2158 struct cea_sad *sads;2159 int ret;2160 2161 ret = drm_edid_to_sad(edid, &sads);2162 /* Ignore any errors */2163 if (ret < 0)2164 ret = 0;2165 if (ret)2166 kfree(sads);2167 audio_caps->sad_count = ret;2168 2169 /*2170 * FIXME: This should use connector->display_info.has_audio from2171 * a path that has read the EDID and called2172 * drm_edid_connector_update().2173 */2174 audio_caps->detect_monitor = drm_detect_monitor_audio(edid);2175 }2176 2177 if (!enabled) {2178 mtk_dp_aux_panel_poweron(mtk_dp, false);2179 drm_atomic_bridge_chain_post_disable(bridge, connector->state->state);2180 }2181 2182 return drm_edid;2183}2184 2185static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux *mtk_aux,2186 struct drm_dp_aux_msg *msg)2187{2188 struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);2189 bool is_read;2190 u8 request;2191 size_t accessed_bytes = 0;2192 int ret;2193 2194 if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP &&2195 !mtk_dp->train_info.cable_plugged_in) {2196 ret = -EIO;2197 goto err;2198 }2199 2200 switch (msg->request) {2201 case DP_AUX_I2C_MOT:2202 case DP_AUX_I2C_WRITE:2203 case DP_AUX_NATIVE_WRITE:2204 case DP_AUX_I2C_WRITE_STATUS_UPDATE:2205 case DP_AUX_I2C_WRITE_STATUS_UPDATE | DP_AUX_I2C_MOT:2206 request = msg->request & ~DP_AUX_I2C_WRITE_STATUS_UPDATE;2207 is_read = false;2208 break;2209 case DP_AUX_I2C_READ:2210 case DP_AUX_NATIVE_READ:2211 case DP_AUX_I2C_READ | DP_AUX_I2C_MOT:2212 request = msg->request;2213 is_read = true;2214 break;2215 default:2216 dev_err(mtk_dp->dev, "invalid aux cmd = %d\n",2217 msg->request);2218 ret = -EINVAL;2219 goto err;2220 }2221 2222 do {2223 size_t to_access = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES,2224 msg->size - accessed_bytes);2225 2226 ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, request,2227 msg->address + accessed_bytes,2228 msg->buffer + accessed_bytes,2229 to_access, &msg->reply);2230 2231 if (ret) {2232 dev_info(mtk_dp->dev,2233 "Failed to do AUX transfer: %d\n", ret);2234 goto err;2235 }2236 accessed_bytes += to_access;2237 } while (accessed_bytes < msg->size);2238 2239 return msg->size;2240err:2241 msg->reply = DP_AUX_NATIVE_REPLY_NACK | DP_AUX_I2C_REPLY_NACK;2242 return ret;2243}2244 2245static int mtk_dp_poweron(struct mtk_dp *mtk_dp)2246{2247 int ret;2248 2249 ret = phy_init(mtk_dp->phy);2250 if (ret) {2251 dev_err(mtk_dp->dev, "Failed to initialize phy: %d\n", ret);2252 return ret;2253 }2254 2255 mtk_dp_init_port(mtk_dp);2256 mtk_dp_power_enable(mtk_dp);2257 2258 return 0;2259}2260 2261static void mtk_dp_poweroff(struct mtk_dp *mtk_dp)2262{2263 mtk_dp_power_disable(mtk_dp);2264 phy_exit(mtk_dp->phy);2265}2266 2267static int mtk_dp_bridge_attach(struct drm_bridge *bridge,2268 enum drm_bridge_attach_flags flags)2269{2270 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2271 int ret;2272 2273 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {2274 dev_err(mtk_dp->dev, "Driver does not provide a connector!");2275 return -EINVAL;2276 }2277 2278 mtk_dp->aux.drm_dev = bridge->dev;2279 ret = drm_dp_aux_register(&mtk_dp->aux);2280 if (ret) {2281 dev_err(mtk_dp->dev,2282 "failed to register DP AUX channel: %d\n", ret);2283 return ret;2284 }2285 2286 ret = mtk_dp_poweron(mtk_dp);2287 if (ret)2288 goto err_aux_register;2289 2290 if (mtk_dp->next_bridge) {2291 ret = drm_bridge_attach(bridge->encoder, mtk_dp->next_bridge,2292 &mtk_dp->bridge, flags);2293 if (ret) {2294 drm_warn(mtk_dp->drm_dev,2295 "Failed to attach external bridge: %d\n", ret);2296 goto err_bridge_attach;2297 }2298 }2299 2300 mtk_dp->drm_dev = bridge->dev;2301 2302 if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {2303 irq_clear_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);2304 enable_irq(mtk_dp->irq);2305 mtk_dp_hwirq_enable(mtk_dp, true);2306 }2307 2308 return 0;2309 2310err_bridge_attach:2311 mtk_dp_poweroff(mtk_dp);2312err_aux_register:2313 drm_dp_aux_unregister(&mtk_dp->aux);2314 return ret;2315}2316 2317static void mtk_dp_bridge_detach(struct drm_bridge *bridge)2318{2319 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2320 2321 if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {2322 mtk_dp_hwirq_enable(mtk_dp, false);2323 disable_irq(mtk_dp->irq);2324 }2325 mtk_dp->drm_dev = NULL;2326 mtk_dp_poweroff(mtk_dp);2327 drm_dp_aux_unregister(&mtk_dp->aux);2328}2329 2330static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,2331 struct drm_bridge_state *old_state)2332{2333 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2334 int ret;2335 2336 mtk_dp->conn = drm_atomic_get_new_connector_for_encoder(old_state->base.state,2337 bridge->encoder);2338 if (!mtk_dp->conn) {2339 drm_err(mtk_dp->drm_dev,2340 "Can't enable bridge as connector is missing\n");2341 return;2342 }2343 2344 mtk_dp_aux_panel_poweron(mtk_dp, true);2345 2346 /* Training */2347 ret = mtk_dp_training(mtk_dp);2348 if (ret) {2349 drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);2350 goto power_off_aux;2351 }2352 2353 ret = mtk_dp_video_config(mtk_dp);2354 if (ret)2355 goto power_off_aux;2356 2357 mtk_dp_video_enable(mtk_dp, true);2358 2359 mtk_dp->audio_enable =2360 mtk_dp_edid_parse_audio_capabilities(mtk_dp,2361 &mtk_dp->info.audio_cur_cfg);2362 if (mtk_dp->audio_enable) {2363 mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);2364 mtk_dp_audio_mute(mtk_dp, false);2365 } else {2366 memset(&mtk_dp->info.audio_cur_cfg, 0,2367 sizeof(mtk_dp->info.audio_cur_cfg));2368 }2369 2370 mtk_dp->enabled = true;2371 mtk_dp_update_plugged_status(mtk_dp);2372 2373 return;2374power_off_aux:2375 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,2376 DP_PWR_STATE_BANDGAP_TPLL,2377 DP_PWR_STATE_MASK);2378}2379 2380static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge,2381 struct drm_bridge_state *old_state)2382{2383 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2384 2385 mtk_dp->enabled = false;2386 mtk_dp_update_plugged_status(mtk_dp);2387 mtk_dp_video_enable(mtk_dp, false);2388 mtk_dp_audio_mute(mtk_dp, true);2389 2390 if (mtk_dp->train_info.cable_plugged_in) {2391 drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);2392 usleep_range(2000, 3000);2393 }2394 2395 /* power off aux */2396 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,2397 DP_PWR_STATE_BANDGAP_TPLL,2398 DP_PWR_STATE_MASK);2399 2400 /* Ensure the sink is muted */2401 msleep(20);2402}2403 2404static enum drm_mode_status2405mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,2406 const struct drm_display_info *info,2407 const struct drm_display_mode *mode)2408{2409 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2410 u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;2411 u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *2412 drm_dp_max_lane_count(mtk_dp->rx_cap),2413 drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *2414 mtk_dp->max_lanes);2415 2416 if (rate < mode->clock * bpp / 8)2417 return MODE_CLOCK_HIGH;2418 2419 return MODE_OK;2420}2421 2422static u32 *mtk_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,2423 struct drm_bridge_state *bridge_state,2424 struct drm_crtc_state *crtc_state,2425 struct drm_connector_state *conn_state,2426 unsigned int *num_output_fmts)2427{2428 u32 *output_fmts;2429 2430 *num_output_fmts = 0;2431 output_fmts = kmalloc(sizeof(*output_fmts), GFP_KERNEL);2432 if (!output_fmts)2433 return NULL;2434 *num_output_fmts = 1;2435 output_fmts[0] = MEDIA_BUS_FMT_FIXED;2436 return output_fmts;2437}2438 2439static const u32 mt8195_input_fmts[] = {2440 MEDIA_BUS_FMT_RGB888_1X24,2441 MEDIA_BUS_FMT_YUV8_1X24,2442 MEDIA_BUS_FMT_YUYV8_1X16,2443};2444 2445static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,2446 struct drm_bridge_state *bridge_state,2447 struct drm_crtc_state *crtc_state,2448 struct drm_connector_state *conn_state,2449 u32 output_fmt,2450 unsigned int *num_input_fmts)2451{2452 u32 *input_fmts;2453 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2454 struct drm_display_mode *mode = &crtc_state->adjusted_mode;2455 struct drm_display_info *display_info =2456 &conn_state->connector->display_info;2457 u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *2458 drm_dp_max_lane_count(mtk_dp->rx_cap),2459 drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *2460 mtk_dp->max_lanes);2461 2462 *num_input_fmts = 0;2463 2464 /*2465 * If the linkrate is smaller than datarate of RGB888, larger than2466 * datarate of YUV422 and sink device supports YUV422, we output YUV4222467 * format. Use this condition, we can support more resolution.2468 */2469 if ((rate < (mode->clock * 24 / 8)) &&2470 (rate > (mode->clock * 16 / 8)) &&2471 (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {2472 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);2473 if (!input_fmts)2474 return NULL;2475 *num_input_fmts = 1;2476 input_fmts[0] = MEDIA_BUS_FMT_YUYV8_1X16;2477 } else {2478 input_fmts = kcalloc(ARRAY_SIZE(mt8195_input_fmts),2479 sizeof(*input_fmts),2480 GFP_KERNEL);2481 if (!input_fmts)2482 return NULL;2483 2484 *num_input_fmts = ARRAY_SIZE(mt8195_input_fmts);2485 memcpy(input_fmts, mt8195_input_fmts, sizeof(mt8195_input_fmts));2486 }2487 2488 return input_fmts;2489}2490 2491static int mtk_dp_bridge_atomic_check(struct drm_bridge *bridge,2492 struct drm_bridge_state *bridge_state,2493 struct drm_crtc_state *crtc_state,2494 struct drm_connector_state *conn_state)2495{2496 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);2497 struct drm_crtc *crtc = conn_state->crtc;2498 unsigned int input_bus_format;2499 2500 input_bus_format = bridge_state->input_bus_cfg.format;2501 2502 dev_dbg(mtk_dp->dev, "input format 0x%04x, output format 0x%04x\n",2503 bridge_state->input_bus_cfg.format,2504 bridge_state->output_bus_cfg.format);2505 2506 if (input_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)2507 mtk_dp->info.format = DP_PIXELFORMAT_YUV422;2508 else2509 mtk_dp->info.format = DP_PIXELFORMAT_RGB;2510 2511 if (!crtc) {2512 drm_err(mtk_dp->drm_dev,2513 "Can't enable bridge as connector state doesn't have a crtc\n");2514 return -EINVAL;2515 }2516 2517 drm_display_mode_to_videomode(&crtc_state->adjusted_mode, &mtk_dp->info.vm);2518 2519 return 0;2520}2521 2522static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {2523 .atomic_check = mtk_dp_bridge_atomic_check,2524 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,2525 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,2526 .atomic_get_output_bus_fmts = mtk_dp_bridge_atomic_get_output_bus_fmts,2527 .atomic_get_input_bus_fmts = mtk_dp_bridge_atomic_get_input_bus_fmts,2528 .atomic_reset = drm_atomic_helper_bridge_reset,2529 .attach = mtk_dp_bridge_attach,2530 .detach = mtk_dp_bridge_detach,2531 .atomic_enable = mtk_dp_bridge_atomic_enable,2532 .atomic_disable = mtk_dp_bridge_atomic_disable,2533 .mode_valid = mtk_dp_bridge_mode_valid,2534 .edid_read = mtk_dp_edid_read,2535 .detect = mtk_dp_bdg_detect,2536};2537 2538static void mtk_dp_debounce_timer(struct timer_list *t)2539{2540 struct mtk_dp *mtk_dp = from_timer(mtk_dp, t, debounce_timer);2541 2542 mtk_dp->need_debounce = true;2543}2544 2545/*2546 * HDMI audio codec callbacks2547 */2548static int mtk_dp_audio_hw_params(struct device *dev, void *data,2549 struct hdmi_codec_daifmt *daifmt,2550 struct hdmi_codec_params *params)2551{2552 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2553 2554 if (!mtk_dp->enabled) {2555 dev_err(mtk_dp->dev, "%s, DP is not ready!\n", __func__);2556 return -ENODEV;2557 }2558 2559 mtk_dp->info.audio_cur_cfg.channels = params->cea.channels;2560 mtk_dp->info.audio_cur_cfg.sample_rate = params->sample_rate;2561 2562 mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);2563 2564 return 0;2565}2566 2567static int mtk_dp_audio_startup(struct device *dev, void *data)2568{2569 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2570 2571 mtk_dp_audio_mute(mtk_dp, false);2572 2573 return 0;2574}2575 2576static void mtk_dp_audio_shutdown(struct device *dev, void *data)2577{2578 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2579 2580 mtk_dp_audio_mute(mtk_dp, true);2581}2582 2583static int mtk_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,2584 size_t len)2585{2586 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2587 2588 if (mtk_dp->enabled)2589 memcpy(buf, mtk_dp->conn->eld, len);2590 else2591 memset(buf, 0, len);2592 2593 return 0;2594}2595 2596static int mtk_dp_audio_hook_plugged_cb(struct device *dev, void *data,2597 hdmi_codec_plugged_cb fn,2598 struct device *codec_dev)2599{2600 struct mtk_dp *mtk_dp = data;2601 2602 mutex_lock(&mtk_dp->update_plugged_status_lock);2603 mtk_dp->plugged_cb = fn;2604 mtk_dp->codec_dev = codec_dev;2605 mutex_unlock(&mtk_dp->update_plugged_status_lock);2606 2607 mtk_dp_update_plugged_status(mtk_dp);2608 2609 return 0;2610}2611 2612static const struct hdmi_codec_ops mtk_dp_audio_codec_ops = {2613 .hw_params = mtk_dp_audio_hw_params,2614 .audio_startup = mtk_dp_audio_startup,2615 .audio_shutdown = mtk_dp_audio_shutdown,2616 .get_eld = mtk_dp_audio_get_eld,2617 .hook_plugged_cb = mtk_dp_audio_hook_plugged_cb,2618 .no_capture_mute = 1,2619};2620 2621static int mtk_dp_register_audio_driver(struct device *dev)2622{2623 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2624 struct hdmi_codec_pdata codec_data = {2625 .ops = &mtk_dp_audio_codec_ops,2626 .max_i2s_channels = 8,2627 .i2s = 1,2628 .data = mtk_dp,2629 };2630 2631 mtk_dp->audio_pdev = platform_device_register_data(dev,2632 HDMI_CODEC_DRV_NAME,2633 PLATFORM_DEVID_AUTO,2634 &codec_data,2635 sizeof(codec_data));2636 return PTR_ERR_OR_ZERO(mtk_dp->audio_pdev);2637}2638 2639static int mtk_dp_register_phy(struct mtk_dp *mtk_dp)2640{2641 struct device *dev = mtk_dp->dev;2642 2643 mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy",2644 PLATFORM_DEVID_AUTO,2645 &mtk_dp->regs,2646 sizeof(struct regmap *));2647 if (IS_ERR(mtk_dp->phy_dev))2648 return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev),2649 "Failed to create device mediatek-dp-phy\n");2650 2651 mtk_dp_get_calibration_data(mtk_dp);2652 2653 mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");2654 if (IS_ERR(mtk_dp->phy)) {2655 platform_device_unregister(mtk_dp->phy_dev);2656 return dev_err_probe(dev, PTR_ERR(mtk_dp->phy), "Failed to get phy\n");2657 }2658 2659 return 0;2660}2661 2662static int mtk_dp_edp_link_panel(struct drm_dp_aux *mtk_aux)2663{2664 struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);2665 struct device *dev = mtk_aux->dev;2666 int ret;2667 2668 mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);2669 2670 /* Power off the DP and AUX: either detection is done, or no panel present */2671 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,2672 DP_PWR_STATE_BANDGAP_TPLL,2673 DP_PWR_STATE_MASK);2674 mtk_dp_power_disable(mtk_dp);2675 2676 if (IS_ERR(mtk_dp->next_bridge)) {2677 ret = PTR_ERR(mtk_dp->next_bridge);2678 mtk_dp->next_bridge = NULL;2679 return ret;2680 }2681 2682 /* For eDP, we add the bridge only if the panel was found */2683 ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);2684 if (ret)2685 return ret;2686 2687 return 0;2688}2689 2690static int mtk_dp_probe(struct platform_device *pdev)2691{2692 struct mtk_dp *mtk_dp;2693 struct device *dev = &pdev->dev;2694 int ret;2695 2696 mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL);2697 if (!mtk_dp)2698 return -ENOMEM;2699 2700 mtk_dp->dev = dev;2701 mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);2702 2703 ret = mtk_dp_dt_parse(mtk_dp, pdev);2704 if (ret)2705 return dev_err_probe(dev, ret, "Failed to parse dt\n");2706 2707 /*2708 * Request the interrupt and install service routine only if we are2709 * on full DisplayPort.2710 * For eDP, polling the HPD instead is more convenient because we2711 * don't expect any (un)plug events during runtime, hence we can2712 * avoid some locking.2713 */2714 if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP) {2715 mtk_dp->irq = platform_get_irq(pdev, 0);2716 if (mtk_dp->irq < 0)2717 return dev_err_probe(dev, mtk_dp->irq,2718 "failed to request dp irq resource\n");2719 2720 spin_lock_init(&mtk_dp->irq_thread_lock);2721 2722 irq_set_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);2723 ret = devm_request_threaded_irq(dev, mtk_dp->irq, mtk_dp_hpd_event,2724 mtk_dp_hpd_event_thread,2725 IRQ_TYPE_LEVEL_HIGH, dev_name(dev),2726 mtk_dp);2727 if (ret)2728 return dev_err_probe(dev, ret,2729 "failed to request mediatek dptx irq\n");2730 2731 mtk_dp->need_debounce = true;2732 timer_setup(&mtk_dp->debounce_timer, mtk_dp_debounce_timer, 0);2733 }2734 2735 mtk_dp->aux.name = "aux_mtk_dp";2736 mtk_dp->aux.dev = dev;2737 mtk_dp->aux.transfer = mtk_dp_aux_transfer;2738 mtk_dp->aux.wait_hpd_asserted = mtk_dp_wait_hpd_asserted;2739 drm_dp_aux_init(&mtk_dp->aux);2740 2741 platform_set_drvdata(pdev, mtk_dp);2742 2743 if (mtk_dp->data->audio_supported) {2744 mutex_init(&mtk_dp->update_plugged_status_lock);2745 2746 ret = mtk_dp_register_audio_driver(dev);2747 if (ret)2748 return dev_err_probe(dev, ret,2749 "Failed to register audio driver\n");2750 }2751 2752 ret = mtk_dp_register_phy(mtk_dp);2753 if (ret)2754 return ret;2755 2756 mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;2757 mtk_dp->bridge.of_node = dev->of_node;2758 mtk_dp->bridge.type = mtk_dp->data->bridge_type;2759 2760 if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP) {2761 /*2762 * Set the data lanes to idle in case the bootloader didn't2763 * properly close the eDP port to avoid stalls and then2764 * reinitialize, reset and power on the AUX block.2765 */2766 mtk_dp_set_idle_pattern(mtk_dp, true);2767 mtk_dp_initialize_aux_settings(mtk_dp);2768 mtk_dp_power_enable(mtk_dp);2769 2770 /* Disable HW interrupts: we don't need any for eDP */2771 mtk_dp_hwirq_enable(mtk_dp, false);2772 2773 /*2774 * Power on the AUX to allow reading the EDID from aux-bus:2775 * please note that it is necessary to call power off in the2776 * .done_probing() callback (mtk_dp_edp_link_panel), as only2777 * there we can safely assume that we finished reading EDID.2778 */2779 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,2780 DP_PWR_STATE_BANDGAP_TPLL_LANE,2781 DP_PWR_STATE_MASK);2782 2783 ret = devm_of_dp_aux_populate_bus(&mtk_dp->aux, mtk_dp_edp_link_panel);2784 if (ret) {2785 /* -ENODEV this means that the panel is not on the aux-bus */2786 if (ret == -ENODEV) {2787 ret = mtk_dp_edp_link_panel(&mtk_dp->aux);2788 if (ret)2789 return ret;2790 } else {2791 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,2792 DP_PWR_STATE_BANDGAP_TPLL,2793 DP_PWR_STATE_MASK);2794 mtk_dp_power_disable(mtk_dp);2795 return ret;2796 }2797 }2798 } else {2799 mtk_dp->bridge.ops = DRM_BRIDGE_OP_DETECT |2800 DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;2801 ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);2802 if (ret)2803 return dev_err_probe(dev, ret, "Failed to add bridge\n");2804 }2805 2806 pm_runtime_enable(dev);2807 pm_runtime_get_sync(dev);2808 2809 return 0;2810}2811 2812static void mtk_dp_remove(struct platform_device *pdev)2813{2814 struct mtk_dp *mtk_dp = platform_get_drvdata(pdev);2815 2816 pm_runtime_put(&pdev->dev);2817 pm_runtime_disable(&pdev->dev);2818 if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)2819 del_timer_sync(&mtk_dp->debounce_timer);2820 platform_device_unregister(mtk_dp->phy_dev);2821 if (mtk_dp->audio_pdev)2822 platform_device_unregister(mtk_dp->audio_pdev);2823}2824 2825#ifdef CONFIG_PM_SLEEP2826static int mtk_dp_suspend(struct device *dev)2827{2828 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2829 2830 mtk_dp_power_disable(mtk_dp);2831 if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)2832 mtk_dp_hwirq_enable(mtk_dp, false);2833 pm_runtime_put_sync(dev);2834 2835 return 0;2836}2837 2838static int mtk_dp_resume(struct device *dev)2839{2840 struct mtk_dp *mtk_dp = dev_get_drvdata(dev);2841 2842 pm_runtime_get_sync(dev);2843 mtk_dp_init_port(mtk_dp);2844 if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)2845 mtk_dp_hwirq_enable(mtk_dp, true);2846 mtk_dp_power_enable(mtk_dp);2847 2848 return 0;2849}2850#endif2851 2852static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);2853 2854static const struct mtk_dp_data mt8188_dp_data = {2855 .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,2856 .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,2857 .efuse_fmt = mt8188_dp_efuse_fmt,2858 .audio_supported = true,2859 .audio_pkt_in_hblank_area = true,2860 .audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,2861};2862 2863static const struct mtk_dp_data mt8195_edp_data = {2864 .bridge_type = DRM_MODE_CONNECTOR_eDP,2865 .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,2866 .efuse_fmt = mt8195_edp_efuse_fmt,2867 .audio_supported = false,2868 .audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,2869};2870 2871static const struct mtk_dp_data mt8195_dp_data = {2872 .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,2873 .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,2874 .efuse_fmt = mt8195_dp_efuse_fmt,2875 .audio_supported = true,2876 .audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,2877};2878 2879static const struct of_device_id mtk_dp_of_match[] = {2880 {2881 .compatible = "mediatek,mt8188-edp-tx",2882 .data = &mt8195_edp_data,2883 },2884 {2885 .compatible = "mediatek,mt8188-dp-tx",2886 .data = &mt8188_dp_data,2887 },2888 {2889 .compatible = "mediatek,mt8195-edp-tx",2890 .data = &mt8195_edp_data,2891 },2892 {2893 .compatible = "mediatek,mt8195-dp-tx",2894 .data = &mt8195_dp_data,2895 },2896 {},2897};2898MODULE_DEVICE_TABLE(of, mtk_dp_of_match);2899 2900static struct platform_driver mtk_dp_driver = {2901 .probe = mtk_dp_probe,2902 .remove_new = mtk_dp_remove,2903 .driver = {2904 .name = "mediatek-drm-dp",2905 .of_match_table = mtk_dp_of_match,2906 .pm = &mtk_dp_pm_ops,2907 },2908};2909 2910module_platform_driver(mtk_dp_driver);2911 2912MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");2913MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");2914MODULE_AUTHOR("Bo-Chen Chen <rex-bc.chen@mediatek.com>");2915MODULE_DESCRIPTION("MediaTek DisplayPort Driver");2916MODULE_LICENSE("GPL");2917MODULE_SOFTDEP("pre: phy_mtk_dp");2918