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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019-2022 MediaTek Inc.4 * Copyright (c) 2022 BayLibre5 */6#ifndef _MTK_DP_REG_H_7#define _MTK_DP_REG_H_8 9#define SEC_OFFSET 0x400010 11#define MTK_DP_HPD_DISCONNECT BIT(1)12#define MTK_DP_HPD_CONNECT BIT(2)13#define MTK_DP_HPD_INTERRUPT BIT(3)14 15/* offset: 0x0 */16#define DP_PHY_GLB_BIAS_GEN_00 0x017#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)18#define DP_PHY_GLB_DPAUX_TX 0x819#define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)20#define MTK_DP_0034 0x3421#define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)22#define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)23#define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)24#define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)25#define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)26#define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)27#define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)28#define DA_CKM_XTAL_CK_FORCE_EN BIT(8)29#define DA_CKM_BIAS_LPF_EN_FORCE_VAL BIT(7)30#define DA_CKM_BIAS_LPF_EN_FORCE_EN BIT(6)31#define DA_CKM_BIAS_EN_FORCE_VAL BIT(5)32#define DA_CKM_BIAS_EN_FORCE_EN BIT(4)33#define DA_XTP_GLB_AVD10_ON_FORCE_VAL BIT(3)34#define DA_XTP_GLB_AVD10_ON_FORCE BIT(2)35#define DA_XTP_GLB_LDO_EN_FORCE_VAL BIT(1)36#define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)37#define DP_PHY_LANE_TX_0 0x10438#define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)39#define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)40#define DP_PHY_LANE_TX_1 0x20441#define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)42#define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)43#define DP_PHY_LANE_TX_2 0x30444#define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)45#define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)46#define DP_PHY_LANE_TX_3 0x40447#define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)48#define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16)49#define MTK_DP_1040 0x104050#define RG_DPAUX_RX_VALID_DEGLITCH_EN BIT(2)51#define RG_XTP_GLB_CKDET_EN BIT(1)52#define RG_DPAUX_RX_EN BIT(0)53 54/* offset: TOP_OFFSET (0x2000) */55#define MTK_DP_TOP_PWR_STATE 0x200056#define DP_PWR_STATE_MASK GENMASK(1, 0)57#define DP_PWR_STATE_BANDGAP BIT(0)58#define DP_PWR_STATE_BANDGAP_TPLL BIT(1)59#define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)60#define MTK_DP_TOP_SWING_EMP 0x200461#define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)62#define DP_TX0_VOLT_SWING_SHIFT 063#define DP_TX0_PRE_EMPH_MASK GENMASK(3, 2)64#define DP_TX0_PRE_EMPH_SHIFT 265#define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)66#define DP_TX1_VOLT_SWING_SHIFT 867#define DP_TX1_PRE_EMPH_MASK GENMASK(11, 10)68#define DP_TX2_VOLT_SWING_MASK GENMASK(17, 16)69#define DP_TX2_PRE_EMPH_MASK GENMASK(19, 18)70#define DP_TX3_VOLT_SWING_MASK GENMASK(25, 24)71#define DP_TX3_PRE_EMPH_MASK GENMASK(27, 26)72#define MTK_DP_TOP_RESET_AND_PROBE 0x202073#define SW_RST_B_PHYD BIT(4)74#define MTK_DP_TOP_IRQ_MASK 0x202c75#define IRQ_MASK_AUX_TOP_IRQ BIT(2)76#define MTK_DP_TOP_MEM_PD 0x203877#define MEM_ISO_EN BIT(0)78#define FUSE_SEL BIT(2)79 80/* offset: ENC0_OFFSET (0x3000) */81#define MTK_DP_ENC0_P0_3000 0x300082#define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)83#define VIDEO_MUTE_SW_DP_ENC0_P0 BIT(2)84#define VIDEO_MUTE_SEL_DP_ENC0_P0 BIT(3)85#define ENHANCED_FRAME_EN_DP_ENC0_P0 BIT(4)86#define MTK_DP_ENC0_P0_3004 0x300487#define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8)88#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9)89#define MTK_DP_ENC0_P0_3010 0x301090#define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)91#define MTK_DP_ENC0_P0_3014 0x301492#define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)93#define MTK_DP_ENC0_P0_3018 0x301894#define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)95#define MTK_DP_ENC0_P0_301C 0x301c96#define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)97#define MTK_DP_ENC0_P0_3020 0x302098#define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)99#define MTK_DP_ENC0_P0_3024 0x3024100#define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)101#define MTK_DP_ENC0_P0_3028 0x3028102#define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)103#define HSP_SW_DP_ENC0_P0_MASK BIT(15)104#define MTK_DP_ENC0_P0_302C 0x302c105#define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)106#define VSP_SW_DP_ENC0_P0_MASK BIT(15)107#define MTK_DP_ENC0_P0_3030 0x3030108#define HTOTAL_SEL_DP_ENC0_P0 BIT(0)109#define VTOTAL_SEL_DP_ENC0_P0 BIT(1)110#define HSTART_SEL_DP_ENC0_P0 BIT(2)111#define VSTART_SEL_DP_ENC0_P0 BIT(3)112#define HWIDTH_SEL_DP_ENC0_P0 BIT(4)113#define VHEIGHT_SEL_DP_ENC0_P0 BIT(5)114#define HSP_SEL_DP_ENC0_P0 BIT(6)115#define HSW_SEL_DP_ENC0_P0 BIT(7)116#define VSP_SEL_DP_ENC0_P0 BIT(8)117#define VSW_SEL_DP_ENC0_P0 BIT(9)118#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 BIT(11)119#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0 BIT(12)120#define MTK_DP_ENC0_P0_3034 0x3034121#define MTK_DP_ENC0_P0_3038 0x3038122#define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK BIT(11)123#define MTK_DP_ENC0_P0_303C 0x303c124#define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0)125#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8)126#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)127#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << 8)128#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << 8)129#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << 8)130#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << 8)131#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK GENMASK(14, 12)132#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << 12)133#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << 12)134#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 (2 << 12)135#define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)136#define MTK_DP_ENC0_P0_3040 0x3040137#define SDP_DOWN_CNT_DP_ENC0_P0_VAL 0x20138#define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0)139#define MTK_DP_ENC0_P0_304C 0x304c140#define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK BIT(2)141#define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK BIT(8)142#define MTK_DP_ENC0_P0_3064 0x3064143#define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)144#define MTK_DP_ENC0_P0_3088 0x3088145#define AU_EN_DP_ENC0_P0 BIT(6)146#define AUDIO_8CH_EN_DP_ENC0_P0_MASK BIT(7)147#define AUDIO_8CH_SEL_DP_ENC0_P0_MASK BIT(8)148#define AUDIO_2CH_EN_DP_ENC0_P0_MASK BIT(14)149#define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)150#define MTK_DP_ENC0_P0_308C 0x308c151#define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)152#define MTK_DP_ENC0_P0_3090 0x3090153#define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)154#define MTK_DP_ENC0_P0_3094 0x3094155#define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)156#define MTK_DP_ENC0_P0_30A4 0x30a4157#define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)158#define MTK_DP_ENC0_P0_30A8 0x30a8159#define MTK_DP_ENC0_P0_30BC 0x30bc160#define ISRC_CONT_DP_ENC0_P0 BIT(0)161#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)162#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)163#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)164#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)165#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8)166#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8)167#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)168#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)169#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)170#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)171#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8)172#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8)173#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)174#define MTK_DP_ENC0_P0_30D8 0x30d8175#define MTK_DP_ENC0_P0_312C 0x312c176#define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)177#define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)178#define MTK_DP_ENC0_P0_3154 0x3154179#define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)180#define MTK_DP_ENC0_P0_3158 0x3158181#define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0)182#define MTK_DP_ENC0_P0_315C 0x315c183#define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)184#define MTK_DP_ENC0_P0_3160 0x3160185#define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0)186#define MTK_DP_ENC0_P0_3164 0x3164187#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)188#define MTK_DP_ENC0_P0_3168 0x3168189#define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0)190#define MTK_DP_ENC0_P0_316C 0x316c191#define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0)192#define MTK_DP_ENC0_P0_3170 0x3170193#define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)194#define MTK_DP_ENC0_P0_3174 0x3174195#define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0)196#define MTK_DP_ENC0_P0_3178 0x3178197#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)198#define MTK_DP_ENC0_P0_31B0 0x31b0199#define PGEN_PATTERN_SEL_VAL 4200#define PGEN_PATTERN_SEL_MASK GENMASK(6, 4)201#define MTK_DP_ENC0_P0_31EC 0x31ec202#define AUDIO_CH_SRC_SEL_DP_ENC0_P0 BIT(4)203#define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)204 205/* offset: ENC1_OFFSET (0x3200) */206#define MTK_DP_ENC1_P0_3200 0x3200207#define MTK_DP_ENC1_P0_3280 0x3280208#define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)209#define SDP_PACKET_W_DP_ENC1_P0 BIT(5)210#define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5)211#define MTK_DP_ENC1_P0_3300 0x3300212#define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2213#define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)214#define MTK_DP_ENC1_P0_3304 0x3304215#define AU_PRTY_REGEN_DP_ENC1_P0_MASK BIT(8)216#define AU_CH_STS_REGEN_DP_ENC1_P0_MASK BIT(9)217#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK BIT(12)218#define MTK_DP_ENC1_P0_3324 0x3324219#define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8)220#define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX 0221#define MTK_DP_ENC1_P0_3364 0x3364222#define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL 0x20223#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0)224#define FIFO_READ_START_POINT_DP_ENC1_P0_VAL 4225#define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)226#define MTK_DP_ENC1_P0_3368 0x3368227#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0)228#define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 BIT(4)229#define SDP_DP13_EN_DP_ENC1_P0 BIT(8)230#define BS2BS_MODE_DP_ENC1_P0 BIT(12)231#define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12)232#define BS2BS_MODE_DP_ENC1_P0_VAL 1233#define DP_ENC1_P0_3368_VAL (VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | \234 VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \235 SDP_DP13_EN_DP_ENC1_P0 | \236 BS2BS_MODE_DP_ENC1_P0)237 238#define MTK_DP_ENC1_P0_3374 0x3374239#define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12)240#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)241 242#define MTK_DP_ENC1_P0_33F4 0x33f4243#define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)244#define DP_ENC_DUMMY_RW_1 BIT(9)245 246/* offset: TRANS_OFFSET (0x3400) */247#define MTK_DP_TRANS_P0_3400 0x3400248#define PATTERN1_EN_DP_TRANS_P0_MASK BIT(12)249#define PATTERN2_EN_DP_TRANS_P0_MASK BIT(13)250#define PATTERN3_EN_DP_TRANS_P0_MASK BIT(14)251#define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)252#define MTK_DP_TRANS_P0_3404 0x3404253#define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0)254#define MTK_DP_TRANS_P0_340C 0x340c255#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0 BIT(13)256#define MTK_DP_TRANS_P0_3410 0x3410257#define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0)258#define HPD_INT_THD_DP_TRANS_P0_MASK GENMASK(7, 4)259#define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << 4)260#define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << 6)261#define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8)262#define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)263#define MTK_DP_TRANS_P0_3414 0x3414264#define HPD_DB_DP_TRANS_P0_MASK BIT(2)265#define MTK_DP_TRANS_P0_3418 0x3418266#define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0)267#define IRQ_MASK_DP_TRANS_P0_MASK GENMASK(7, 4)268#define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << 4)269#define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << 4)270#define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << 4)271#define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)272#define MTK_DP_TRANS_P0_342C 0x342c273#define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6))274#define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0)275#define MTK_DP_TRANS_P0_3430 0x3430276#define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)277#define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)278#define MTK_DP_TRANS_P0_34A4 0x34a4279#define LANE_NUM_DP_TRANS_P0_MASK GENMASK(3, 2)280#define MTK_DP_TRANS_P0_3540 0x3540281#define FEC_EN_DP_TRANS_P0_MASK BIT(0)282#define FEC_CLOCK_EN_MODE_DP_TRANS_P0 BIT(3)283#define MTK_DP_TRANS_P0_3580 0x3580284#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK BIT(8)285#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK BIT(9)286#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK BIT(10)287#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK BIT(11)288#define MTK_DP_TRANS_P0_35C8 0x35c8289#define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)290#define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)291#define MTK_DP_TRANS_P0_35D0 0x35d0292#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)293#define MTK_DP_TRANS_P0_35F0 0x35f0294#define DP_TRANS_DUMMY_RW_0 BIT(3)295#define DP_TRANS_DUMMY_RW_0_MASK GENMASK(3, 2)296 297/* offset: AUX_OFFSET (0x3600) */298#define MTK_DP_AUX_P0_360C 0x360c299#define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)300#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595301#define MTK_DP_AUX_P0_3614 0x3614302#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)303#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13304#define MTK_DP_AUX_P0_3618 0x3618305#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)306#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)307#define MTK_DP_AUX_P0_3620 0x3620308#define AUX_RD_MODE_AUX_TX_P0_MASK BIT(9)309#define AUX_RX_FIFO_READ_PULSE_TX_P0 BIT(8)310#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0)311#define MTK_DP_AUX_P0_3624 0x3624312#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)313#define MTK_DP_AUX_P0_3628 0x3628314#define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0)315#define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0)316#define MTK_DP_AUX_P0_362C 0x362c317#define AUX_NO_LENGTH_AUX_TX_P0 BIT(0)318#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK BIT(1)319#define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)320#define MTK_DP_AUX_P0_3630 0x3630321#define AUX_TX_REQUEST_READY_AUX_TX_P0 BIT(3)322#define MTK_DP_AUX_P0_3634 0x3634323#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)324#define AUX_TX_OVER_SAMPLE_RATE_FOR_26M 25325#define MTK_DP_AUX_P0_3640 0x3640326#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(6)327#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(5)328#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(4)329#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 BIT(3)330#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 BIT(2)331#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 BIT(1)332#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 BIT(0)333#define DP_AUX_P0_3640_VAL (AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 | \334 AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 | \335 AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 | \336 AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 | \337 AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 | \338 AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 | \339 AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0)340#define MTK_DP_AUX_P0_3644 0x3644341#define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)342#define MTK_DP_AUX_P0_3648 0x3648343#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)344#define MTK_DP_AUX_P0_364C 0x364c345#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)346#define MTK_DP_AUX_P0_3650 0x3650347#define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)348#define PHY_FIFO_RST_AUX_TX_P0_MASK BIT(9)349#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8)350#define MTK_DP_AUX_P0_3658 0x3658351#define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)352#define MTK_DP_AUX_P0_3690 0x3690353#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8)354#define MTK_DP_AUX_P0_3704 0x3704355#define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1)356#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0 BIT(2)357#define MTK_DP_AUX_P0_3708 0x3708358#define MTK_DP_AUX_P0_37C8 0x37c8359#define MTK_ATOP_EN_AUX_TX_P0 BIT(0)360 361#endif /*_MTK_DP_REG_H_*/362