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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2015 MediaTek Inc.4 * Author: YT SHEN <yt.shen@mediatek.com>5 */6 7#include <linux/component.h>8#include <linux/module.h>9#include <linux/of.h>10#include <linux/of_platform.h>11#include <linux/platform_device.h>12#include <linux/pm_runtime.h>13#include <linux/dma-mapping.h>14 15#include <drm/drm_atomic.h>16#include <drm/drm_atomic_helper.h>17#include <drm/drm_drv.h>18#include <drm/drm_fbdev_dma.h>19#include <drm/drm_fourcc.h>20#include <drm/drm_gem.h>21#include <drm/drm_gem_framebuffer_helper.h>22#include <drm/drm_ioctl.h>23#include <drm/drm_of.h>24#include <drm/drm_probe_helper.h>25#include <drm/drm_vblank.h>26 27#include "mtk_crtc.h"28#include "mtk_ddp_comp.h"29#include "mtk_drm_drv.h"30#include "mtk_gem.h"31 32#define DRIVER_NAME "mediatek"33#define DRIVER_DESC "Mediatek SoC DRM"34#define DRIVER_DATE "20150513"35#define DRIVER_MAJOR 136#define DRIVER_MINOR 037 38static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,40};41 42static struct drm_framebuffer *43mtk_drm_mode_fb_create(struct drm_device *dev,44 struct drm_file *file,45 const struct drm_mode_fb_cmd2 *cmd)46{47 const struct drm_format_info *info = drm_get_format_info(dev, cmd);48 49 if (info->num_planes != 1)50 return ERR_PTR(-EINVAL);51 52 return drm_gem_fb_create(dev, file, cmd);53}54 55static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {56 .fb_create = mtk_drm_mode_fb_create,57 .atomic_check = drm_atomic_helper_check,58 .atomic_commit = drm_atomic_helper_commit,59};60 61static const unsigned int mt2701_mtk_ddp_main[] = {62 DDP_COMPONENT_OVL0,63 DDP_COMPONENT_RDMA0,64 DDP_COMPONENT_COLOR0,65 DDP_COMPONENT_BLS,66 DDP_COMPONENT_DSI0,67};68 69static const unsigned int mt2701_mtk_ddp_ext[] = {70 DDP_COMPONENT_RDMA1,71 DDP_COMPONENT_DPI0,72};73 74static const unsigned int mt7623_mtk_ddp_main[] = {75 DDP_COMPONENT_OVL0,76 DDP_COMPONENT_RDMA0,77 DDP_COMPONENT_COLOR0,78 DDP_COMPONENT_BLS,79 DDP_COMPONENT_DPI0,80};81 82static const unsigned int mt7623_mtk_ddp_ext[] = {83 DDP_COMPONENT_RDMA1,84 DDP_COMPONENT_DSI0,85};86 87static const unsigned int mt2712_mtk_ddp_main[] = {88 DDP_COMPONENT_OVL0,89 DDP_COMPONENT_COLOR0,90 DDP_COMPONENT_AAL0,91 DDP_COMPONENT_OD0,92 DDP_COMPONENT_RDMA0,93 DDP_COMPONENT_DPI0,94 DDP_COMPONENT_PWM0,95};96 97static const unsigned int mt2712_mtk_ddp_ext[] = {98 DDP_COMPONENT_OVL1,99 DDP_COMPONENT_COLOR1,100 DDP_COMPONENT_AAL1,101 DDP_COMPONENT_OD1,102 DDP_COMPONENT_RDMA1,103 DDP_COMPONENT_DPI1,104 DDP_COMPONENT_PWM1,105};106 107static const unsigned int mt2712_mtk_ddp_third[] = {108 DDP_COMPONENT_RDMA2,109 DDP_COMPONENT_DSI3,110 DDP_COMPONENT_PWM2,111};112 113static unsigned int mt8167_mtk_ddp_main[] = {114 DDP_COMPONENT_OVL0,115 DDP_COMPONENT_COLOR0,116 DDP_COMPONENT_CCORR,117 DDP_COMPONENT_AAL0,118 DDP_COMPONENT_GAMMA,119 DDP_COMPONENT_DITHER0,120 DDP_COMPONENT_RDMA0,121 DDP_COMPONENT_DSI0,122};123 124static const unsigned int mt8173_mtk_ddp_main[] = {125 DDP_COMPONENT_OVL0,126 DDP_COMPONENT_COLOR0,127 DDP_COMPONENT_AAL0,128 DDP_COMPONENT_OD0,129 DDP_COMPONENT_RDMA0,130 DDP_COMPONENT_UFOE,131 DDP_COMPONENT_DSI0,132 DDP_COMPONENT_PWM0,133};134 135static const unsigned int mt8173_mtk_ddp_ext[] = {136 DDP_COMPONENT_OVL1,137 DDP_COMPONENT_COLOR1,138 DDP_COMPONENT_GAMMA,139 DDP_COMPONENT_RDMA1,140 DDP_COMPONENT_DPI0,141};142 143static const unsigned int mt8183_mtk_ddp_main[] = {144 DDP_COMPONENT_OVL0,145 DDP_COMPONENT_OVL_2L0,146 DDP_COMPONENT_RDMA0,147 DDP_COMPONENT_COLOR0,148 DDP_COMPONENT_CCORR,149 DDP_COMPONENT_AAL0,150 DDP_COMPONENT_GAMMA,151 DDP_COMPONENT_DITHER0,152 DDP_COMPONENT_DSI0,153};154 155static const unsigned int mt8183_mtk_ddp_ext[] = {156 DDP_COMPONENT_OVL_2L1,157 DDP_COMPONENT_RDMA1,158 DDP_COMPONENT_DPI0,159};160 161static const unsigned int mt8186_mtk_ddp_main[] = {162 DDP_COMPONENT_OVL0,163 DDP_COMPONENT_RDMA0,164 DDP_COMPONENT_COLOR0,165 DDP_COMPONENT_CCORR,166 DDP_COMPONENT_AAL0,167 DDP_COMPONENT_GAMMA,168 DDP_COMPONENT_POSTMASK0,169 DDP_COMPONENT_DITHER0,170 DDP_COMPONENT_DSI0,171};172 173static const unsigned int mt8186_mtk_ddp_ext[] = {174 DDP_COMPONENT_OVL_2L0,175 DDP_COMPONENT_RDMA1,176 DDP_COMPONENT_DPI0,177};178 179static const unsigned int mt8188_mtk_ddp_main[] = {180 DDP_COMPONENT_OVL0,181 DDP_COMPONENT_RDMA0,182 DDP_COMPONENT_COLOR0,183 DDP_COMPONENT_CCORR,184 DDP_COMPONENT_AAL0,185 DDP_COMPONENT_GAMMA,186 DDP_COMPONENT_POSTMASK0,187 DDP_COMPONENT_DITHER0,188};189 190static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {191 {0, DDP_COMPONENT_DP_INTF0},192 {0, DDP_COMPONENT_DSI0},193};194 195static const unsigned int mt8192_mtk_ddp_main[] = {196 DDP_COMPONENT_OVL0,197 DDP_COMPONENT_OVL_2L0,198 DDP_COMPONENT_RDMA0,199 DDP_COMPONENT_COLOR0,200 DDP_COMPONENT_CCORR,201 DDP_COMPONENT_AAL0,202 DDP_COMPONENT_GAMMA,203 DDP_COMPONENT_POSTMASK0,204 DDP_COMPONENT_DITHER0,205 DDP_COMPONENT_DSI0,206};207 208static const unsigned int mt8192_mtk_ddp_ext[] = {209 DDP_COMPONENT_OVL_2L2,210 DDP_COMPONENT_RDMA4,211 DDP_COMPONENT_DPI0,212};213 214static const unsigned int mt8195_mtk_ddp_main[] = {215 DDP_COMPONENT_OVL0,216 DDP_COMPONENT_RDMA0,217 DDP_COMPONENT_COLOR0,218 DDP_COMPONENT_CCORR,219 DDP_COMPONENT_AAL0,220 DDP_COMPONENT_GAMMA,221 DDP_COMPONENT_DITHER0,222 DDP_COMPONENT_DSC0,223 DDP_COMPONENT_MERGE0,224 DDP_COMPONENT_DP_INTF0,225};226 227static const unsigned int mt8195_mtk_ddp_ext[] = {228 DDP_COMPONENT_DRM_OVL_ADAPTOR,229 DDP_COMPONENT_MERGE5,230 DDP_COMPONENT_DP_INTF1,231};232 233static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {234 .main_path = mt2701_mtk_ddp_main,235 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),236 .ext_path = mt2701_mtk_ddp_ext,237 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),238 .shadow_register = true,239 .mmsys_dev_num = 1,240};241 242static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {243 .main_path = mt7623_mtk_ddp_main,244 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),245 .ext_path = mt7623_mtk_ddp_ext,246 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),247 .shadow_register = true,248 .mmsys_dev_num = 1,249};250 251static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {252 .main_path = mt2712_mtk_ddp_main,253 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),254 .ext_path = mt2712_mtk_ddp_ext,255 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),256 .third_path = mt2712_mtk_ddp_third,257 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),258 .mmsys_dev_num = 1,259};260 261static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {262 .main_path = mt8167_mtk_ddp_main,263 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),264 .mmsys_dev_num = 1,265};266 267static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {268 .main_path = mt8173_mtk_ddp_main,269 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),270 .ext_path = mt8173_mtk_ddp_ext,271 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),272 .mmsys_dev_num = 1,273};274 275static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {276 .main_path = mt8183_mtk_ddp_main,277 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),278 .ext_path = mt8183_mtk_ddp_ext,279 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),280 .mmsys_dev_num = 1,281};282 283static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {284 .main_path = mt8186_mtk_ddp_main,285 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),286 .ext_path = mt8186_mtk_ddp_ext,287 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),288 .mmsys_dev_num = 1,289};290 291static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {292 .main_path = mt8188_mtk_ddp_main,293 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),294 .conn_routes = mt8188_mtk_ddp_main_routes,295 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),296 .mmsys_dev_num = 2,297 .max_width = 8191,298 .min_width = 1,299 .min_height = 1,300};301 302static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {303 .main_path = mt8192_mtk_ddp_main,304 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),305 .ext_path = mt8192_mtk_ddp_ext,306 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),307 .mmsys_dev_num = 1,308};309 310static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {311 .main_path = mt8195_mtk_ddp_main,312 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),313 .mmsys_dev_num = 2,314 .max_width = 8191,315 .min_width = 1,316 .min_height = 1,317};318 319static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {320 .ext_path = mt8195_mtk_ddp_ext,321 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),322 .mmsys_id = 1,323 .mmsys_dev_num = 2,324 .max_width = 8191,325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */326 .min_height = 1,327};328 329static const struct of_device_id mtk_drm_of_ids[] = {330 { .compatible = "mediatek,mt2701-mmsys",331 .data = &mt2701_mmsys_driver_data},332 { .compatible = "mediatek,mt7623-mmsys",333 .data = &mt7623_mmsys_driver_data},334 { .compatible = "mediatek,mt2712-mmsys",335 .data = &mt2712_mmsys_driver_data},336 { .compatible = "mediatek,mt8167-mmsys",337 .data = &mt8167_mmsys_driver_data},338 { .compatible = "mediatek,mt8173-mmsys",339 .data = &mt8173_mmsys_driver_data},340 { .compatible = "mediatek,mt8183-mmsys",341 .data = &mt8183_mmsys_driver_data},342 { .compatible = "mediatek,mt8186-mmsys",343 .data = &mt8186_mmsys_driver_data},344 { .compatible = "mediatek,mt8188-vdosys0",345 .data = &mt8188_vdosys0_driver_data},346 { .compatible = "mediatek,mt8188-vdosys1",347 .data = &mt8195_vdosys1_driver_data},348 { .compatible = "mediatek,mt8192-mmsys",349 .data = &mt8192_mmsys_driver_data},350 { .compatible = "mediatek,mt8195-mmsys",351 .data = &mt8195_vdosys0_driver_data},352 { .compatible = "mediatek,mt8195-vdosys0",353 .data = &mt8195_vdosys0_driver_data},354 { .compatible = "mediatek,mt8195-vdosys1",355 .data = &mt8195_vdosys1_driver_data},356 { }357};358MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);359 360static int mtk_drm_match(struct device *dev, void *data)361{362 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))363 return true;364 return false;365}366 367static bool mtk_drm_get_all_drm_priv(struct device *dev)368{369 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);370 struct mtk_drm_private *all_drm_priv[MAX_CRTC];371 struct mtk_drm_private *temp_drm_priv;372 struct device_node *phandle = dev->parent->of_node;373 const struct of_device_id *of_id;374 struct device_node *node;375 struct device *drm_dev;376 unsigned int cnt = 0;377 int i, j;378 379 for_each_child_of_node(phandle->parent, node) {380 struct platform_device *pdev;381 382 of_id = of_match_node(mtk_drm_of_ids, node);383 if (!of_id)384 continue;385 386 pdev = of_find_device_by_node(node);387 if (!pdev)388 continue;389 390 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);391 if (!drm_dev)392 continue;393 394 temp_drm_priv = dev_get_drvdata(drm_dev);395 if (!temp_drm_priv)396 continue;397 398 if (temp_drm_priv->data->main_len)399 all_drm_priv[CRTC_MAIN] = temp_drm_priv;400 else if (temp_drm_priv->data->ext_len)401 all_drm_priv[CRTC_EXT] = temp_drm_priv;402 else if (temp_drm_priv->data->third_len)403 all_drm_priv[CRTC_THIRD] = temp_drm_priv;404 405 if (temp_drm_priv->mtk_drm_bound)406 cnt++;407 408 if (cnt == MAX_CRTC)409 break;410 }411 412 if (drm_priv->data->mmsys_dev_num == cnt) {413 for (i = 0; i < cnt; i++)414 for (j = 0; j < cnt; j++)415 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];416 417 return true;418 }419 420 return false;421}422 423static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)424{425 const struct mtk_mmsys_driver_data *drv_data = private->data;426 int i;427 428 if (drv_data->main_path)429 for (i = 0; i < drv_data->main_len; i++)430 if (drv_data->main_path[i] == comp_id)431 return true;432 433 if (drv_data->ext_path)434 for (i = 0; i < drv_data->ext_len; i++)435 if (drv_data->ext_path[i] == comp_id)436 return true;437 438 if (drv_data->third_path)439 for (i = 0; i < drv_data->third_len; i++)440 if (drv_data->third_path[i] == comp_id)441 return true;442 443 if (drv_data->num_conn_routes)444 for (i = 0; i < drv_data->num_conn_routes; i++)445 if (drv_data->conn_routes[i].route_ddp == comp_id)446 return true;447 448 return false;449}450 451static int mtk_drm_kms_init(struct drm_device *drm)452{453 struct mtk_drm_private *private = drm->dev_private;454 struct mtk_drm_private *priv_n;455 struct device *dma_dev = NULL;456 struct drm_crtc *crtc;457 int ret, i, j;458 459 if (drm_firmware_drivers_only())460 return -ENODEV;461 462 ret = drmm_mode_config_init(drm);463 if (ret)464 goto put_mutex_dev;465 466 drm->mode_config.min_width = 64;467 drm->mode_config.min_height = 64;468 469 /*470 * set max width and height as default value(4096x4096).471 * this value would be used to check framebuffer size limitation472 * at drm_mode_addfb().473 */474 drm->mode_config.max_width = 4096;475 drm->mode_config.max_height = 4096;476 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;477 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;478 479 for (i = 0; i < private->data->mmsys_dev_num; i++) {480 drm->dev_private = private->all_drm_private[i];481 ret = component_bind_all(private->all_drm_private[i]->dev, drm);482 if (ret)483 goto put_mutex_dev;484 }485 486 /*487 * Ensure internal panels are at the top of the connector list before488 * crtc creation.489 */490 drm_helper_move_panel_connectors_to_head(drm);491 492 /*493 * 1. We currently support two fixed data streams, each optional,494 * and each statically assigned to a crtc:495 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...496 * 2. For multi mmsys architecture, crtc path data are located in497 * different drm private data structures. Loop through crtc index to498 * create crtc from the main path and then ext_path and finally the499 * third path.500 */501 for (i = 0; i < MAX_CRTC; i++) {502 for (j = 0; j < private->data->mmsys_dev_num; j++) {503 priv_n = private->all_drm_private[j];504 505 if (priv_n->data->max_width)506 drm->mode_config.max_width = priv_n->data->max_width;507 508 if (priv_n->data->min_width)509 drm->mode_config.min_width = priv_n->data->min_width;510 511 if (priv_n->data->min_height)512 drm->mode_config.min_height = priv_n->data->min_height;513 514 if (i == CRTC_MAIN && priv_n->data->main_len) {515 ret = mtk_crtc_create(drm, priv_n->data->main_path,516 priv_n->data->main_len, j,517 priv_n->data->conn_routes,518 priv_n->data->num_conn_routes);519 if (ret)520 goto err_component_unbind;521 522 continue;523 } else if (i == CRTC_EXT && priv_n->data->ext_len) {524 ret = mtk_crtc_create(drm, priv_n->data->ext_path,525 priv_n->data->ext_len, j, NULL, 0);526 if (ret)527 goto err_component_unbind;528 529 continue;530 } else if (i == CRTC_THIRD && priv_n->data->third_len) {531 ret = mtk_crtc_create(drm, priv_n->data->third_path,532 priv_n->data->third_len, j, NULL, 0);533 if (ret)534 goto err_component_unbind;535 536 continue;537 }538 }539 }540 541 /* IGT will check if the cursor size is configured */542 drm->mode_config.cursor_width = 512;543 drm->mode_config.cursor_height = 512;544 545 /* Use OVL device for all DMA memory allocations */546 crtc = drm_crtc_from_index(drm, 0);547 if (crtc)548 dma_dev = mtk_crtc_dma_dev_get(crtc);549 if (!dma_dev) {550 ret = -ENODEV;551 dev_err(drm->dev, "Need at least one OVL device\n");552 goto err_component_unbind;553 }554 555 for (i = 0; i < private->data->mmsys_dev_num; i++)556 private->all_drm_private[i]->dma_dev = dma_dev;557 558 /*559 * Configure the DMA segment size to make sure we get contiguous IOVA560 * when importing PRIME buffers.561 */562 dma_set_max_seg_size(dma_dev, UINT_MAX);563 564 ret = drm_vblank_init(drm, MAX_CRTC);565 if (ret < 0)566 goto err_component_unbind;567 568 drm_kms_helper_poll_init(drm);569 drm_mode_config_reset(drm);570 571 return 0;572 573err_component_unbind:574 for (i = 0; i < private->data->mmsys_dev_num; i++)575 component_unbind_all(private->all_drm_private[i]->dev, drm);576put_mutex_dev:577 for (i = 0; i < private->data->mmsys_dev_num; i++)578 put_device(private->all_drm_private[i]->mutex_dev);579 580 return ret;581}582 583static void mtk_drm_kms_deinit(struct drm_device *drm)584{585 drm_kms_helper_poll_fini(drm);586 drm_atomic_helper_shutdown(drm);587 588 component_unbind_all(drm->dev, drm);589}590 591DEFINE_DRM_GEM_FOPS(mtk_drm_fops);592 593/*594 * We need to override this because the device used to import the memory is595 * not dev->dev, as drm_gem_prime_import() expects.596 */597static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,598 struct dma_buf *dma_buf)599{600 struct mtk_drm_private *private = dev->dev_private;601 602 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);603}604 605static const struct drm_driver mtk_drm_driver = {606 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,607 608 .dumb_create = mtk_gem_dumb_create,609 610 .gem_prime_import = mtk_gem_prime_import,611 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,612 .fops = &mtk_drm_fops,613 614 .name = DRIVER_NAME,615 .desc = DRIVER_DESC,616 .date = DRIVER_DATE,617 .major = DRIVER_MAJOR,618 .minor = DRIVER_MINOR,619};620 621static int compare_dev(struct device *dev, void *data)622{623 return dev == (struct device *)data;624}625 626static int mtk_drm_bind(struct device *dev)627{628 struct mtk_drm_private *private = dev_get_drvdata(dev);629 struct platform_device *pdev;630 struct drm_device *drm;631 int ret, i;632 633 pdev = of_find_device_by_node(private->mutex_node);634 if (!pdev) {635 dev_err(dev, "Waiting for disp-mutex device %pOF\n",636 private->mutex_node);637 of_node_put(private->mutex_node);638 return -EPROBE_DEFER;639 }640 641 private->mutex_dev = &pdev->dev;642 private->mtk_drm_bound = true;643 private->dev = dev;644 645 if (!mtk_drm_get_all_drm_priv(dev))646 return 0;647 648 drm = drm_dev_alloc(&mtk_drm_driver, dev);649 if (IS_ERR(drm))650 return PTR_ERR(drm);651 652 private->drm_master = true;653 drm->dev_private = private;654 for (i = 0; i < private->data->mmsys_dev_num; i++)655 private->all_drm_private[i]->drm = drm;656 657 ret = mtk_drm_kms_init(drm);658 if (ret < 0)659 goto err_free;660 661 ret = drm_dev_register(drm, 0);662 if (ret < 0)663 goto err_deinit;664 665 drm_fbdev_dma_setup(drm, 32);666 667 return 0;668 669err_deinit:670 mtk_drm_kms_deinit(drm);671err_free:672 private->drm = NULL;673 drm_dev_put(drm);674 return ret;675}676 677static void mtk_drm_unbind(struct device *dev)678{679 struct mtk_drm_private *private = dev_get_drvdata(dev);680 681 /* for multi mmsys dev, unregister drm dev in mmsys master */682 if (private->drm_master) {683 drm_dev_unregister(private->drm);684 mtk_drm_kms_deinit(private->drm);685 drm_dev_put(private->drm);686 }687 private->mtk_drm_bound = false;688 private->drm_master = false;689 private->drm = NULL;690}691 692static const struct component_master_ops mtk_drm_ops = {693 .bind = mtk_drm_bind,694 .unbind = mtk_drm_unbind,695};696 697static const struct of_device_id mtk_ddp_comp_dt_ids[] = {698 { .compatible = "mediatek,mt8167-disp-aal",699 .data = (void *)MTK_DISP_AAL},700 { .compatible = "mediatek,mt8173-disp-aal",701 .data = (void *)MTK_DISP_AAL},702 { .compatible = "mediatek,mt8183-disp-aal",703 .data = (void *)MTK_DISP_AAL},704 { .compatible = "mediatek,mt8192-disp-aal",705 .data = (void *)MTK_DISP_AAL},706 { .compatible = "mediatek,mt8167-disp-ccorr",707 .data = (void *)MTK_DISP_CCORR },708 { .compatible = "mediatek,mt8183-disp-ccorr",709 .data = (void *)MTK_DISP_CCORR },710 { .compatible = "mediatek,mt8192-disp-ccorr",711 .data = (void *)MTK_DISP_CCORR },712 { .compatible = "mediatek,mt2701-disp-color",713 .data = (void *)MTK_DISP_COLOR },714 { .compatible = "mediatek,mt8167-disp-color",715 .data = (void *)MTK_DISP_COLOR },716 { .compatible = "mediatek,mt8173-disp-color",717 .data = (void *)MTK_DISP_COLOR },718 { .compatible = "mediatek,mt8167-disp-dither",719 .data = (void *)MTK_DISP_DITHER },720 { .compatible = "mediatek,mt8183-disp-dither",721 .data = (void *)MTK_DISP_DITHER },722 { .compatible = "mediatek,mt8195-disp-dsc",723 .data = (void *)MTK_DISP_DSC },724 { .compatible = "mediatek,mt8167-disp-gamma",725 .data = (void *)MTK_DISP_GAMMA, },726 { .compatible = "mediatek,mt8173-disp-gamma",727 .data = (void *)MTK_DISP_GAMMA, },728 { .compatible = "mediatek,mt8183-disp-gamma",729 .data = (void *)MTK_DISP_GAMMA, },730 { .compatible = "mediatek,mt8195-disp-gamma",731 .data = (void *)MTK_DISP_GAMMA, },732 { .compatible = "mediatek,mt8195-disp-merge",733 .data = (void *)MTK_DISP_MERGE },734 { .compatible = "mediatek,mt2701-disp-mutex",735 .data = (void *)MTK_DISP_MUTEX },736 { .compatible = "mediatek,mt2712-disp-mutex",737 .data = (void *)MTK_DISP_MUTEX },738 { .compatible = "mediatek,mt8167-disp-mutex",739 .data = (void *)MTK_DISP_MUTEX },740 { .compatible = "mediatek,mt8173-disp-mutex",741 .data = (void *)MTK_DISP_MUTEX },742 { .compatible = "mediatek,mt8183-disp-mutex",743 .data = (void *)MTK_DISP_MUTEX },744 { .compatible = "mediatek,mt8186-disp-mutex",745 .data = (void *)MTK_DISP_MUTEX },746 { .compatible = "mediatek,mt8188-disp-mutex",747 .data = (void *)MTK_DISP_MUTEX },748 { .compatible = "mediatek,mt8192-disp-mutex",749 .data = (void *)MTK_DISP_MUTEX },750 { .compatible = "mediatek,mt8195-disp-mutex",751 .data = (void *)MTK_DISP_MUTEX },752 { .compatible = "mediatek,mt8173-disp-od",753 .data = (void *)MTK_DISP_OD },754 { .compatible = "mediatek,mt2701-disp-ovl",755 .data = (void *)MTK_DISP_OVL },756 { .compatible = "mediatek,mt8167-disp-ovl",757 .data = (void *)MTK_DISP_OVL },758 { .compatible = "mediatek,mt8173-disp-ovl",759 .data = (void *)MTK_DISP_OVL },760 { .compatible = "mediatek,mt8183-disp-ovl",761 .data = (void *)MTK_DISP_OVL },762 { .compatible = "mediatek,mt8192-disp-ovl",763 .data = (void *)MTK_DISP_OVL },764 { .compatible = "mediatek,mt8195-disp-ovl",765 .data = (void *)MTK_DISP_OVL },766 { .compatible = "mediatek,mt8183-disp-ovl-2l",767 .data = (void *)MTK_DISP_OVL_2L },768 { .compatible = "mediatek,mt8192-disp-ovl-2l",769 .data = (void *)MTK_DISP_OVL_2L },770 { .compatible = "mediatek,mt8192-disp-postmask",771 .data = (void *)MTK_DISP_POSTMASK },772 { .compatible = "mediatek,mt2701-disp-pwm",773 .data = (void *)MTK_DISP_BLS },774 { .compatible = "mediatek,mt8167-disp-pwm",775 .data = (void *)MTK_DISP_PWM },776 { .compatible = "mediatek,mt8173-disp-pwm",777 .data = (void *)MTK_DISP_PWM },778 { .compatible = "mediatek,mt2701-disp-rdma",779 .data = (void *)MTK_DISP_RDMA },780 { .compatible = "mediatek,mt8167-disp-rdma",781 .data = (void *)MTK_DISP_RDMA },782 { .compatible = "mediatek,mt8173-disp-rdma",783 .data = (void *)MTK_DISP_RDMA },784 { .compatible = "mediatek,mt8183-disp-rdma",785 .data = (void *)MTK_DISP_RDMA },786 { .compatible = "mediatek,mt8195-disp-rdma",787 .data = (void *)MTK_DISP_RDMA },788 { .compatible = "mediatek,mt8173-disp-ufoe",789 .data = (void *)MTK_DISP_UFOE },790 { .compatible = "mediatek,mt8173-disp-wdma",791 .data = (void *)MTK_DISP_WDMA },792 { .compatible = "mediatek,mt2701-dpi",793 .data = (void *)MTK_DPI },794 { .compatible = "mediatek,mt8167-dsi",795 .data = (void *)MTK_DSI },796 { .compatible = "mediatek,mt8173-dpi",797 .data = (void *)MTK_DPI },798 { .compatible = "mediatek,mt8183-dpi",799 .data = (void *)MTK_DPI },800 { .compatible = "mediatek,mt8186-dpi",801 .data = (void *)MTK_DPI },802 { .compatible = "mediatek,mt8188-dp-intf",803 .data = (void *)MTK_DP_INTF },804 { .compatible = "mediatek,mt8192-dpi",805 .data = (void *)MTK_DPI },806 { .compatible = "mediatek,mt8195-dp-intf",807 .data = (void *)MTK_DP_INTF },808 { .compatible = "mediatek,mt2701-dsi",809 .data = (void *)MTK_DSI },810 { .compatible = "mediatek,mt8173-dsi",811 .data = (void *)MTK_DSI },812 { .compatible = "mediatek,mt8183-dsi",813 .data = (void *)MTK_DSI },814 { .compatible = "mediatek,mt8186-dsi",815 .data = (void *)MTK_DSI },816 { .compatible = "mediatek,mt8188-dsi",817 .data = (void *)MTK_DSI },818 { }819};820 821static int mtk_drm_probe(struct platform_device *pdev)822{823 struct device *dev = &pdev->dev;824 struct device_node *phandle = dev->parent->of_node;825 const struct of_device_id *of_id;826 struct mtk_drm_private *private;827 struct device_node *node;828 struct component_match *match = NULL;829 struct platform_device *ovl_adaptor;830 int ret;831 int i;832 833 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);834 if (!private)835 return -ENOMEM;836 837 private->mmsys_dev = dev->parent;838 if (!private->mmsys_dev) {839 dev_err(dev, "Failed to get MMSYS device\n");840 return -ENODEV;841 }842 843 of_id = of_match_node(mtk_drm_of_ids, phandle);844 if (!of_id)845 return -ENODEV;846 847 private->data = of_id->data;848 849 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,850 sizeof(*private->all_drm_private),851 GFP_KERNEL);852 if (!private->all_drm_private)853 return -ENOMEM;854 855 /* Bringup ovl_adaptor */856 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {857 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",858 PLATFORM_DEVID_AUTO,859 (void *)private->mmsys_dev,860 sizeof(*private->mmsys_dev));861 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;862 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],863 DDP_COMPONENT_DRM_OVL_ADAPTOR);864 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);865 }866 867 /* Iterate over sibling DISP function blocks */868 for_each_child_of_node(phandle->parent, node) {869 const struct of_device_id *of_id;870 enum mtk_ddp_comp_type comp_type;871 int comp_id;872 873 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);874 if (!of_id)875 continue;876 877 if (!of_device_is_available(node)) {878 dev_dbg(dev, "Skipping disabled component %pOF\n",879 node);880 continue;881 }882 883 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data;884 885 if (comp_type == MTK_DISP_MUTEX) {886 int id;887 888 id = of_alias_get_id(node, "mutex");889 if (id < 0 || id == private->data->mmsys_id) {890 private->mutex_node = of_node_get(node);891 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);892 }893 continue;894 }895 896 comp_id = mtk_ddp_comp_get_id(node, comp_type);897 if (comp_id < 0) {898 dev_warn(dev, "Skipping unknown component %pOF\n",899 node);900 continue;901 }902 903 if (!mtk_drm_find_mmsys_comp(private, comp_id))904 continue;905 906 private->comp_node[comp_id] = of_node_get(node);907 908 /*909 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI910 * blocks have separate component platform drivers and initialize their own911 * DDP component structure. The others are initialized here.912 */913 if (comp_type == MTK_DISP_AAL ||914 comp_type == MTK_DISP_CCORR ||915 comp_type == MTK_DISP_COLOR ||916 comp_type == MTK_DISP_GAMMA ||917 comp_type == MTK_DISP_MERGE ||918 comp_type == MTK_DISP_OVL ||919 comp_type == MTK_DISP_OVL_2L ||920 comp_type == MTK_DISP_OVL_ADAPTOR ||921 comp_type == MTK_DISP_RDMA ||922 comp_type == MTK_DP_INTF ||923 comp_type == MTK_DPI ||924 comp_type == MTK_DSI) {925 dev_info(dev, "Adding component match for %pOF\n",926 node);927 drm_of_component_match_add(dev, &match, component_compare_of,928 node);929 }930 931 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);932 if (ret) {933 of_node_put(node);934 goto err_node;935 }936 }937 938 if (!private->mutex_node) {939 dev_err(dev, "Failed to find disp-mutex node\n");940 ret = -ENODEV;941 goto err_node;942 }943 944 pm_runtime_enable(dev);945 946 platform_set_drvdata(pdev, private);947 948 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);949 if (ret)950 goto err_pm;951 952 return 0;953 954err_pm:955 pm_runtime_disable(dev);956err_node:957 of_node_put(private->mutex_node);958 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)959 of_node_put(private->comp_node[i]);960 return ret;961}962 963static void mtk_drm_remove(struct platform_device *pdev)964{965 struct mtk_drm_private *private = platform_get_drvdata(pdev);966 int i;967 968 component_master_del(&pdev->dev, &mtk_drm_ops);969 pm_runtime_disable(&pdev->dev);970 of_node_put(private->mutex_node);971 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)972 of_node_put(private->comp_node[i]);973}974 975static void mtk_drm_shutdown(struct platform_device *pdev)976{977 struct mtk_drm_private *private = platform_get_drvdata(pdev);978 979 drm_atomic_helper_shutdown(private->drm);980}981 982static int mtk_drm_sys_prepare(struct device *dev)983{984 struct mtk_drm_private *private = dev_get_drvdata(dev);985 struct drm_device *drm = private->drm;986 987 if (private->drm_master)988 return drm_mode_config_helper_suspend(drm);989 else990 return 0;991}992 993static void mtk_drm_sys_complete(struct device *dev)994{995 struct mtk_drm_private *private = dev_get_drvdata(dev);996 struct drm_device *drm = private->drm;997 int ret = 0;998 999 if (private->drm_master)1000 ret = drm_mode_config_helper_resume(drm);1001 if (ret)1002 dev_err(dev, "Failed to resume\n");1003}1004 1005static const struct dev_pm_ops mtk_drm_pm_ops = {1006 .prepare = mtk_drm_sys_prepare,1007 .complete = mtk_drm_sys_complete,1008};1009 1010static struct platform_driver mtk_drm_platform_driver = {1011 .probe = mtk_drm_probe,1012 .remove_new = mtk_drm_remove,1013 .shutdown = mtk_drm_shutdown,1014 .driver = {1015 .name = "mediatek-drm",1016 .pm = &mtk_drm_pm_ops,1017 },1018};1019 1020static struct platform_driver * const mtk_drm_drivers[] = {1021 &mtk_disp_aal_driver,1022 &mtk_disp_ccorr_driver,1023 &mtk_disp_color_driver,1024 &mtk_disp_gamma_driver,1025 &mtk_disp_merge_driver,1026 &mtk_disp_ovl_adaptor_driver,1027 &mtk_disp_ovl_driver,1028 &mtk_disp_rdma_driver,1029 &mtk_dpi_driver,1030 &mtk_drm_platform_driver,1031 &mtk_dsi_driver,1032 &mtk_ethdr_driver,1033 &mtk_mdp_rdma_driver,1034 &mtk_padding_driver,1035};1036 1037static int __init mtk_drm_init(void)1038{1039 return platform_register_drivers(mtk_drm_drivers,1040 ARRAY_SIZE(mtk_drm_drivers));1041}1042 1043static void __exit mtk_drm_exit(void)1044{1045 platform_unregister_drivers(mtk_drm_drivers,1046 ARRAY_SIZE(mtk_drm_drivers));1047}1048 1049module_init(mtk_drm_init);1050module_exit(mtk_drm_exit);1051 1052MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");1053MODULE_DESCRIPTION("Mediatek SoC DRM driver");1054MODULE_LICENSE("GPL v2");1055