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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2021 MediaTek Inc.4 */5 6#include <drm/drm_blend.h>7#include <drm/drm_fourcc.h>8#include <drm/drm_framebuffer.h>9#include <linux/clk.h>10#include <linux/component.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/platform_device.h>14#include <linux/reset.h>15#include <linux/soc/mediatek/mtk-cmdq.h>16#include <linux/soc/mediatek/mtk-mmsys.h>17 18#include "mtk_crtc.h"19#include "mtk_ddp_comp.h"20#include "mtk_drm_drv.h"21#include "mtk_ethdr.h"22 23#define MIX_INTEN 0x424#define MIX_FME_CPL_INTEN BIT(1)25#define MIX_INTSTA 0x826#define MIX_EN 0xc27#define MIX_RST 0x1428#define MIX_ROI_SIZE 0x1829#define MIX_DATAPATH_CON 0x1c30#define OUTPUT_NO_RND BIT(3)31#define SOURCE_RGB_SEL BIT(7)32#define BACKGROUND_RELAY (4 << 9)33#define MIX_ROI_BGCLR 0x2034#define BGCLR_BLACK 0xff00000035#define MIX_SRC_CON 0x2436#define MIX_SRC_L0_EN BIT(0)37#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))38#define NON_PREMULTI_SOURCE (2 << 12)39#define PREMULTI_SOURCE (3 << 12)40#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))41#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))42#define MIX_FUNC_DCM0 0x12043#define MIX_FUNC_DCM1 0x12444#define MIX_FUNC_DCM_ENABLE 0xffffffff45 46#define HDR_VDO_FE_0804_HDR_DM_FE 0x80447#define HDR_VDO_FE_0804_BYPASS_ALL 0xfd48#define HDR_GFX_FE_0204_GFX_HDR_FE 0x20449#define HDR_GFX_FE_0204_BYPASS_ALL 0xfd50#define HDR_VDO_BE_0204_VDO_DM_BE 0x20451#define HDR_VDO_BE_0204_BYPASS_ALL 0x7e52 53#define MIXER_INX_MODE_BYPASS 054#define MIXER_INX_MODE_EVEN_EXTEND 155#define MIXER_ALPHA_AEN BIT(8)56#define MIXER_ALPHA 0xff57#define ETHDR_CLK_NUM 1358 59enum mtk_ethdr_comp_id {60 ETHDR_MIXER,61 ETHDR_VDO_FE0,62 ETHDR_VDO_FE1,63 ETHDR_GFX_FE0,64 ETHDR_GFX_FE1,65 ETHDR_VDO_BE,66 ETHDR_ADL_DS,67 ETHDR_ID_MAX68};69 70struct mtk_ethdr_comp {71 struct device *dev;72 void __iomem *regs;73 struct cmdq_client_reg cmdq_base;74};75 76struct mtk_ethdr {77 struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];78 struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];79 struct device *mmsys_dev;80 void (*vblank_cb)(void *data);81 void *vblank_cb_data;82 int irq;83 struct reset_control *reset_ctl;84};85 86static const char * const ethdr_clk_str[] = {87 "ethdr_top",88 "mixer",89 "vdo_fe0",90 "vdo_fe1",91 "gfx_fe0",92 "gfx_fe1",93 "vdo_be",94 "adl_ds",95 "vdo_fe0_async",96 "vdo_fe1_async",97 "gfx_fe0_async",98 "gfx_fe1_async",99 "vdo_be_async",100};101 102void mtk_ethdr_register_vblank_cb(struct device *dev,103 void (*vblank_cb)(void *),104 void *vblank_cb_data)105{106 struct mtk_ethdr *priv = dev_get_drvdata(dev);107 108 priv->vblank_cb = vblank_cb;109 priv->vblank_cb_data = vblank_cb_data;110}111 112void mtk_ethdr_unregister_vblank_cb(struct device *dev)113{114 struct mtk_ethdr *priv = dev_get_drvdata(dev);115 116 priv->vblank_cb = NULL;117 priv->vblank_cb_data = NULL;118}119 120void mtk_ethdr_enable_vblank(struct device *dev)121{122 struct mtk_ethdr *priv = dev_get_drvdata(dev);123 124 writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);125}126 127void mtk_ethdr_disable_vblank(struct device *dev)128{129 struct mtk_ethdr *priv = dev_get_drvdata(dev);130 131 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);132}133 134static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)135{136 struct mtk_ethdr *priv = dev_id;137 138 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);139 140 if (!priv->vblank_cb)141 return IRQ_NONE;142 143 priv->vblank_cb(priv->vblank_cb_data);144 145 return IRQ_HANDLED;146}147 148u32 mtk_ethdr_get_blend_modes(struct device *dev)149{150 return BIT(DRM_MODE_BLEND_PREMULTI) |151 BIT(DRM_MODE_BLEND_COVERAGE) |152 BIT(DRM_MODE_BLEND_PIXEL_NONE);153}154 155void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,156 struct mtk_plane_state *state,157 struct cmdq_pkt *cmdq_pkt)158{159 struct mtk_ethdr *priv = dev_get_drvdata(dev);160 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];161 struct mtk_plane_pending_state *pending = &state->pending;162 unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;163 unsigned int align_width = ALIGN_DOWN(pending->width, 2);164 unsigned int alpha_con = 0;165 bool replace_src_a = false;166 167 dev_dbg(dev, "%s+ idx:%d", __func__, idx);168 169 if (idx >= 4)170 return;171 172 if (!pending->enable || !pending->width || !pending->height) {173 /*174 * instead of disabling layer with MIX_SRC_CON directly175 * set the size to 0 to avoid screen shift due to mixer176 * mode switch (hardware behavior)177 */178 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));179 return;180 }181 182 if (state->base.fb) {183 alpha_con |= MIXER_ALPHA_AEN;184 alpha_con |= state->base.alpha & MIXER_ALPHA;185 }186 187 if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)188 alpha_con |= PREMULTI_SOURCE;189 else190 alpha_con |= NON_PREMULTI_SOURCE;191 192 if ((state->base.fb && !state->base.fb->format->has_alpha) ||193 state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {194 /*195 * Mixer doesn't support CONST_BLD mode,196 * use a trick to make the output equivalent197 */198 replace_src_a = true;199 }200 201 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a,202 MIXER_ALPHA,203 pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :204 MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);205 206 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,207 mixer->regs, MIX_L_SRC_SIZE(idx));208 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));209 mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));210 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,211 BIT(idx));212}213 214void mtk_ethdr_config(struct device *dev, unsigned int w,215 unsigned int h, unsigned int vrefresh,216 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)217{218 struct mtk_ethdr *priv = dev_get_drvdata(dev);219 struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];220 struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];221 struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];222 struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];223 struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];224 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];225 226 dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);227 228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,229 vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);230 231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,232 vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);233 234 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,235 gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);236 237 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,238 gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);239 240 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,241 vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);242 243 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);244 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);245 mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);246 mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);247 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,248 MIX_L_SRC_CON(0));249 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,250 MIX_L_SRC_CON(1));251 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,252 MIX_L_SRC_CON(2));253 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,254 MIX_L_SRC_CON(3));255 mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));256 mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,257 &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);258 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,259 MIX_SRC_CON, MIX_SRC_L0_EN);260 261 mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt);262 mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt);263}264 265void mtk_ethdr_start(struct device *dev)266{267 struct mtk_ethdr *priv = dev_get_drvdata(dev);268 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];269 270 writel(1, mixer->regs + MIX_EN);271}272 273void mtk_ethdr_stop(struct device *dev)274{275 struct mtk_ethdr *priv = dev_get_drvdata(dev);276 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];277 278 writel(0, mixer->regs + MIX_EN);279 writel(1, mixer->regs + MIX_RST);280 reset_control_reset(priv->reset_ctl);281 writel(0, mixer->regs + MIX_RST);282}283 284int mtk_ethdr_clk_enable(struct device *dev)285{286 int ret;287 struct mtk_ethdr *priv = dev_get_drvdata(dev);288 289 ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);290 if (ret)291 dev_err(dev,292 "ethdr_clk prepare enable failed\n");293 return ret;294}295 296void mtk_ethdr_clk_disable(struct device *dev)297{298 struct mtk_ethdr *priv = dev_get_drvdata(dev);299 300 clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);301}302 303static int mtk_ethdr_bind(struct device *dev, struct device *master,304 void *data)305{306 struct mtk_ethdr *priv = dev_get_drvdata(dev);307 308 priv->mmsys_dev = data;309 return 0;310}311 312static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)313{314}315 316static const struct component_ops mtk_ethdr_component_ops = {317 .bind = mtk_ethdr_bind,318 .unbind = mtk_ethdr_unbind,319};320 321static int mtk_ethdr_probe(struct platform_device *pdev)322{323 struct device *dev = &pdev->dev;324 struct mtk_ethdr *priv;325 int ret;326 int i;327 328 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);329 if (!priv)330 return -ENOMEM;331 332 for (i = 0; i < ETHDR_ID_MAX; i++) {333 priv->ethdr_comp[i].dev = dev;334 priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);335#if IS_REACHABLE(CONFIG_MTK_CMDQ)336 ret = cmdq_dev_get_client_reg(dev,337 &priv->ethdr_comp[i].cmdq_base, i);338 if (ret)339 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");340#endif341 dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);342 }343 344 for (i = 0; i < ETHDR_CLK_NUM; i++)345 priv->ethdr_clk[i].id = ethdr_clk_str[i];346 ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);347 if (ret)348 return ret;349 350 priv->irq = platform_get_irq(pdev, 0);351 if (priv->irq < 0)352 priv->irq = 0;353 354 if (priv->irq) {355 ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,356 IRQF_TRIGGER_NONE, dev_name(dev), priv);357 if (ret < 0)358 return dev_err_probe(dev, ret,359 "Failed to request irq %d\n",360 priv->irq);361 }362 363 priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev);364 if (IS_ERR(priv->reset_ctl))365 return dev_err_probe(dev, PTR_ERR(priv->reset_ctl),366 "cannot get ethdr reset control\n");367 368 platform_set_drvdata(pdev, priv);369 370 ret = component_add(dev, &mtk_ethdr_component_ops);371 if (ret)372 return dev_err_probe(dev, ret, "Failed to add component\n");373 374 return 0;375}376 377static void mtk_ethdr_remove(struct platform_device *pdev)378{379 component_del(&pdev->dev, &mtk_ethdr_component_ops);380}381 382static const struct of_device_id mtk_ethdr_driver_dt_match[] = {383 { .compatible = "mediatek,mt8195-disp-ethdr"},384 {},385};386 387MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);388 389struct platform_driver mtk_ethdr_driver = {390 .probe = mtk_ethdr_probe,391 .remove_new = mtk_ethdr_remove,392 .driver = {393 .name = "mediatek-disp-ethdr",394 .of_match_table = mtk_ethdr_driver_dt_match,395 },396};397