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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2016 BayLibre, SAS4 * Author: Neil Armstrong <narmstrong@baylibre.com>5 */6 7#ifndef __MESON_DRV_H8#define __MESON_DRV_H9 10#include <linux/device.h>11#include <linux/of.h>12#include <linux/regmap.h>13 14struct drm_crtc;15struct drm_device;16struct drm_plane;17struct meson_drm;18struct meson_afbcd_ops;19 20enum vpu_compatible {21 VPU_COMPATIBLE_GXBB = 0,22 VPU_COMPATIBLE_GXL = 1,23 VPU_COMPATIBLE_GXM = 2,24 VPU_COMPATIBLE_G12A = 3,25};26 27enum {28 MESON_ENC_CVBS = 0,29 MESON_ENC_HDMI,30 MESON_ENC_DSI,31 MESON_ENC_LAST,32};33 34struct meson_drm_match_data {35 enum vpu_compatible compat;36 struct meson_afbcd_ops *afbcd_ops;37};38 39struct meson_drm_soc_limits {40 unsigned int max_hdmi_phy_freq;41};42 43struct meson_drm {44 struct device *dev;45 enum vpu_compatible compat;46 void __iomem *io_base;47 struct regmap *hhi;48 int vsync_irq;49 50 struct meson_canvas *canvas;51 u8 canvas_id_osd1;52 u8 canvas_id_vd1_0;53 u8 canvas_id_vd1_1;54 u8 canvas_id_vd1_2;55 56 struct drm_device *drm;57 struct drm_crtc *crtc;58 struct drm_plane *primary_plane;59 struct drm_plane *overlay_plane;60 void *encoders[MESON_ENC_LAST];61 62 const struct meson_drm_soc_limits *limits;63 64 /* Components Data */65 struct {66 bool osd1_enabled;67 bool osd1_interlace;68 bool osd1_commit;69 bool osd1_afbcd;70 uint32_t osd1_ctrl_stat;71 uint32_t osd1_ctrl_stat2;72 uint32_t osd1_blk0_cfg[5];73 uint32_t osd1_blk1_cfg4;74 uint32_t osd1_blk2_cfg4;75 uint32_t osd1_addr;76 uint32_t osd1_stride;77 uint32_t osd1_height;78 uint32_t osd1_width;79 uint32_t osd_sc_ctrl0;80 uint32_t osd_sc_i_wh_m1;81 uint32_t osd_sc_o_h_start_end;82 uint32_t osd_sc_o_v_start_end;83 uint32_t osd_sc_v_ini_phase;84 uint32_t osd_sc_v_phase_step;85 uint32_t osd_sc_h_ini_phase;86 uint32_t osd_sc_h_phase_step;87 uint32_t osd_sc_h_ctrl0;88 uint32_t osd_sc_v_ctrl0;89 uint32_t osd_blend_din0_scope_h;90 uint32_t osd_blend_din0_scope_v;91 uint32_t osb_blend0_size;92 uint32_t osb_blend1_size;93 94 bool vd1_enabled;95 bool vd1_commit;96 bool vd1_afbc;97 unsigned int vd1_planes;98 uint32_t vd1_if0_gen_reg;99 uint32_t vd1_if0_luma_x0;100 uint32_t vd1_if0_luma_y0;101 uint32_t vd1_if0_chroma_x0;102 uint32_t vd1_if0_chroma_y0;103 uint32_t vd1_if0_repeat_loop;104 uint32_t vd1_if0_luma0_rpt_pat;105 uint32_t vd1_if0_chroma0_rpt_pat;106 uint32_t vd1_range_map_y;107 uint32_t vd1_range_map_cb;108 uint32_t vd1_range_map_cr;109 uint32_t viu_vd1_fmt_w;110 uint32_t vd1_if0_canvas0;111 uint32_t vd1_if0_gen_reg2;112 uint32_t viu_vd1_fmt_ctrl;113 uint32_t vd1_addr0;114 uint32_t vd1_addr1;115 uint32_t vd1_addr2;116 uint32_t vd1_stride0;117 uint32_t vd1_stride1;118 uint32_t vd1_stride2;119 uint32_t vd1_height0;120 uint32_t vd1_height1;121 uint32_t vd1_height2;122 uint32_t vd1_afbc_mode;123 uint32_t vd1_afbc_en;124 uint32_t vd1_afbc_head_addr;125 uint32_t vd1_afbc_body_addr;126 uint32_t vd1_afbc_conv_ctrl;127 uint32_t vd1_afbc_dec_def_color;128 uint32_t vd1_afbc_vd_cfmt_ctrl;129 uint32_t vd1_afbc_vd_cfmt_w;130 uint32_t vd1_afbc_vd_cfmt_h;131 uint32_t vd1_afbc_mif_hor_scope;132 uint32_t vd1_afbc_mif_ver_scope;133 uint32_t vd1_afbc_size_out;134 uint32_t vd1_afbc_pixel_hor_scope;135 uint32_t vd1_afbc_pixel_ver_scope;136 uint32_t vd1_afbc_size_in;137 uint32_t vpp_pic_in_height;138 uint32_t vpp_postblend_vd1_h_start_end;139 uint32_t vpp_postblend_vd1_v_start_end;140 uint32_t vpp_hsc_region12_startp;141 uint32_t vpp_hsc_region34_startp;142 uint32_t vpp_hsc_region4_endp;143 uint32_t vpp_hsc_start_phase_step;144 uint32_t vpp_hsc_region1_phase_slope;145 uint32_t vpp_hsc_region3_phase_slope;146 uint32_t vpp_line_in_length;147 uint32_t vpp_preblend_h_size;148 uint32_t vpp_vsc_region12_startp;149 uint32_t vpp_vsc_region34_startp;150 uint32_t vpp_vsc_region4_endp;151 uint32_t vpp_vsc_start_phase_step;152 uint32_t vpp_vsc_ini_phase;153 uint32_t vpp_vsc_phase_ctrl;154 uint32_t vpp_hsc_phase_ctrl;155 uint32_t vpp_blend_vd2_h_start_end;156 uint32_t vpp_blend_vd2_v_start_end;157 } viu;158 159 struct {160 unsigned int current_mode;161 bool hdmi_repeat;162 bool venc_repeat;163 bool hdmi_use_enci;164 } venc;165 166 struct {167 dma_addr_t addr_dma;168 uint32_t *addr;169 unsigned int offset;170 } rdma;171 172 struct {173 struct meson_afbcd_ops *ops;174 u64 modifier;175 u32 format;176 } afbcd;177};178 179static inline int meson_vpu_is_compatible(struct meson_drm *priv,180 enum vpu_compatible family)181{182 return priv->compat == family;183}184 185#endif /* __MESON_DRV_H */186