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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.4 */5 6#ifndef __MESON_REGISTERS_H7#define __MESON_REGISTERS_H8 9#include <linux/io.h>10 11/* Shift all registers by 2 */12#define _REG(reg) ((reg) << 2)13 14#define writel_bits_relaxed(mask, val, addr) \15 writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr)16 17/* vpp2 */18#define VPP2_DUMMY_DATA 0x190019#define VPP2_LINE_IN_LENGTH 0x190120#define VPP2_PIC_IN_HEIGHT 0x190221#define VPP2_SCALE_COEF_IDX 0x190322#define VPP2_SCALE_COEF 0x190423#define VPP2_VSC_REGION12_STARTP 0x190524#define VPP2_VSC_REGION34_STARTP 0x190625#define VPP2_VSC_REGION4_ENDP 0x190726#define VPP2_VSC_START_PHASE_STEP 0x190827#define VPP2_VSC_REGION0_PHASE_SLOPE 0x190928#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a29#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b30#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c31#define VPP2_VSC_PHASE_CTRL 0x190d32#define VPP2_VSC_INI_PHASE 0x190e33#define VPP2_HSC_REGION12_STARTP 0x191034#define VPP2_HSC_REGION34_STARTP 0x191135#define VPP2_HSC_REGION4_ENDP 0x191236#define VPP2_HSC_START_PHASE_STEP 0x191337#define VPP2_HSC_REGION0_PHASE_SLOPE 0x191438#define VPP2_HSC_REGION1_PHASE_SLOPE 0x191539#define VPP2_HSC_REGION3_PHASE_SLOPE 0x191640#define VPP2_HSC_REGION4_PHASE_SLOPE 0x191741#define VPP2_HSC_PHASE_CTRL 0x191842#define VPP2_SC_MISC 0x191943#define VPP2_PREBLEND_VD1_H_START_END 0x191a44#define VPP2_PREBLEND_VD1_V_START_END 0x191b45#define VPP2_POSTBLEND_VD1_H_START_END 0x191c46#define VPP2_POSTBLEND_VD1_V_START_END 0x191d47#define VPP2_PREBLEND_H_SIZE 0x192048#define VPP2_POSTBLEND_H_SIZE 0x192149#define VPP2_HOLD_LINES 0x192250#define VPP2_BLEND_ONECOLOR_CTRL 0x192351#define VPP2_PREBLEND_CURRENT_XY 0x192452#define VPP2_POSTBLEND_CURRENT_XY 0x192553#define VPP2_MISC 0x192654#define VPP2_OFIFO_SIZE 0x192755#define VPP2_FIFO_STATUS 0x192856#define VPP2_SMOKE_CTRL 0x192957#define VPP2_SMOKE1_VAL 0x192a58#define VPP2_SMOKE2_VAL 0x192b59#define VPP2_SMOKE1_H_START_END 0x192d60#define VPP2_SMOKE1_V_START_END 0x192e61#define VPP2_SMOKE2_H_START_END 0x192f62#define VPP2_SMOKE2_V_START_END 0x193063#define VPP2_SCO_FIFO_CTRL 0x193364#define VPP2_HSC_PHASE_CTRL1 0x193465#define VPP2_HSC_INI_PAT_CTRL 0x193566#define VPP2_VADJ_CTRL 0x194067#define VPP2_VADJ1_Y 0x194168#define VPP2_VADJ1_MA_MB 0x194269#define VPP2_VADJ1_MC_MD 0x194370#define VPP2_VADJ2_Y 0x194471#define VPP2_VADJ2_MA_MB 0x194572#define VPP2_VADJ2_MC_MD 0x194673#define VPP2_MATRIX_PROBE_COLOR 0x195c74#define VPP2_MATRIX_HL_COLOR 0x195d75#define VPP2_MATRIX_PROBE_POS 0x195e76#define VPP2_MATRIX_CTRL 0x195f77#define VPP2_MATRIX_COEF00_01 0x196078#define VPP2_MATRIX_COEF02_10 0x196179#define VPP2_MATRIX_COEF11_12 0x196280#define VPP2_MATRIX_COEF20_21 0x196381#define VPP2_MATRIX_COEF22 0x196482#define VPP2_MATRIX_OFFSET0_1 0x196583#define VPP2_MATRIX_OFFSET2 0x196684#define VPP2_MATRIX_PRE_OFFSET0_1 0x196785#define VPP2_MATRIX_PRE_OFFSET2 0x196886#define VPP2_DUMMY_DATA1 0x196987#define VPP2_GAINOFF_CTRL0 0x196a88#define VPP2_GAINOFF_CTRL1 0x196b89#define VPP2_GAINOFF_CTRL2 0x196c90#define VPP2_GAINOFF_CTRL3 0x196d91#define VPP2_GAINOFF_CTRL4 0x196e92#define VPP2_CHROMA_ADDR_PORT 0x197093#define VPP2_CHROMA_DATA_PORT 0x197194#define VPP2_GCLK_CTRL0 0x197295#define VPP2_GCLK_CTRL1 0x197396#define VPP2_SC_GCLK_CTRL 0x197497#define VPP2_MISC1 0x197698#define VPP2_DNLP_CTRL_00 0x198199#define VPP2_DNLP_CTRL_01 0x1982100#define VPP2_DNLP_CTRL_02 0x1983101#define VPP2_DNLP_CTRL_03 0x1984102#define VPP2_DNLP_CTRL_04 0x1985103#define VPP2_DNLP_CTRL_05 0x1986104#define VPP2_DNLP_CTRL_06 0x1987105#define VPP2_DNLP_CTRL_07 0x1988106#define VPP2_DNLP_CTRL_08 0x1989107#define VPP2_DNLP_CTRL_09 0x198a108#define VPP2_DNLP_CTRL_10 0x198b109#define VPP2_DNLP_CTRL_11 0x198c110#define VPP2_DNLP_CTRL_12 0x198d111#define VPP2_DNLP_CTRL_13 0x198e112#define VPP2_DNLP_CTRL_14 0x198f113#define VPP2_DNLP_CTRL_15 0x1990114#define VPP2_VE_ENABLE_CTRL 0x19a1115#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2116#define VPP2_VE_DEMO_CENTER_BAR 0x19a3117#define VPP2_VE_H_V_SIZE 0x19a4118#define VPP2_VDO_MEAS_CTRL 0x19a8119#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9120#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa121#define VPP2_OSD_VSC_PHASE_STEP 0x19c0122#define VPP2_OSD_VSC_INI_PHASE 0x19c1123#define VPP2_OSD_VSC_CTRL0 0x19c2124#define VPP2_OSD_HSC_PHASE_STEP 0x19c3125#define VPP2_OSD_HSC_INI_PHASE 0x19c4126#define VPP2_OSD_HSC_CTRL0 0x19c5127#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6128#define VPP2_OSD_SC_DUMMY_DATA 0x19c7129#define VPP2_OSD_SC_CTRL0 0x19c8130#define VPP2_OSD_SCI_WH_M1 0x19c9131#define VPP2_OSD_SCO_H_START_END 0x19ca132#define VPP2_OSD_SCO_V_START_END 0x19cb133#define VPP2_OSD_SCALE_COEF_IDX 0x19cc134#define VPP2_OSD_SCALE_COEF 0x19cd135#define VPP2_INT_LINE_NUM 0x19ce136 137/* viu */138#define VIU_ADDR_START 0x1a00139#define VIU_ADDR_END 0x1aff140#define VIU_SW_RESET 0x1a01141#define VIU_SW_RESET_OSD1_AFBCD BIT(31)142#define VIU_SW_RESET_G12A_OSD1_AFBCD BIT(21)143#define VIU_SW_RESET_G12A_AFBC_ARB BIT(19)144#define VIU_SW_RESET_OSD1 BIT(0)145#define VIU_MISC_CTRL0 0x1a06146#define VIU_CTRL0_VD1_AFBC_MASK 0x170000147#define VIU_CTRL0_AFBC_TO_VD1 BIT(20)148#define VIU_MISC_CTRL1 0x1a07149#define MALI_AFBC_MISC GENMASK(15, 8)150#define D2D3_INTF_LENGTH 0x1a08151#define D2D3_INTF_CTRL0 0x1a09152#define VD1_AFBCD0_MISC_CTRL 0x1a0a153#define VD1_AXI_SEL_AFBC (1 << 12)154#define AFBC_VD1_SEL (1 << 10)155#define VD2_AFBCD1_MISC_CTRL 0x1a0b156#define VIU_OSD1_CTRL_STAT 0x1a10157#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)158#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)159#define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8)160#define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8)161#define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8)162#define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8)163#define VIU_OSD1_OSD_ENABLE BIT(21)164#define VIU_OSD1_CFG_SYN_EN BIT(31)165#define VIU_OSD1_CTRL_STAT2 0x1a2d166#define VIU_OSD1_COLOR_ADDR 0x1a11167#define VIU_OSD1_COLOR 0x1a12168#define VIU_OSD1_TCOLOR_AG0 0x1a17169#define VIU_OSD1_TCOLOR_AG1 0x1a18170#define VIU_OSD1_TCOLOR_AG2 0x1a19171#define VIU_OSD1_TCOLOR_AG3 0x1a1a172#define VIU_OSD1_BLK0_CFG_W0 0x1a1b173#define VIU_OSD1_BLK1_CFG_W0 0x1a1f174#define VIU_OSD1_BLK2_CFG_W0 0x1a23175#define VIU_OSD1_BLK3_CFG_W0 0x1a27176#define VIU_OSD1_BLK0_CFG_W1 0x1a1c177#define VIU_OSD1_BLK1_CFG_W1 0x1a20178#define VIU_OSD1_BLK2_CFG_W1 0x1a24179#define VIU_OSD1_BLK3_CFG_W1 0x1a28180#define VIU_OSD1_BLK0_CFG_W2 0x1a1d181#define VIU_OSD1_BLK1_CFG_W2 0x1a21182#define VIU_OSD1_BLK2_CFG_W2 0x1a25183#define VIU_OSD1_BLK3_CFG_W2 0x1a29184#define VIU_OSD1_BLK0_CFG_W3 0x1a1e185#define VIU_OSD1_BLK1_CFG_W3 0x1a22186#define VIU_OSD1_BLK2_CFG_W3 0x1a26187#define VIU_OSD1_BLK3_CFG_W3 0x1a2a188#define VIU_OSD1_BLK0_CFG_W4 0x1a13189#define VIU_OSD1_BLK1_CFG_W4 0x1a14190#define VIU_OSD1_BLK2_CFG_W4 0x1a15191#define VIU_OSD1_BLK3_CFG_W4 0x1a16192#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b193#define VIU_OSD1_TEST_RDDATA 0x1a2c194#define VIU_OSD1_PROT_CTRL 0x1a2e195#define VIU_OSD1_MALI_UNPACK_CTRL 0x1a2f196#define VIU_OSD1_MALI_UNPACK_EN BIT(31)197#define VIU_OSD1_MALI_AFBCD_R_REORDER GENMASK(15, 12)198#define VIU_OSD1_MALI_AFBCD_G_REORDER GENMASK(11, 8)199#define VIU_OSD1_MALI_AFBCD_B_REORDER GENMASK(7, 4)200#define VIU_OSD1_MALI_AFBCD_A_REORDER GENMASK(3, 0)201#define VIU_OSD1_MALI_REORDER_R 1202#define VIU_OSD1_MALI_REORDER_G 2203#define VIU_OSD1_MALI_REORDER_B 3204#define VIU_OSD1_MALI_REORDER_A 4205#define VIU_OSD2_CTRL_STAT 0x1a30206#define VIU_OSD2_CTRL_STAT2 0x1a4d207#define VIU_OSD2_COLOR_ADDR 0x1a31208#define VIU_OSD2_COLOR 0x1a32209#define VIU_OSD2_HL1_H_START_END 0x1a33210#define VIU_OSD2_HL1_V_START_END 0x1a34211#define VIU_OSD2_HL2_H_START_END 0x1a35212#define VIU_OSD2_HL2_V_START_END 0x1a36213#define VIU_OSD2_TCOLOR_AG0 0x1a37214#define VIU_OSD2_TCOLOR_AG1 0x1a38215#define VIU_OSD2_TCOLOR_AG2 0x1a39216#define VIU_OSD2_TCOLOR_AG3 0x1a3a217#define VIU_OSD2_BLK0_CFG_W0 0x1a3b218#define VIU_OSD2_BLK1_CFG_W0 0x1a3f219#define VIU_OSD2_BLK2_CFG_W0 0x1a43220#define VIU_OSD2_BLK3_CFG_W0 0x1a47221#define VIU_OSD2_BLK0_CFG_W1 0x1a3c222#define VIU_OSD2_BLK1_CFG_W1 0x1a40223#define VIU_OSD2_BLK2_CFG_W1 0x1a44224#define VIU_OSD2_BLK3_CFG_W1 0x1a48225#define VIU_OSD2_BLK0_CFG_W2 0x1a3d226#define VIU_OSD2_BLK1_CFG_W2 0x1a41227#define VIU_OSD2_BLK2_CFG_W2 0x1a45228#define VIU_OSD2_BLK3_CFG_W2 0x1a49229#define VIU_OSD2_BLK0_CFG_W3 0x1a3e230#define VIU_OSD2_BLK1_CFG_W3 0x1a42231#define VIU_OSD2_BLK2_CFG_W3 0x1a46232#define VIU_OSD2_BLK3_CFG_W3 0x1a4a233#define VIU_OSD2_BLK0_CFG_W4 0x1a64234#define VIU_OSD2_BLK1_CFG_W4 0x1a65235#define VIU_OSD2_BLK2_CFG_W4 0x1a66236#define VIU_OSD2_BLK3_CFG_W4 0x1a67237#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b238#define VIU_OSD2_TEST_RDDATA 0x1a4c239#define VIU_OSD2_PROT_CTRL 0x1a4e240#define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd241#define VIU_OSD2_DIMM_CTRL 0x1acf242 243#define VIU_OSD3_CTRL_STAT 0x3d80244#define VIU_OSD3_CTRL_STAT2 0x3d81245#define VIU_OSD3_COLOR_ADDR 0x3d82246#define VIU_OSD3_COLOR 0x3d83247#define VIU_OSD3_TCOLOR_AG0 0x3d84248#define VIU_OSD3_TCOLOR_AG1 0x3d85249#define VIU_OSD3_TCOLOR_AG2 0x3d86250#define VIU_OSD3_TCOLOR_AG3 0x3d87251#define VIU_OSD3_BLK0_CFG_W0 0x3d88252#define VIU_OSD3_BLK0_CFG_W1 0x3d8c253#define VIU_OSD3_BLK0_CFG_W2 0x3d90254#define VIU_OSD3_BLK0_CFG_W3 0x3d94255#define VIU_OSD3_BLK0_CFG_W4 0x3d98256#define VIU_OSD3_BLK1_CFG_W4 0x3d99257#define VIU_OSD3_BLK2_CFG_W4 0x3d9a258#define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c259#define VIU_OSD3_TEST_RDDATA 0x3d9d260#define VIU_OSD3_PROT_CTRL 0x3d9e261#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f262#define VIU_OSD3_DIMM_CTRL 0x3da0263 264#define VIU_OSD_DDR_PRIORITY_URGENT BIT(0)265#define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5)266#define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12)267#define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22)268#define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24)269#define VIU_OSD_BURST_LENGTH_24 (0x0 << 31 | 0x0 << 10)270#define VIU_OSD_BURST_LENGTH_32 (0x0 << 31 | 0x1 << 10)271#define VIU_OSD_BURST_LENGTH_48 (0x0 << 31 | 0x2 << 10)272#define VIU_OSD_BURST_LENGTH_64 (0x0 << 31 | 0x3 << 10)273#define VIU_OSD_BURST_LENGTH_96 (0x1 << 31 | 0x0 << 10)274#define VIU_OSD_BURST_LENGTH_128 (0x1 << 31 | 0x1 << 10)275 276#define VD1_IF0_GEN_REG 0x1a50277#define VD1_IF0_CANVAS0 0x1a51278#define VD1_IF0_CANVAS1 0x1a52279#define VD1_IF0_LUMA_X0 0x1a53280#define VD1_IF0_LUMA_Y0 0x1a54281#define VD1_IF0_CHROMA_X0 0x1a55282#define VD1_IF0_CHROMA_Y0 0x1a56283#define VD1_IF0_LUMA_X1 0x1a57284#define VD1_IF0_LUMA_Y1 0x1a58285#define VD1_IF0_CHROMA_X1 0x1a59286#define VD1_IF0_CHROMA_Y1 0x1a5a287#define VD1_IF0_RPT_LOOP 0x1a5b288#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c289#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d290#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e291#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f292#define VD1_IF0_LUMA_PSEL 0x1a60293#define VD1_IF0_CHROMA_PSEL 0x1a61294#define VD1_IF0_DUMMY_PIXEL 0x1a62295#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63296#define VD1_IF0_RANGE_MAP_Y 0x1a6a297#define VD1_IF0_RANGE_MAP_CB 0x1a6b298#define VD1_IF0_RANGE_MAP_CR 0x1a6c299#define VD1_IF0_GEN_REG2 0x1a6d300#define VD1_IF0_PROT_CNTL 0x1a6e301#define VIU_VD1_FMT_CTRL 0x1a68302#define VIU_VD1_FMT_W 0x1a69303#define VD2_IF0_GEN_REG 0x1a70304#define VD2_IF0_CANVAS0 0x1a71305#define VD2_IF0_CANVAS1 0x1a72306#define VD2_IF0_LUMA_X0 0x1a73307#define VD2_IF0_LUMA_Y0 0x1a74308#define VD2_IF0_CHROMA_X0 0x1a75309#define VD2_IF0_CHROMA_Y0 0x1a76310#define VD2_IF0_LUMA_X1 0x1a77311#define VD2_IF0_LUMA_Y1 0x1a78312#define VD2_IF0_CHROMA_X1 0x1a79313#define VD2_IF0_CHROMA_Y1 0x1a7a314#define VD2_IF0_RPT_LOOP 0x1a7b315#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c316#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d317#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e318#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f319#define VD2_IF0_LUMA_PSEL 0x1a80320#define VD2_IF0_CHROMA_PSEL 0x1a81321#define VD2_IF0_DUMMY_PIXEL 0x1a82322#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83323#define VD2_IF0_RANGE_MAP_Y 0x1a8a324#define VD2_IF0_RANGE_MAP_CB 0x1a8b325#define VD2_IF0_RANGE_MAP_CR 0x1a8c326#define VD2_IF0_GEN_REG2 0x1a8d327#define VD2_IF0_PROT_CNTL 0x1a8e328#define VIU_VD2_FMT_CTRL 0x1a88329#define VIU_VD2_FMT_W 0x1a89330 331/* VIU Matrix Registers */332#define VIU_OSD1_MATRIX_CTRL 0x1a90333#define VIU_OSD1_MATRIX_COEF00_01 0x1a91334#define VIU_OSD1_MATRIX_COEF02_10 0x1a92335#define VIU_OSD1_MATRIX_COEF11_12 0x1a93336#define VIU_OSD1_MATRIX_COEF20_21 0x1a94337#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95338#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96339#define VIU_OSD1_MATRIX_OFFSET2 0x1a97340#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98341#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99342#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d343#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e344#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f345#define VD1_IF0_GEN_REG3 0x1aa7346 347#define VIU_OSD_BLENDO_H_START_END 0x1aa9348#define VIU_OSD_BLENDO_V_START_END 0x1aaa349#define VIU_OSD_BLEND_GEN_CTRL0 0x1aab350#define VIU_OSD_BLEND_GEN_CTRL1 0x1aac351#define VIU_OSD_BLEND_DUMMY_DATA 0x1aad352#define VIU_OSD_BLEND_CURRENT_XY 0x1aae353 354#define VIU_OSD2_MATRIX_CTRL 0x1ab0355#define VIU_OSD2_MATRIX_COEF00_01 0x1ab1356#define VIU_OSD2_MATRIX_COEF02_10 0x1ab2357#define VIU_OSD2_MATRIX_COEF11_12 0x1ab3358#define VIU_OSD2_MATRIX_COEF20_21 0x1ab4359#define VIU_OSD2_MATRIX_COEF22 0x1ab5360#define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6361#define VIU_OSD2_MATRIX_OFFSET2 0x1ab7362#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8363#define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9364#define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba365#define VIU_OSD2_MATRIX_HL_COLOR 0x1abb366#define VIU_OSD2_MATRIX_PROBE_POS 0x1abc367#define VIU_OSD1_EOTF_CTL 0x1ad4368#define VIU_OSD1_EOTF_COEF00_01 0x1ad5369#define VIU_OSD1_EOTF_COEF02_10 0x1ad6370#define VIU_OSD1_EOTF_COEF11_12 0x1ad7371#define VIU_OSD1_EOTF_COEF20_21 0x1ad8372#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9373#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada374#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb375#define VIU_OSD1_OETF_CTL 0x1adc376#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add377#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade378#define AFBC_ENABLE 0x1ae0379#define AFBC_MODE 0x1ae1380#define AFBC_SIZE_IN 0x1ae2381#define AFBC_DEC_DEF_COLOR 0x1ae3382#define AFBC_CONV_CTRL 0x1ae4383#define AFBC_LBUF_DEPTH 0x1ae5384#define AFBC_HEAD_BADDR 0x1ae6385#define AFBC_BODY_BADDR 0x1ae7386#define AFBC_SIZE_OUT 0x1ae8387#define AFBC_OUT_YSCOPE 0x1ae9388#define AFBC_STAT 0x1aea389#define AFBC_VD_CFMT_CTRL 0x1aeb390#define AFBC_VD_CFMT_W 0x1aec391#define AFBC_MIF_HOR_SCOPE 0x1aed392#define AFBC_MIF_VER_SCOPE 0x1aee393#define AFBC_PIXEL_HOR_SCOPE 0x1aef394#define AFBC_PIXEL_VER_SCOPE 0x1af0395#define AFBC_VD_CFMT_H 0x1af1396 397/* vpp */398#define VPP_DUMMY_DATA 0x1d00399#define VPP_LINE_IN_LENGTH 0x1d01400#define VPP_PIC_IN_HEIGHT 0x1d02401#define VPP_SCALE_COEF_IDX 0x1d03402#define VPP_SCALE_HORIZONTAL_COEF BIT(8)403#define VPP_SCALE_COEF 0x1d04404#define VPP_VSC_REGION12_STARTP 0x1d05405#define VPP_VSC_REGION34_STARTP 0x1d06406#define VPP_VSC_REGION4_ENDP 0x1d07407#define VPP_VSC_START_PHASE_STEP 0x1d08408#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09409#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a410#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b411#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c412#define VPP_VSC_PHASE_CTRL 0x1d0d413#define VPP_VSC_INI_PHASE 0x1d0e414#define VPP_HSC_REGION12_STARTP 0x1d10415#define VPP_HSC_REGION34_STARTP 0x1d11416#define VPP_HSC_REGION4_ENDP 0x1d12417#define VPP_HSC_START_PHASE_STEP 0x1d13418#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14419#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15420#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16421#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17422#define VPP_HSC_PHASE_CTRL 0x1d18423#define VPP_SC_MISC 0x1d19424#define VPP_SC_VD_EN_ENABLE BIT(15)425#define VPP_SC_TOP_EN_ENABLE BIT(16)426#define VPP_SC_HSC_EN_ENABLE BIT(17)427#define VPP_SC_VSC_EN_ENABLE BIT(18)428#define VPP_VSC_BANK_LENGTH(length) (length & 0x7)429#define VPP_HSC_BANK_LENGTH(length) ((length & 0x7) << 8)430#define VPP_PREBLEND_VD1_H_START_END 0x1d1a431#define VPP_PREBLEND_VD1_V_START_END 0x1d1b432#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c433#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d434#define VPP_BLEND_VD2_H_START_END 0x1d1e435#define VPP_BLEND_VD2_V_START_END 0x1d1f436#define VPP_PREBLEND_H_SIZE 0x1d20437#define VPP_POSTBLEND_H_SIZE 0x1d21438#define VPP_HOLD_LINES 0x1d22439#define VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf)440#define VPP_PREBLEND_HOLD_LINES(lines) ((lines & 0xf) << 8)441#define VPP_BLEND_ONECOLOR_CTRL 0x1d23442#define VPP_PREBLEND_CURRENT_XY 0x1d24443#define VPP_POSTBLEND_CURRENT_XY 0x1d25444#define VPP_MISC 0x1d26445#define VPP_PREBLEND_ENABLE BIT(6)446#define VPP_POSTBLEND_ENABLE BIT(7)447#define VPP_OSD2_ALPHA_PREMULT BIT(8)448#define VPP_OSD1_ALPHA_PREMULT BIT(9)449#define VPP_VD1_POSTBLEND BIT(10)450#define VPP_VD2_POSTBLEND BIT(11)451#define VPP_OSD1_POSTBLEND BIT(12)452#define VPP_OSD2_POSTBLEND BIT(13)453#define VPP_VD1_PREBLEND BIT(14)454#define VPP_VD2_PREBLEND BIT(15)455#define VPP_OSD1_PREBLEND BIT(16)456#define VPP_OSD2_PREBLEND BIT(17)457#define VPP_COLOR_MNG_ENABLE BIT(28)458#define VPP_OFIFO_SIZE 0x1d27459#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0)460#define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000)461#define VPP_FIFO_STATUS 0x1d28462#define VPP_SMOKE_CTRL 0x1d29463#define VPP_SMOKE1_VAL 0x1d2a464#define VPP_SMOKE2_VAL 0x1d2b465#define VPP_SMOKE3_VAL 0x1d2c466#define VPP_SMOKE1_H_START_END 0x1d2d467#define VPP_SMOKE1_V_START_END 0x1d2e468#define VPP_SMOKE2_H_START_END 0x1d2f469#define VPP_SMOKE2_V_START_END 0x1d30470#define VPP_SMOKE3_H_START_END 0x1d31471#define VPP_SMOKE3_V_START_END 0x1d32472#define VPP_SCO_FIFO_CTRL 0x1d33473#define VPP_HSC_PHASE_CTRL1 0x1d34474#define VPP_HSC_INI_PAT_CTRL 0x1d35475#define VPP_VADJ_CTRL 0x1d40476#define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1)477 478#define VPP_VADJ1_Y 0x1d41479#define VPP_VADJ1_MA_MB 0x1d42480#define VPP_VADJ1_MC_MD 0x1d43481#define VPP_VADJ2_Y 0x1d44482#define VPP_VADJ2_MA_MB 0x1d45483#define VPP_VADJ2_MC_MD 0x1d46484#define VPP_HSHARP_CTRL 0x1d50485#define VPP_HSHARP_LUMA_THRESH01 0x1d51486#define VPP_HSHARP_LUMA_THRESH23 0x1d52487#define VPP_HSHARP_CHROMA_THRESH01 0x1d53488#define VPP_HSHARP_CHROMA_THRESH23 0x1d54489#define VPP_HSHARP_LUMA_GAIN 0x1d55490#define VPP_HSHARP_CHROMA_GAIN 0x1d56491#define VPP_MATRIX_PROBE_COLOR 0x1d5c492#define VPP_MATRIX_HL_COLOR 0x1d5d493#define VPP_MATRIX_PROBE_POS 0x1d5e494#define VPP_MATRIX_CTRL 0x1d5f495#define VPP_MATRIX_COEF00_01 0x1d60496#define VPP_MATRIX_COEF02_10 0x1d61497#define VPP_MATRIX_COEF11_12 0x1d62498#define VPP_MATRIX_COEF20_21 0x1d63499#define VPP_MATRIX_COEF22 0x1d64500#define VPP_MATRIX_OFFSET0_1 0x1d65501#define VPP_MATRIX_OFFSET2 0x1d66502#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67503#define VPP_MATRIX_PRE_OFFSET2 0x1d68504#define VPP_DUMMY_DATA1 0x1d69505#define VPP_GAINOFF_CTRL0 0x1d6a506#define VPP_GAINOFF_CTRL1 0x1d6b507#define VPP_GAINOFF_CTRL2 0x1d6c508#define VPP_GAINOFF_CTRL3 0x1d6d509#define VPP_GAINOFF_CTRL4 0x1d6e510#define VPP_CHROMA_ADDR_PORT 0x1d70511#define VPP_CHROMA_DATA_PORT 0x1d71512#define VPP_GCLK_CTRL0 0x1d72513#define VPP_GCLK_CTRL1 0x1d73514#define VPP_SC_GCLK_CTRL 0x1d74515#define VPP_MISC1 0x1d76516#define VPP_BLACKEXT_CTRL 0x1d80517#define VPP_DNLP_CTRL_00 0x1d81518#define VPP_DNLP_CTRL_01 0x1d82519#define VPP_DNLP_CTRL_02 0x1d83520#define VPP_DNLP_CTRL_03 0x1d84521#define VPP_DNLP_CTRL_04 0x1d85522#define VPP_DNLP_CTRL_05 0x1d86523#define VPP_DNLP_CTRL_06 0x1d87524#define VPP_DNLP_CTRL_07 0x1d88525#define VPP_DNLP_CTRL_08 0x1d89526#define VPP_DNLP_CTRL_09 0x1d8a527#define VPP_DNLP_CTRL_10 0x1d8b528#define VPP_DNLP_CTRL_11 0x1d8c529#define VPP_DNLP_CTRL_12 0x1d8d530#define VPP_DNLP_CTRL_13 0x1d8e531#define VPP_DNLP_CTRL_14 0x1d8f532#define VPP_DNLP_CTRL_15 0x1d90533#define VPP_PEAKING_HGAIN 0x1d91534#define VPP_PEAKING_VGAIN 0x1d92535#define VPP_PEAKING_NLP_1 0x1d93536#define VPP_DOLBY_CTRL 0x1d93537#define VPP_PPS_DUMMY_DATA_MODE (1 << 17)538#define VPP_PEAKING_NLP_2 0x1d94539#define VPP_PEAKING_NLP_3 0x1d95540#define VPP_PEAKING_NLP_4 0x1d96541#define VPP_PEAKING_NLP_5 0x1d97542#define VPP_SHARP_LIMIT 0x1d98543#define VPP_VLTI_CTRL 0x1d99544#define VPP_HLTI_CTRL 0x1d9a545#define VPP_CTI_CTRL 0x1d9b546#define VPP_BLUE_STRETCH_1 0x1d9c547#define VPP_BLUE_STRETCH_2 0x1d9d548#define VPP_BLUE_STRETCH_3 0x1d9e549#define VPP_CCORING_CTRL 0x1da0550#define VPP_VE_ENABLE_CTRL 0x1da1551#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2552#define VPP_VE_DEMO_CENTER_BAR 0x1da3553#define VPP_VE_H_V_SIZE 0x1da4554#define VPP_VDO_MEAS_CTRL 0x1da8555#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9556#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa557#define VPP_INPUT_CTRL 0x1dab558#define VPP_CTI_CTRL2 0x1dac559#define VPP_PEAKING_SAT_THD1 0x1dad560#define VPP_PEAKING_SAT_THD2 0x1dae561#define VPP_PEAKING_SAT_THD3 0x1daf562#define VPP_PEAKING_SAT_THD4 0x1db0563#define VPP_PEAKING_SAT_THD5 0x1db1564#define VPP_PEAKING_SAT_THD6 0x1db2565#define VPP_PEAKING_SAT_THD7 0x1db3566#define VPP_PEAKING_SAT_THD8 0x1db4567#define VPP_PEAKING_SAT_THD9 0x1db5568#define VPP_PEAKING_GAIN_ADD1 0x1db6569#define VPP_PEAKING_GAIN_ADD2 0x1db7570#define VPP_PEAKING_DNLP 0x1db8571#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9572#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba573#define VPP_FRONT_HLTI_CTRL 0x1dbb574#define VPP_FRONT_CTI_CTRL 0x1dbc575#define VPP_FRONT_CTI_CTRL2 0x1dbd576#define VPP_OSD_VSC_PHASE_STEP 0x1dc0577#define VPP_OSD_VSC_INI_PHASE 0x1dc1578#define VPP_OSD_VSC_CTRL0 0x1dc2579#define VPP_OSD_HSC_PHASE_STEP 0x1dc3580#define VPP_OSD_HSC_INI_PHASE 0x1dc4581#define VPP_OSD_HSC_CTRL0 0x1dc5582#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6583#define VPP_OSD_SC_DUMMY_DATA 0x1dc7584#define VPP_OSD_SC_CTRL0 0x1dc8585#define VPP_OSD_SCI_WH_M1 0x1dc9586#define VPP_OSD_SCO_H_START_END 0x1dca587#define VPP_OSD_SCO_V_START_END 0x1dcb588#define VPP_OSD_SCALE_COEF_IDX 0x1dcc589#define VPP_OSD_SCALE_COEF 0x1dcd590#define VPP_INT_LINE_NUM 0x1dce591 592#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60593#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61594#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62595#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63596#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64597#define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65598#define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66599#define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67600#define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68601#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69602#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a603#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b604#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c605#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d606 607#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70608#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71609#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72610#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73611#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74612#define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75613#define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76614#define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77615#define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78616#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79617#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a618#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b619#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c620#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d621 622#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0623#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1624#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2625#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3626#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4627#define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5628#define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6629#define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7630#define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8631#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9632#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba633#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb634#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc635#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd636 637/* osd1 HDR */638#define OSD1_HDR2_CTRL 0x38a0639#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN BIT(13)640#define OSD1_HDR2_CTRL_REG_ONLY_MAT BIT(16)641 642/* osd2 scaler */643#define OSD2_VSC_PHASE_STEP 0x3d00644#define OSD2_VSC_INI_PHASE 0x3d01645#define OSD2_VSC_CTRL0 0x3d02646#define OSD2_HSC_PHASE_STEP 0x3d03647#define OSD2_HSC_INI_PHASE 0x3d04648#define OSD2_HSC_CTRL0 0x3d05649#define OSD2_HSC_INI_PAT_CTRL 0x3d06650#define OSD2_SC_DUMMY_DATA 0x3d07651#define OSD2_SC_CTRL0 0x3d08652#define OSD2_SCI_WH_M1 0x3d09653#define OSD2_SCO_H_START_END 0x3d0a654#define OSD2_SCO_V_START_END 0x3d0b655#define OSD2_SCALE_COEF_IDX 0x3d18656#define OSD2_SCALE_COEF 0x3d19657 658/* osd34 scaler */659#define OSD34_SCALE_COEF_IDX 0x3d1e660#define OSD34_SCALE_COEF 0x3d1f661#define OSD34_VSC_PHASE_STEP 0x3d20662#define OSD34_VSC_INI_PHASE 0x3d21663#define OSD34_VSC_CTRL0 0x3d22664#define OSD34_HSC_PHASE_STEP 0x3d23665#define OSD34_HSC_INI_PHASE 0x3d24666#define OSD34_HSC_CTRL0 0x3d25667#define OSD34_HSC_INI_PAT_CTRL 0x3d26668#define OSD34_SC_DUMMY_DATA 0x3d27669#define OSD34_SC_CTRL0 0x3d28670#define OSD34_SCI_WH_M1 0x3d29671#define OSD34_SCO_H_START_END 0x3d2a672#define OSD34_SCO_V_START_END 0x3d2b673 674/* viu2 */675#define VIU2_ADDR_START 0x1e00676#define VIU2_ADDR_END 0x1eff677#define VIU2_SW_RESET 0x1e01678#define VIU2_OSD1_CTRL_STAT 0x1e10679#define VIU2_OSD1_CTRL_STAT2 0x1e2d680#define VIU2_OSD1_COLOR_ADDR 0x1e11681#define VIU2_OSD1_COLOR 0x1e12682#define VIU2_OSD1_TCOLOR_AG0 0x1e17683#define VIU2_OSD1_TCOLOR_AG1 0x1e18684#define VIU2_OSD1_TCOLOR_AG2 0x1e19685#define VIU2_OSD1_TCOLOR_AG3 0x1e1a686#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b687#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f688#define VIU2_OSD1_BLK2_CFG_W0 0x1e23689#define VIU2_OSD1_BLK3_CFG_W0 0x1e27690#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c691#define VIU2_OSD1_BLK1_CFG_W1 0x1e20692#define VIU2_OSD1_BLK2_CFG_W1 0x1e24693#define VIU2_OSD1_BLK3_CFG_W1 0x1e28694#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d695#define VIU2_OSD1_BLK1_CFG_W2 0x1e21696#define VIU2_OSD1_BLK2_CFG_W2 0x1e25697#define VIU2_OSD1_BLK3_CFG_W2 0x1e29698#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e699#define VIU2_OSD1_BLK1_CFG_W3 0x1e22700#define VIU2_OSD1_BLK2_CFG_W3 0x1e26701#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a702#define VIU2_OSD1_BLK0_CFG_W4 0x1e13703#define VIU2_OSD1_BLK1_CFG_W4 0x1e14704#define VIU2_OSD1_BLK2_CFG_W4 0x1e15705#define VIU2_OSD1_BLK3_CFG_W4 0x1e16706#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b707#define VIU2_OSD1_TEST_RDDATA 0x1e2c708#define VIU2_OSD1_PROT_CTRL 0x1e2e709#define VIU2_OSD2_CTRL_STAT 0x1e30710#define VIU2_OSD2_CTRL_STAT2 0x1e4d711#define VIU2_OSD2_COLOR_ADDR 0x1e31712#define VIU2_OSD2_COLOR 0x1e32713#define VIU2_OSD2_HL1_H_START_END 0x1e33714#define VIU2_OSD2_HL1_V_START_END 0x1e34715#define VIU2_OSD2_HL2_H_START_END 0x1e35716#define VIU2_OSD2_HL2_V_START_END 0x1e36717#define VIU2_OSD2_TCOLOR_AG0 0x1e37718#define VIU2_OSD2_TCOLOR_AG1 0x1e38719#define VIU2_OSD2_TCOLOR_AG2 0x1e39720#define VIU2_OSD2_TCOLOR_AG3 0x1e3a721#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b722#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f723#define VIU2_OSD2_BLK2_CFG_W0 0x1e43724#define VIU2_OSD2_BLK3_CFG_W0 0x1e47725#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c726#define VIU2_OSD2_BLK1_CFG_W1 0x1e40727#define VIU2_OSD2_BLK2_CFG_W1 0x1e44728#define VIU2_OSD2_BLK3_CFG_W1 0x1e48729#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d730#define VIU2_OSD2_BLK1_CFG_W2 0x1e41731#define VIU2_OSD2_BLK2_CFG_W2 0x1e45732#define VIU2_OSD2_BLK3_CFG_W2 0x1e49733#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e734#define VIU2_OSD2_BLK1_CFG_W3 0x1e42735#define VIU2_OSD2_BLK2_CFG_W3 0x1e46736#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a737#define VIU2_OSD2_BLK0_CFG_W4 0x1e64738#define VIU2_OSD2_BLK1_CFG_W4 0x1e65739#define VIU2_OSD2_BLK2_CFG_W4 0x1e66740#define VIU2_OSD2_BLK3_CFG_W4 0x1e67741#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b742#define VIU2_OSD2_TEST_RDDATA 0x1e4c743#define VIU2_OSD2_PROT_CTRL 0x1e4e744#define VIU2_VD1_IF0_GEN_REG 0x1e50745#define VIU2_VD1_IF0_CANVAS0 0x1e51746#define VIU2_VD1_IF0_CANVAS1 0x1e52747#define VIU2_VD1_IF0_LUMA_X0 0x1e53748#define VIU2_VD1_IF0_LUMA_Y0 0x1e54749#define VIU2_VD1_IF0_CHROMA_X0 0x1e55750#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56751#define VIU2_VD1_IF0_LUMA_X1 0x1e57752#define VIU2_VD1_IF0_LUMA_Y1 0x1e58753#define VIU2_VD1_IF0_CHROMA_X1 0x1e59754#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a755#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b756#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c757#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d758#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e759#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f760#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60761#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61762#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62763#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63764#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a765#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b766#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c767#define VIU2_VD1_IF0_GEN_REG2 0x1e6d768#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e769#define VIU2_VD1_FMT_CTRL 0x1e68770#define VIU2_VD1_FMT_W 0x1e69771 772/* encode */773#define ENCP_VFIFO2VD_CTL 0x1b58774#define ENCP_VFIFO2VD_PIXEL_START 0x1b59775#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a776#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b777#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c778#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d779#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e780#define VENC_SYNC_ROUTE 0x1b60781#define VENC_VIDEO_EXSRC 0x1b61782#define VENC_DVI_SETTING 0x1b62783#define VENC_C656_CTRL 0x1b63784#define VENC_UPSAMPLE_CTRL0 0x1b64785#define VENC_UPSAMPLE_CTRL1 0x1b65786#define VENC_UPSAMPLE_CTRL2 0x1b66787#define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0)788#define VENC_UPSAMPLE_CTRL_F1_EN BIT(5)789#define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6)790#define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12)791#define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12)792#define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12)793#define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12)794#define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12)795#define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12)796#define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12)797#define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12)798#define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12)799#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12)800#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12)801#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12)802#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12)803#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12)804#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12)805#define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12)806#define TCON_INVERT_CTL 0x1b67807#define VENC_VIDEO_PROG_MODE 0x1b68808#define VENC_ENCI_LINE 0x1b69809#define VENC_ENCI_PIXEL 0x1b6a810#define VENC_ENCP_LINE 0x1b6b811#define VENC_ENCP_PIXEL 0x1b6c812#define VENC_STATA 0x1b6d813#define VENC_INTCTRL 0x1b6e814#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)815#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9)816#define VENC_INTFLAG 0x1b6f817#define VENC_VIDEO_TST_EN 0x1b70818#define VENC_VIDEO_TST_MDSEL 0x1b71819#define VENC_VIDEO_TST_Y 0x1b72820#define VENC_VIDEO_TST_CB 0x1b73821#define VENC_VIDEO_TST_CR 0x1b74822#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75823#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76824#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77825#define VENC_VDAC_DACSEL0 0x1b78826#define VENC_VDAC_SEL_ATV_DMD BIT(5)827#define VENC_VDAC_DACSEL1 0x1b79828#define VENC_VDAC_DACSEL2 0x1b7a829#define VENC_VDAC_DACSEL3 0x1b7b830#define VENC_VDAC_DACSEL4 0x1b7c831#define VENC_VDAC_DACSEL5 0x1b7d832#define VENC_VDAC_SETTING 0x1b7e833#define VENC_VDAC_TST_VAL 0x1b7f834#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0835#define VENC_VDAC_DAC0_OFFSET 0x1bf1836#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2837#define VENC_VDAC_DAC1_OFFSET 0x1bf3838#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4839#define VENC_VDAC_DAC2_OFFSET 0x1bf5840#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6841#define VENC_VDAC_DAC3_OFFSET 0x1bf7842#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8843#define VENC_VDAC_DAC4_OFFSET 0x1bf9844#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa845#define VENC_VDAC_DAC5_OFFSET 0x1bfb846#define VENC_VDAC_FIFO_CTRL 0x1bfc847#define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13)848#define ENCL_TCON_INVERT_CTL 0x1bfd849#define ENCP_VIDEO_EN 0x1b80850#define ENCP_VIDEO_SYNC_MODE 0x1b81851#define ENCP_MACV_EN 0x1b82852#define ENCP_VIDEO_Y_SCL 0x1b83853#define ENCP_VIDEO_PB_SCL 0x1b84854#define ENCP_VIDEO_PR_SCL 0x1b85855#define ENCP_VIDEO_SYNC_SCL 0x1b86856#define ENCP_VIDEO_MACV_SCL 0x1b87857#define ENCP_VIDEO_Y_OFFST 0x1b88858#define ENCP_VIDEO_PB_OFFST 0x1b89859#define ENCP_VIDEO_PR_OFFST 0x1b8a860#define ENCP_VIDEO_SYNC_OFFST 0x1b8b861#define ENCP_VIDEO_MACV_OFFST 0x1b8c862#define ENCP_VIDEO_MODE 0x1b8d863#define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14)864#define ENCP_VIDEO_MODE_ADV 0x1b8e865#define ENCP_DBG_PX_RST 0x1b90866#define ENCP_DBG_LN_RST 0x1b91867#define ENCP_DBG_PX_INT 0x1b92868#define ENCP_DBG_LN_INT 0x1b93869#define ENCP_VIDEO_YFP1_HTIME 0x1b94870#define ENCP_VIDEO_YFP2_HTIME 0x1b95871#define ENCP_VIDEO_YC_DLY 0x1b96872#define ENCP_VIDEO_MAX_PXCNT 0x1b97873#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98874#define ENCP_VIDEO_HSPULS_END 0x1b99875#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a876#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b877#define ENCP_VIDEO_VSPULS_END 0x1b9c878#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d879#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e880#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f881#define ENCP_VIDEO_EQPULS_END 0x1ba0882#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1883#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2884#define ENCP_VIDEO_HAVON_END 0x1ba3885#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4886#define ENCP_VIDEO_VAVON_ELINE 0x1baf887#define ENCP_VIDEO_VAVON_BLINE 0x1ba6888#define ENCP_VIDEO_HSO_BEGIN 0x1ba7889#define ENCP_VIDEO_HSO_END 0x1ba8890#define ENCP_VIDEO_VSO_BEGIN 0x1ba9891#define ENCP_VIDEO_VSO_END 0x1baa892#define ENCP_VIDEO_VSO_BLINE 0x1bab893#define ENCP_VIDEO_VSO_ELINE 0x1bac894#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad895#define ENCP_VIDEO_MAX_LNCNT 0x1bae896#define ENCP_VIDEO_SY_VAL 0x1bb0897#define ENCP_VIDEO_SY2_VAL 0x1bb1898#define ENCP_VIDEO_BLANKY_VAL 0x1bb2899#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3900#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4901#define ENCP_VIDEO_HOFFST 0x1bb5902#define ENCP_VIDEO_VOFFST 0x1bb6903#define ENCP_VIDEO_RGB_CTRL 0x1bb7904#define ENCP_VIDEO_FILT_CTRL 0x1bb8905#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9906#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba907#define ENCP_VIDEO_MATRIX_CB 0x1bbb908#define ENCP_VIDEO_MATRIX_CR 0x1bbc909#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd910#define ENCP_MACV_BLANKY_VAL 0x1bc0911#define ENCP_MACV_MAXY_VAL 0x1bc1912#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2913#define ENCP_MACV_PSSYNC_STRT 0x1bc3914#define ENCP_MACV_AGC_STRT 0x1bc4915#define ENCP_MACV_AGC_END 0x1bc5916#define ENCP_MACV_WAVE_END 0x1bc6917#define ENCP_MACV_STRTLINE 0x1bc7918#define ENCP_MACV_ENDLINE 0x1bc8919#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9920#define ENCP_MACV_TS_CNT_MAX_H 0x1bca921#define ENCP_MACV_TIME_DOWN 0x1bcb922#define ENCP_MACV_TIME_LO 0x1bcc923#define ENCP_MACV_TIME_UP 0x1bcd924#define ENCP_MACV_TIME_RST 0x1bce925#define ENCP_VBI_CTRL 0x1bd0926#define ENCP_VBI_SETTING 0x1bd1927#define ENCP_VBI_BEGIN 0x1bd2928#define ENCP_VBI_WIDTH 0x1bd3929#define ENCP_VBI_HVAL 0x1bd4930#define ENCP_VBI_DATA0 0x1bd5931#define ENCP_VBI_DATA1 0x1bd6932#define C656_HS_ST 0x1be0933#define C656_HS_ED 0x1be1934#define C656_VS_LNST_E 0x1be2935#define C656_VS_LNST_O 0x1be3936#define C656_VS_LNED_E 0x1be4937#define C656_VS_LNED_O 0x1be5938#define C656_FS_LNST 0x1be6939#define C656_FS_LNED 0x1be7940#define ENCI_VIDEO_MODE 0x1b00941#define ENCI_VIDEO_MODE_ADV 0x1b01942#define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3)943#define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2)944#define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4)945#define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4)946#define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4)947#define ENCI_VIDEO_FSC_ADJ 0x1b02948#define ENCI_VIDEO_BRIGHT 0x1b03949#define ENCI_VIDEO_CONT 0x1b04950#define ENCI_VIDEO_SAT 0x1b05951#define ENCI_VIDEO_HUE 0x1b06952#define ENCI_VIDEO_SCH 0x1b07953#define ENCI_SYNC_MODE 0x1b08954#define ENCI_SYNC_CTRL 0x1b09955#define ENCI_SYNC_HSO_BEGIN 0x1b0a956#define ENCI_SYNC_HSO_END 0x1b0b957#define ENCI_SYNC_VSO_EVN 0x1b0c958#define ENCI_SYNC_VSO_ODD 0x1b0d959#define ENCI_SYNC_VSO_EVNLN 0x1b0e960#define ENCI_SYNC_VSO_ODDLN 0x1b0f961#define ENCI_SYNC_HOFFST 0x1b10962#define ENCI_SYNC_VOFFST 0x1b11963#define ENCI_SYNC_ADJ 0x1b12964#define ENCI_RGB_SETTING 0x1b13965#define ENCI_DE_H_BEGIN 0x1b16966#define ENCI_DE_H_END 0x1b17967#define ENCI_DE_V_BEGIN_EVEN 0x1b18968#define ENCI_DE_V_END_EVEN 0x1b19969#define ENCI_DE_V_BEGIN_ODD 0x1b1a970#define ENCI_DE_V_END_ODD 0x1b1b971#define ENCI_VBI_SETTING 0x1b20972#define ENCI_VBI_CCDT_EVN 0x1b21973#define ENCI_VBI_CCDT_ODD 0x1b22974#define ENCI_VBI_CC525_LN 0x1b23975#define ENCI_VBI_CC625_LN 0x1b24976#define ENCI_VBI_WSSDT 0x1b25977#define ENCI_VBI_WSS_LN 0x1b26978#define ENCI_VBI_CGMSDT_L 0x1b27979#define ENCI_VBI_CGMSDT_H 0x1b28980#define ENCI_VBI_CGMS_LN 0x1b29981#define ENCI_VBI_TTX_HTIME 0x1b2a982#define ENCI_VBI_TTX_LN 0x1b2b983#define ENCI_VBI_TTXDT0 0x1b2c984#define ENCI_VBI_TTXDT1 0x1b2d985#define ENCI_VBI_TTXDT2 0x1b2e986#define ENCI_VBI_TTXDT3 0x1b2f987#define ENCI_MACV_N0 0x1b30988#define ENCI_MACV_N1 0x1b31989#define ENCI_MACV_N2 0x1b32990#define ENCI_MACV_N3 0x1b33991#define ENCI_MACV_N4 0x1b34992#define ENCI_MACV_N5 0x1b35993#define ENCI_MACV_N6 0x1b36994#define ENCI_MACV_N7 0x1b37995#define ENCI_MACV_N8 0x1b38996#define ENCI_MACV_N9 0x1b39997#define ENCI_MACV_N10 0x1b3a998#define ENCI_MACV_N11 0x1b3b999#define ENCI_MACV_N12 0x1b3c1000#define ENCI_MACV_N13 0x1b3d1001#define ENCI_MACV_N14 0x1b3e1002#define ENCI_MACV_N15 0x1b3f1003#define ENCI_MACV_N16 0x1b401004#define ENCI_MACV_N17 0x1b411005#define ENCI_MACV_N18 0x1b421006#define ENCI_MACV_N19 0x1b431007#define ENCI_MACV_N20 0x1b441008#define ENCI_MACV_N21 0x1b451009#define ENCI_MACV_N22 0x1b461010#define ENCI_DBG_PX_RST 0x1b481011#define ENCI_DBG_FLDLN_RST 0x1b491012#define ENCI_DBG_PX_INT 0x1b4a1013#define ENCI_DBG_FLDLN_INT 0x1b4b1014#define ENCI_DBG_MAXPX 0x1b4c1015#define ENCI_DBG_MAXLN 0x1b4d1016#define ENCI_MACV_MAX_AMP 0x1b501017#define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15)1018#define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff)1019#define ENCI_MACV_PULSE_LO 0x1b511020#define ENCI_MACV_PULSE_HI 0x1b521021#define ENCI_MACV_BKP_MAX 0x1b531022#define ENCI_CFILT_CTRL 0x1b541023#define ENCI_CFILT_CMPT_SEL_HIGH BIT(1)1024#define ENCI_CFILT7 0x1b551025#define ENCI_YC_DELAY 0x1b561026#define ENCI_VIDEO_EN 0x1b571027#define ENCI_VIDEO_EN_ENABLE BIT(0)1028#define ENCI_DVI_HSO_BEGIN 0x1c001029#define ENCI_DVI_HSO_END 0x1c011030#define ENCI_DVI_VSO_BLINE_EVN 0x1c021031#define ENCI_DVI_VSO_BLINE_ODD 0x1c031032#define ENCI_DVI_VSO_ELINE_EVN 0x1c041033#define ENCI_DVI_VSO_ELINE_ODD 0x1c051034#define ENCI_DVI_VSO_BEGIN_EVN 0x1c061035#define ENCI_DVI_VSO_BEGIN_ODD 0x1c071036#define ENCI_DVI_VSO_END_EVN 0x1c081037#define ENCI_DVI_VSO_END_ODD 0x1c091038#define ENCI_CFILT_CTRL2 0x1c0a1039#define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf)1040#define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4)1041#define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8)1042#define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12)1043#define ENCI_DACSEL_0 0x1c0b1044#define ENCI_DACSEL_1 0x1c0c1045#define ENCP_DACSEL_0 0x1c0d1046#define ENCP_DACSEL_1 0x1c0e1047#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f1048#define ENCI_TST_EN 0x1c101049#define ENCI_TST_MDSEL 0x1c111050#define ENCI_TST_Y 0x1c121051#define ENCI_TST_CB 0x1c131052#define ENCI_TST_CR 0x1c141053#define ENCI_TST_CLRBAR_STRT 0x1c151054#define ENCI_TST_CLRBAR_WIDTH 0x1c161055#define ENCI_TST_VDCNT_STSET 0x1c171056#define ENCI_VFIFO2VD_CTL 0x1c181057#define ENCI_VFIFO2VD_CTL_ENABLE BIT(0)1058#define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8)1059#define ENCI_VFIFO2VD_PIXEL_START 0x1c191060#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a1061#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b1062#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c1063#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d1064#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e1065#define ENCI_VFIFO2VD_CTL2 0x1c1f1066#define ENCT_VFIFO2VD_CTL 0x1c201067#define ENCT_VFIFO2VD_PIXEL_START 0x1c211068#define ENCT_VFIFO2VD_PIXEL_END 0x1c221069#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c231070#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c241071#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c251072#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c261073#define ENCT_VFIFO2VD_CTL2 0x1c271074#define ENCT_TST_EN 0x1c281075#define ENCT_TST_MDSEL 0x1c291076#define ENCT_TST_Y 0x1c2a1077#define ENCT_TST_CB 0x1c2b1078#define ENCT_TST_CR 0x1c2c1079#define ENCT_TST_CLRBAR_STRT 0x1c2d1080#define ENCT_TST_CLRBAR_WIDTH 0x1c2e1081#define ENCT_TST_VDCNT_STSET 0x1c2f1082#define ENCP_DVI_HSO_BEGIN 0x1c301083#define ENCP_DVI_HSO_END 0x1c311084#define ENCP_DVI_VSO_BLINE_EVN 0x1c321085#define ENCP_DVI_VSO_BLINE_ODD 0x1c331086#define ENCP_DVI_VSO_ELINE_EVN 0x1c341087#define ENCP_DVI_VSO_ELINE_ODD 0x1c351088#define ENCP_DVI_VSO_BEGIN_EVN 0x1c361089#define ENCP_DVI_VSO_BEGIN_ODD 0x1c371090#define ENCP_DVI_VSO_END_EVN 0x1c381091#define ENCP_DVI_VSO_END_ODD 0x1c391092#define ENCP_DE_H_BEGIN 0x1c3a1093#define ENCP_DE_H_END 0x1c3b1094#define ENCP_DE_V_BEGIN_EVEN 0x1c3c1095#define ENCP_DE_V_END_EVEN 0x1c3d1096#define ENCP_DE_V_BEGIN_ODD 0x1c3e1097#define ENCP_DE_V_END_ODD 0x1c3f1098#define ENCI_SYNC_LINE_LENGTH 0x1c401099#define ENCI_SYNC_PIXEL_EN 0x1c411100#define ENCI_SYNC_TO_LINE_EN 0x1c421101#define ENCI_SYNC_TO_PIXEL 0x1c431102#define ENCP_SYNC_LINE_LENGTH 0x1c441103#define ENCP_SYNC_PIXEL_EN 0x1c451104#define ENCP_SYNC_TO_LINE_EN 0x1c461105#define ENCP_SYNC_TO_PIXEL 0x1c471106#define ENCT_SYNC_LINE_LENGTH 0x1c481107#define ENCT_SYNC_PIXEL_EN 0x1c491108#define ENCT_SYNC_TO_LINE_EN 0x1c4a1109#define ENCT_SYNC_TO_PIXEL 0x1c4b1110#define ENCL_SYNC_LINE_LENGTH 0x1c4c1111#define ENCL_SYNC_PIXEL_EN 0x1c4d1112#define ENCL_SYNC_TO_LINE_EN 0x1c4e1113#define ENCL_SYNC_TO_PIXEL 0x1c4f1114#define ENCP_VFIFO2VD_CTL2 0x1c501115#define VENC_DVI_SETTING_MORE 0x1c511116#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c541117#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c551118#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c561119#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c571120#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c581121#define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0)1122#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c591123#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a1124#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b1125#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c1126#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d1127#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e1128#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f1129#define ENCT_VIDEO_EN 0x1c601130#define ENCT_VIDEO_Y_SCL 0x1c611131#define ENCT_VIDEO_PB_SCL 0x1c621132#define ENCT_VIDEO_PR_SCL 0x1c631133#define ENCT_VIDEO_Y_OFFST 0x1c641134#define ENCT_VIDEO_PB_OFFST 0x1c651135#define ENCT_VIDEO_PR_OFFST 0x1c661136#define ENCT_VIDEO_MODE 0x1c671137#define ENCT_VIDEO_MODE_ADV 0x1c681138#define ENCT_DBG_PX_RST 0x1c691139#define ENCT_DBG_LN_RST 0x1c6a1140#define ENCT_DBG_PX_INT 0x1c6b1141#define ENCT_DBG_LN_INT 0x1c6c1142#define ENCT_VIDEO_YFP1_HTIME 0x1c6d1143#define ENCT_VIDEO_YFP2_HTIME 0x1c6e1144#define ENCT_VIDEO_YC_DLY 0x1c6f1145#define ENCT_VIDEO_MAX_PXCNT 0x1c701146#define ENCT_VIDEO_HAVON_END 0x1c711147#define ENCT_VIDEO_HAVON_BEGIN 0x1c721148#define ENCT_VIDEO_VAVON_ELINE 0x1c731149#define ENCT_VIDEO_VAVON_BLINE 0x1c741150#define ENCT_VIDEO_HSO_BEGIN 0x1c751151#define ENCT_VIDEO_HSO_END 0x1c761152#define ENCT_VIDEO_VSO_BEGIN 0x1c771153#define ENCT_VIDEO_VSO_END 0x1c781154#define ENCT_VIDEO_VSO_BLINE 0x1c791155#define ENCT_VIDEO_VSO_ELINE 0x1c7a1156#define ENCT_VIDEO_MAX_LNCNT 0x1c7b1157#define ENCT_VIDEO_BLANKY_VAL 0x1c7c1158#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d1159#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e1160#define ENCT_VIDEO_HOFFST 0x1c7f1161#define ENCT_VIDEO_VOFFST 0x1c801162#define ENCT_VIDEO_RGB_CTRL 0x1c811163#define ENCT_VIDEO_FILT_CTRL 0x1c821164#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c831165#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c841166#define ENCT_VIDEO_MATRIX_CB 0x1c851167#define ENCT_VIDEO_MATRIX_CR 0x1c861168#define ENCT_VIDEO_RGBIN_CTRL 0x1c871169#define ENCT_MAX_LINE_SWITCH_POINT 0x1c881170#define ENCT_DACSEL_0 0x1c891171#define ENCT_DACSEL_1 0x1c8a1172#define ENCL_VFIFO2VD_CTL 0x1c901173#define ENCL_VFIFO2VD_PIXEL_START 0x1c911174#define ENCL_VFIFO2VD_PIXEL_END 0x1c921175#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c931176#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c941177#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c951178#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c961179#define ENCL_VFIFO2VD_CTL2 0x1c971180#define ENCL_TST_EN 0x1c981181#define ENCL_TST_MDSEL 0x1c991182#define ENCL_TST_Y 0x1c9a1183#define ENCL_TST_CB 0x1c9b1184#define ENCL_TST_CR 0x1c9c1185#define ENCL_TST_CLRBAR_STRT 0x1c9d1186#define ENCL_TST_CLRBAR_WIDTH 0x1c9e1187#define ENCL_TST_VDCNT_STSET 0x1c9f1188#define ENCL_VIDEO_EN 0x1ca01189#define ENCL_VIDEO_Y_SCL 0x1ca11190#define ENCL_VIDEO_PB_SCL 0x1ca21191#define ENCL_VIDEO_PR_SCL 0x1ca31192#define ENCL_VIDEO_Y_OFFST 0x1ca41193#define ENCL_VIDEO_PB_OFFST 0x1ca51194#define ENCL_VIDEO_PR_OFFST 0x1ca61195#define ENCL_VIDEO_MODE 0x1ca71196#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15)1197#define ENCL_VIDEO_MODE_ADV 0x1ca81198#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3)1199#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4)1200#define ENCL_SEL_GAMMA_RGB_IN BIT(10)1201#define ENCL_DBG_PX_RST 0x1ca91202#define ENCL_DBG_LN_RST 0x1caa1203#define ENCL_DBG_PX_INT 0x1cab1204#define ENCL_DBG_LN_INT 0x1cac1205#define ENCL_VIDEO_YFP1_HTIME 0x1cad1206#define ENCL_VIDEO_YFP2_HTIME 0x1cae1207#define ENCL_VIDEO_YC_DLY 0x1caf1208#define ENCL_VIDEO_MAX_PXCNT 0x1cb01209#define ENCL_VIDEO_HAVON_END 0x1cb11210#define ENCL_VIDEO_HAVON_BEGIN 0x1cb21211#define ENCL_VIDEO_VAVON_ELINE 0x1cb31212#define ENCL_VIDEO_VAVON_BLINE 0x1cb41213#define ENCL_VIDEO_HSO_BEGIN 0x1cb51214#define ENCL_VIDEO_HSO_END 0x1cb61215#define ENCL_VIDEO_VSO_BEGIN 0x1cb71216#define ENCL_VIDEO_VSO_END 0x1cb81217#define ENCL_VIDEO_VSO_BLINE 0x1cb91218#define ENCL_VIDEO_VSO_ELINE 0x1cba1219#define ENCL_VIDEO_MAX_LNCNT 0x1cbb1220#define ENCL_VIDEO_BLANKY_VAL 0x1cbc1221#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd1222#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe1223#define ENCL_VIDEO_HOFFST 0x1cbf1224#define ENCL_VIDEO_VOFFST 0x1cc01225#define ENCL_VIDEO_RGB_CTRL 0x1cc11226#define ENCL_VIDEO_FILT_CTRL 0x1cc21227#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12)1228#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc31229#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc41230#define ENCL_VIDEO_MATRIX_CB 0x1cc51231#define ENCL_VIDEO_MATRIX_CR 0x1cc61232#define ENCL_VIDEO_RGBIN_CTRL 0x1cc71233#define ENCL_VIDEO_RGBIN_RGB BIT(0)1234#define ENCL_VIDEO_RGBIN_ZBLK BIT(1)1235#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc81236#define ENCL_DACSEL_0 0x1cc91237#define ENCL_DACSEL_1 0x1cca1238#define RDMA_AHB_START_ADDR_MAN 0x11001239#define RDMA_AHB_END_ADDR_MAN 0x11011240#define RDMA_AHB_START_ADDR_1 0x11021241#define RDMA_AHB_END_ADDR_1 0x11031242#define RDMA_AHB_START_ADDR_2 0x11041243#define RDMA_AHB_END_ADDR_2 0x11051244#define RDMA_AHB_START_ADDR_3 0x11061245#define RDMA_AHB_END_ADDR_3 0x11071246#define RDMA_AHB_START_ADDR_4 0x11081247#define RDMA_AHB_END_ADDR_4 0x11091248#define RDMA_AHB_START_ADDR_5 0x110a1249#define RDMA_AHB_END_ADDR_5 0x110b1250#define RDMA_AHB_START_ADDR_6 0x110c1251#define RDMA_AHB_END_ADDR_6 0x110d1252#define RDMA_AHB_START_ADDR_7 0x110e1253#define RDMA_AHB_END_ADDR_7 0x110f1254#define RDMA_ACCESS_AUTO 0x11101255#define RDMA_ACCESS_TRIGGER_CHAN3 GENMASK(31, 24)1256#define RDMA_ACCESS_TRIGGER_CHAN2 GENMASK(23, 16)1257#define RDMA_ACCESS_TRIGGER_CHAN1 GENMASK(15, 8)1258#define RDMA_ACCESS_TRIGGER_STOP 01259#define RDMA_ACCESS_TRIGGER_VSYNC 11260#define RDMA_ACCESS_TRIGGER_LINE 321261#define RDMA_ACCESS_RW_FLAG_CHAN3 BIT(7)1262#define RDMA_ACCESS_RW_FLAG_CHAN2 BIT(6)1263#define RDMA_ACCESS_RW_FLAG_CHAN1 BIT(5)1264#define RDMA_ACCESS_ADDR_INC_CHAN3 BIT(3)1265#define RDMA_ACCESS_ADDR_INC_CHAN2 BIT(2)1266#define RDMA_ACCESS_ADDR_INC_CHAN1 BIT(1)1267#define RDMA_ACCESS_AUTO2 0x11111268#define RDMA_ACCESS_RW_FLAG_CHAN7 BIT(7)1269#define RDMA_ACCESS_RW_FLAG_CHAN6 BIT(6)1270#define RDMA_ACCESS_RW_FLAG_CHAN5 BIT(5)1271#define RDMA_ACCESS_RW_FLAG_CHAN4 BIT(4)1272#define RDMA_ACCESS_ADDR_INC_CHAN7 BIT(3)1273#define RDMA_ACCESS_ADDR_INC_CHAN6 BIT(2)1274#define RDMA_ACCESS_ADDR_INC_CHAN5 BIT(1)1275#define RDMA_ACCESS_ADDR_INC_CHAN4 BIT(0)1276#define RDMA_ACCESS_AUTO3 0x11121277#define RDMA_ACCESS_TRIGGER_CHAN7 GENMASK(31, 24)1278#define RDMA_ACCESS_TRIGGER_CHAN6 GENMASK(23, 16)1279#define RDMA_ACCESS_TRIGGER_CHAN5 GENMASK(15, 8)1280#define RDMA_ACCESS_TRIGGER_CHAN4 GENMASK(7, 0)1281#define RDMA_ACCESS_MAN 0x11131282#define RDMA_ACCESS_MAN_RW_FLAG BIT(2)1283#define RDMA_ACCESS_MAN_ADDR_INC BIT(1)1284#define RDMA_ACCESS_MAN_START BIT(0)1285#define RDMA_CTRL 0x11141286#define RDMA_IRQ_CLEAR_CHAN7 BIT(31)1287#define RDMA_IRQ_CLEAR_CHAN6 BIT(30)1288#define RDMA_IRQ_CLEAR_CHAN5 BIT(29)1289#define RDMA_IRQ_CLEAR_CHAN4 BIT(28)1290#define RDMA_IRQ_CLEAR_CHAN3 BIT(27)1291#define RDMA_IRQ_CLEAR_CHAN2 BIT(26)1292#define RDMA_IRQ_CLEAR_CHAN1 BIT(25)1293#define RDMA_IRQ_CLEAR_CHAN_MAN BIT(24)1294#define RDMA_DEFAULT_CONFIG (BIT(7) | BIT(6))1295#define RDMA_CTRL_AHB_WR_BURST GENMASK(5, 4)1296#define RDMA_CTRL_AHB_RD_BURST GENMASK(3, 2)1297#define RDMA_CTRL_SW_RESET BIT(1)1298#define RDMA_CTRL_FREE_CLK_EN BIT(0)1299#define RDMA_STATUS 0x11151300#define RDMA_IRQ_STAT_CHAN7 BIT(31)1301#define RDMA_IRQ_STAT_CHAN6 BIT(30)1302#define RDMA_IRQ_STAT_CHAN5 BIT(29)1303#define RDMA_IRQ_STAT_CHAN4 BIT(28)1304#define RDMA_IRQ_STAT_CHAN3 BIT(27)1305#define RDMA_IRQ_STAT_CHAN2 BIT(26)1306#define RDMA_IRQ_STAT_CHAN1 BIT(25)1307#define RDMA_IRQ_STAT_CHAN_MAN BIT(24)1308#define RDMA_STATUS2 0x11161309#define RDMA_STATUS3 0x11171310#define L_GAMMA_CNTL_PORT 0x14001311#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */1312#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */1313#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */1314#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */1315#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */1316#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */1317#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */1318#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */1319#define L_GAMMA_DATA_PORT 0x14011320#define L_GAMMA_ADDR_PORT 0x14021321#define L_GAMMA_ADDR_PORT_RD BIT(12)1322#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11)1323#define L_GAMMA_ADDR_PORT_SEL_R BIT(10)1324#define L_GAMMA_ADDR_PORT_SEL_G BIT(9)1325#define L_GAMMA_ADDR_PORT_SEL_B BIT(8)1326#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0)1327#define L_GAMMA_VCOM_HSWITCH_ADDR 0x14031328#define L_RGB_BASE_ADDR 0x14051329#define L_RGB_COEFF_ADDR 0x14061330#define L_POL_CNTL_ADDR 0x14071331#define L_DITH_CNTL_ADDR 0x14081332#define L_DITH_CNTL_DITH10_EN BIT(10)1333#define L_GAMMA_PROBE_CTRL 0x14091334#define L_GAMMA_PROBE_COLOR_L 0x140a1335#define L_GAMMA_PROBE_COLOR_H 0x140b1336#define L_GAMMA_PROBE_HL_COLOR 0x140c1337#define L_GAMMA_PROBE_POS_X 0x140d1338#define L_GAMMA_PROBE_POS_Y 0x140e1339#define L_STH1_HS_ADDR 0x14101340#define L_STH1_HE_ADDR 0x14111341#define L_STH1_VS_ADDR 0x14121342#define L_STH1_VE_ADDR 0x14131343#define L_STH2_HS_ADDR 0x14141344#define L_STH2_HE_ADDR 0x14151345#define L_STH2_VS_ADDR 0x14161346#define L_STH2_VE_ADDR 0x14171347#define L_OEH_HS_ADDR 0x14181348#define L_OEH_HE_ADDR 0x14191349#define L_OEH_VS_ADDR 0x141a1350#define L_OEH_VE_ADDR 0x141b1351#define L_VCOM_HSWITCH_ADDR 0x141c1352#define L_VCOM_VS_ADDR 0x141d1353#define L_VCOM_VE_ADDR 0x141e1354#define L_CPV1_HS_ADDR 0x141f1355#define L_CPV1_HE_ADDR 0x14201356#define L_CPV1_VS_ADDR 0x14211357#define L_CPV1_VE_ADDR 0x14221358#define L_CPV2_HS_ADDR 0x14231359#define L_CPV2_HE_ADDR 0x14241360#define L_CPV2_VS_ADDR 0x14251361#define L_CPV2_VE_ADDR 0x14261362#define L_STV1_HS_ADDR 0x14271363#define L_STV1_HE_ADDR 0x14281364#define L_STV1_VS_ADDR 0x14291365#define L_STV1_VE_ADDR 0x142a1366#define L_STV2_HS_ADDR 0x142b1367#define L_STV2_HE_ADDR 0x142c1368#define L_STV2_VS_ADDR 0x142d1369#define L_STV2_VE_ADDR 0x142e1370#define L_OEV1_HS_ADDR 0x142f1371#define L_OEV1_HE_ADDR 0x14301372#define L_OEV1_VS_ADDR 0x14311373#define L_OEV1_VE_ADDR 0x14321374#define L_OEV2_HS_ADDR 0x14331375#define L_OEV2_HE_ADDR 0x14341376#define L_OEV2_VS_ADDR 0x14351377#define L_OEV2_VE_ADDR 0x14361378#define L_OEV3_HS_ADDR 0x14371379#define L_OEV3_HE_ADDR 0x14381380#define L_OEV3_VS_ADDR 0x14391381#define L_OEV3_VE_ADDR 0x143a1382#define L_LCD_PWR_ADDR 0x143b1383#define L_LCD_PWM0_LO_ADDR 0x143c1384#define L_LCD_PWM0_HI_ADDR 0x143d1385#define L_LCD_PWM1_LO_ADDR 0x143e1386#define L_LCD_PWM1_HI_ADDR 0x143f1387#define L_INV_CNT_ADDR 0x14401388#define L_TCON_MISC_SEL_ADDR 0x14411389#define L_TCON_MISC_SEL_STV1 BIT(4)1390#define L_TCON_MISC_SEL_STV2 BIT(5)1391#define L_DUAL_PORT_CNTL_ADDR 0x14421392#define MLVDS_CLK_CTL1_HI 0x14431393#define MLVDS_CLK_CTL1_LO 0x14441394#define L_TCON_DOUBLE_CTL 0x14491395#define L_TCON_PATTERN_HI 0x144a1396#define L_TCON_PATTERN_LO 0x144b1397#define LDIM_BL_ADDR_PORT 0x144e1398#define LDIM_BL_DATA_PORT 0x144f1399#define L_DE_HS_ADDR 0x14511400#define L_DE_HE_ADDR 0x14521401#define L_DE_VS_ADDR 0x14531402#define L_DE_VE_ADDR 0x14541403#define L_HSYNC_HS_ADDR 0x14551404#define L_HSYNC_HE_ADDR 0x14561405#define L_HSYNC_VS_ADDR 0x14571406#define L_HSYNC_VE_ADDR 0x14581407#define L_VSYNC_HS_ADDR 0x14591408#define L_VSYNC_HE_ADDR 0x145a1409#define L_VSYNC_VS_ADDR 0x145b1410#define L_VSYNC_VE_ADDR 0x145c1411#define L_LCD_MCU_CTL 0x145d1412#define DUAL_MLVDS_CTL 0x14601413#define DUAL_MLVDS_LINE_START 0x14611414#define DUAL_MLVDS_LINE_END 0x14621415#define DUAL_MLVDS_PIXEL_W_START_L 0x14631416#define DUAL_MLVDS_PIXEL_W_END_L 0x14641417#define DUAL_MLVDS_PIXEL_W_START_R 0x14651418#define DUAL_MLVDS_PIXEL_W_END_R 0x14661419#define DUAL_MLVDS_PIXEL_R_START_L 0x14671420#define DUAL_MLVDS_PIXEL_R_CNT_L 0x14681421#define DUAL_MLVDS_PIXEL_R_START_R 0x14691422#define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a1423#define V_INVERSION_PIXEL 0x14701424#define V_INVERSION_LINE 0x14711425#define V_INVERSION_CONTROL 0x14721426#define MLVDS2_CONTROL 0x14741427#define MLVDS2_CONFIG_HI 0x14751428#define MLVDS2_CONFIG_LO 0x14761429#define MLVDS2_DUAL_GATE_WR_START 0x14771430#define MLVDS2_DUAL_GATE_WR_END 0x14781431#define MLVDS2_DUAL_GATE_RD_START 0x14791432#define MLVDS2_DUAL_GATE_RD_END 0x147a1433#define MLVDS2_SECOND_RESET_CTL 0x147b1434#define MLVDS2_DUAL_GATE_CTL_HI 0x147c1435#define MLVDS2_DUAL_GATE_CTL_LO 0x147d1436#define MLVDS2_RESET_CONFIG_HI 0x147e1437#define MLVDS2_RESET_CONFIG_LO 0x147f1438#define GAMMA_CNTL_PORT 0x14801439#define GAMMA_DATA_PORT 0x14811440#define GAMMA_ADDR_PORT 0x14821441#define GAMMA_VCOM_HSWITCH_ADDR 0x14831442#define RGB_BASE_ADDR 0x14851443#define RGB_COEFF_ADDR 0x14861444#define POL_CNTL_ADDR 0x14871445#define DITH_CNTL_ADDR 0x14881446#define GAMMA_PROBE_CTRL 0x14891447#define GAMMA_PROBE_COLOR_L 0x148a1448#define GAMMA_PROBE_COLOR_H 0x148b1449#define GAMMA_PROBE_HL_COLOR 0x148c1450#define GAMMA_PROBE_POS_X 0x148d1451#define GAMMA_PROBE_POS_Y 0x148e1452#define STH1_HS_ADDR 0x14901453#define STH1_HE_ADDR 0x14911454#define STH1_VS_ADDR 0x14921455#define STH1_VE_ADDR 0x14931456#define STH2_HS_ADDR 0x14941457#define STH2_HE_ADDR 0x14951458#define STH2_VS_ADDR 0x14961459#define STH2_VE_ADDR 0x14971460#define OEH_HS_ADDR 0x14981461#define OEH_HE_ADDR 0x14991462#define OEH_VS_ADDR 0x149a1463#define OEH_VE_ADDR 0x149b1464#define VCOM_HSWITCH_ADDR 0x149c1465#define VCOM_VS_ADDR 0x149d1466#define VCOM_VE_ADDR 0x149e1467#define CPV1_HS_ADDR 0x149f1468#define CPV1_HE_ADDR 0x14a01469#define CPV1_VS_ADDR 0x14a11470#define CPV1_VE_ADDR 0x14a21471#define CPV2_HS_ADDR 0x14a31472#define CPV2_HE_ADDR 0x14a41473#define CPV2_VS_ADDR 0x14a51474#define CPV2_VE_ADDR 0x14a61475#define STV1_HS_ADDR 0x14a71476#define STV1_HE_ADDR 0x14a81477#define STV1_VS_ADDR 0x14a91478#define STV1_VE_ADDR 0x14aa1479#define STV2_HS_ADDR 0x14ab1480#define STV2_HE_ADDR 0x14ac1481#define STV2_VS_ADDR 0x14ad1482#define STV2_VE_ADDR 0x14ae1483#define OEV1_HS_ADDR 0x14af1484#define OEV1_HE_ADDR 0x14b01485#define OEV1_VS_ADDR 0x14b11486#define OEV1_VE_ADDR 0x14b21487#define OEV2_HS_ADDR 0x14b31488#define OEV2_HE_ADDR 0x14b41489#define OEV2_VS_ADDR 0x14b51490#define OEV2_VE_ADDR 0x14b61491#define OEV3_HS_ADDR 0x14b71492#define OEV3_HE_ADDR 0x14b81493#define OEV3_VS_ADDR 0x14b91494#define OEV3_VE_ADDR 0x14ba1495#define LCD_PWR_ADDR 0x14bb1496#define LCD_PWM0_LO_ADDR 0x14bc1497#define LCD_PWM0_HI_ADDR 0x14bd1498#define LCD_PWM1_LO_ADDR 0x14be1499#define LCD_PWM1_HI_ADDR 0x14bf1500#define INV_CNT_ADDR 0x14c01501#define TCON_MISC_SEL_ADDR 0x14c11502#define DUAL_PORT_CNTL_ADDR 0x14c21503#define MLVDS_CONTROL 0x14c31504#define MLVDS_RESET_PATTERN_HI 0x14c41505#define MLVDS_RESET_PATTERN_LO 0x14c51506#define MLVDS_RESET_PATTERN_EXT 0x14c61507#define MLVDS_CONFIG_HI 0x14c71508#define MLVDS_CONFIG_LO 0x14c81509#define TCON_DOUBLE_CTL 0x14c91510#define TCON_PATTERN_HI 0x14ca1511#define TCON_PATTERN_LO 0x14cb1512#define TCON_CONTROL_HI 0x14cc1513#define TCON_CONTROL_LO 0x14cd1514#define LVDS_BLANK_DATA_HI 0x14ce1515#define LVDS_BLANK_DATA_LO 0x14cf1516#define LVDS_PACK_CNTL_ADDR 0x14d01517#define DE_HS_ADDR 0x14d11518#define DE_HE_ADDR 0x14d21519#define DE_VS_ADDR 0x14d31520#define DE_VE_ADDR 0x14d41521#define HSYNC_HS_ADDR 0x14d51522#define HSYNC_HE_ADDR 0x14d61523#define HSYNC_VS_ADDR 0x14d71524#define HSYNC_VE_ADDR 0x14d81525#define VSYNC_HS_ADDR 0x14d91526#define VSYNC_HE_ADDR 0x14da1527#define VSYNC_VS_ADDR 0x14db1528#define VSYNC_VE_ADDR 0x14dc1529#define LCD_MCU_CTL 0x14dd1530#define LCD_MCU_DATA_0 0x14de1531#define LCD_MCU_DATA_1 0x14df1532#define LVDS_GEN_CNTL 0x14e01533#define LVDS_PHY_CNTL0 0x14e11534#define LVDS_PHY_CNTL1 0x14e21535#define LVDS_PHY_CNTL2 0x14e31536#define LVDS_PHY_CNTL3 0x14e41537#define LVDS_PHY_CNTL4 0x14e51538#define LVDS_PHY_CNTL5 0x14e61539#define LVDS_SRG_TEST 0x14e81540#define LVDS_BIST_MUX0 0x14e91541#define LVDS_BIST_MUX1 0x14ea1542#define LVDS_BIST_FIXED0 0x14eb1543#define LVDS_BIST_FIXED1 0x14ec1544#define LVDS_BIST_CNTL0 0x14ed1545#define LVDS_CLKB_CLKA 0x14ee1546#define LVDS_PHY_CLK_CNTL 0x14ef1547#define LVDS_SER_EN 0x14f01548#define LVDS_PHY_CNTL6 0x14f11549#define LVDS_PHY_CNTL7 0x14f21550#define LVDS_PHY_CNTL8 0x14f31551#define MLVDS_CLK_CTL0_HI 0x14f41552#define MLVDS_CLK_CTL0_LO 0x14f51553#define MLVDS_DUAL_GATE_WR_START 0x14f61554#define MLVDS_DUAL_GATE_WR_END 0x14f71555#define MLVDS_DUAL_GATE_RD_START 0x14f81556#define MLVDS_DUAL_GATE_RD_END 0x14f91557#define MLVDS_SECOND_RESET_CTL 0x14fa1558#define MLVDS_DUAL_GATE_CTL_HI 0x14fb1559#define MLVDS_DUAL_GATE_CTL_LO 0x14fc1560#define MLVDS_RESET_CONFIG_HI 0x14fd1561#define MLVDS_RESET_CONFIG_LO 0x14fe1562#define VPU_OSD1_MMC_CTRL 0x27011563#define VPU_OSD2_MMC_CTRL 0x27021564#define VPU_VD1_MMC_CTRL 0x27031565#define VPU_VD2_MMC_CTRL 0x27041566#define VPU_DI_IF1_MMC_CTRL 0x27051567#define VPU_DI_MEM_MMC_CTRL 0x27061568#define VPU_DI_INP_MMC_CTRL 0x27071569#define VPU_DI_MTNRD_MMC_CTRL 0x27081570#define VPU_DI_CHAN2_MMC_CTRL 0x27091571#define VPU_DI_MTNWR_MMC_CTRL 0x270a1572#define VPU_DI_NRWR_MMC_CTRL 0x270b1573#define VPU_DI_DIWR_MMC_CTRL 0x270c1574#define VPU_VDIN0_MMC_CTRL 0x270d1575#define VPU_VDIN1_MMC_CTRL 0x270e1576#define VPU_BT656_MMC_CTRL 0x270f1577#define VPU_TVD3D_MMC_CTRL 0x27101578#define VPU_TVDVBI_MMC_CTRL 0x27111579#define VPU_TVDVBI_VSLATCH_ADDR 0x27121580#define VPU_TVDVBI_WRRSP_ADDR 0x27131581#define VPU_VDIN_PRE_ARB_CTRL 0x27141582#define VPU_VDISP_PRE_ARB_CTRL 0x27151583#define VPU_VPUARB2_PRE_ARB_CTRL 0x27161584#define VPU_OSD3_MMC_CTRL 0x27171585#define VPU_OSD4_MMC_CTRL 0x27181586#define VPU_VD3_MMC_CTRL 0x27191587#define VPU_VIU_VENC_MUX_CTRL 0x271a1588#define VIU1_SEL_VENC_MASK 0x31589#define VIU1_SEL_VENC_ENCL 01590#define VIU1_SEL_VENC_ENCI 11591#define VIU1_SEL_VENC_ENCP 21592#define VIU1_SEL_VENC_ENCT 31593#define VIU2_SEL_VENC_MASK 0xc1594#define VIU2_SEL_VENC_ENCL 01595#define VIU2_SEL_VENC_ENCI (1 << 2)1596#define VIU2_SEL_VENC_ENCP (2 << 2)1597#define VIU2_SEL_VENC_ENCT (3 << 2)1598#define VPU_HDMI_SETTING 0x271b1599#define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0)1600#define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1)1601#define VPU_HDMI_INV_HSYNC BIT(2)1602#define VPU_HDMI_INV_VSYNC BIT(3)1603#define VPU_HDMI_OUTPUT_CRYCB (0 << 5)1604#define VPU_HDMI_OUTPUT_YCBCR (1 << 5)1605#define VPU_HDMI_OUTPUT_YCRCB (2 << 5)1606#define VPU_HDMI_OUTPUT_CBCRY (3 << 5)1607#define VPU_HDMI_OUTPUT_CBYCR (4 << 5)1608#define VPU_HDMI_OUTPUT_CRCBY (5 << 5)1609#define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8)1610#define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12)1611#define ENCI_INFO_READ 0x271c1612#define ENCP_INFO_READ 0x271d1613#define ENCT_INFO_READ 0x271e1614#define ENCL_INFO_READ 0x271f1615#define VPU_SW_RESET 0x27201616#define VPU_D2D3_MMC_CTRL 0x27211617#define VPU_CONT_MMC_CTRL 0x27221618#define VPU_CLK_GATE 0x27231619#define VPU_RDMA_MMC_CTRL 0x27241620#define VPU_MEM_PD_REG0 0x27251621#define VPU_MEM_PD_REG1 0x27261622#define VPU_HDMI_DATA_OVR 0x27271623#define VPU_PROT1_MMC_CTRL 0x27281624#define VPU_PROT2_MMC_CTRL 0x27291625#define VPU_PROT3_MMC_CTRL 0x272a1626#define VPU_ARB4_V1_MMC_CTRL 0x272b1627#define VPU_ARB4_V2_MMC_CTRL 0x272c1628#define VPU_VPU_PWM_V0 0x27301629#define VPU_VPU_PWM_V1 0x27311630#define VPU_VPU_PWM_V2 0x27321631#define VPU_VPU_PWM_V3 0x27331632#define VPU_VPU_PWM_H0 0x27341633#define VPU_VPU_PWM_H1 0x27351634#define VPU_VPU_PWM_H2 0x27361635#define VPU_VPU_PWM_H3 0x27371636#define VPU_MISC_CTRL 0x27401637#define VPU_ISP_GCLK_CTRL0 0x27411638#define VPU_ISP_GCLK_CTRL1 0x27421639#define VPU_HDMI_FMT_CTRL 0x27431640#define VPU_VDIN_ASYNC_HOLD_CTRL 0x27431641#define VPU_VDISP_ASYNC_HOLD_CTRL 0x27441642#define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x27451643 1644#define VPU_PROT1_CLK_GATE 0x27501645#define VPU_PROT1_GEN_CNTL 0x27511646#define VPU_PROT1_X_START_END 0x27521647#define VPU_PROT1_Y_START_END 0x27531648#define VPU_PROT1_Y_LEN_STEP 0x27541649#define VPU_PROT1_RPT_LOOP 0x27551650#define VPU_PROT1_RPT_PAT 0x27561651#define VPU_PROT1_DDR 0x27571652#define VPU_PROT1_RBUF_ROOM 0x27581653#define VPU_PROT1_STAT_0 0x27591654#define VPU_PROT1_STAT_1 0x275a1655#define VPU_PROT1_STAT_2 0x275b1656#define VPU_PROT1_REQ_ONOFF 0x275c1657#define VPU_PROT2_CLK_GATE 0x27601658#define VPU_PROT2_GEN_CNTL 0x27611659#define VPU_PROT2_X_START_END 0x27621660#define VPU_PROT2_Y_START_END 0x27631661#define VPU_PROT2_Y_LEN_STEP 0x27641662#define VPU_PROT2_RPT_LOOP 0x27651663#define VPU_PROT2_RPT_PAT 0x27661664#define VPU_PROT2_DDR 0x27671665#define VPU_PROT2_RBUF_ROOM 0x27681666#define VPU_PROT2_STAT_0 0x27691667#define VPU_PROT2_STAT_1 0x276a1668#define VPU_PROT2_STAT_2 0x276b1669#define VPU_PROT2_REQ_ONOFF 0x276c1670#define VPU_PROT3_CLK_GATE 0x27701671#define VPU_PROT3_GEN_CNTL 0x27711672#define VPU_PROT3_X_START_END 0x27721673#define VPU_PROT3_Y_START_END 0x27731674#define VPU_PROT3_Y_LEN_STEP 0x27741675#define VPU_PROT3_RPT_LOOP 0x27751676#define VPU_PROT3_RPT_PAT 0x27761677#define VPU_PROT3_DDR 0x27771678#define VPU_PROT3_RBUF_ROOM 0x27781679#define VPU_PROT3_STAT_0 0x27791680#define VPU_PROT3_STAT_1 0x277a1681#define VPU_PROT3_STAT_2 0x277b1682#define VPU_PROT3_REQ_ONOFF 0x277c1683#define VPU_RDARB_MODE_L1C1 0x27901684#define VPU_RDARB_MODE_L1C2 0x27991685#define VPU_RDARB_MODE_L2C1 0x279d1686#define VPU_WRARB_MODE_L2C1 0x27a21687#define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc))1688 1689/* osd super scale */1690#define OSDSR_HV_SIZEIN 0x31301691#define OSDSR_CTRL_MODE 0x31311692#define OSDSR_ABIC_HCOEF 0x31321693#define OSDSR_YBIC_HCOEF 0x31331694#define OSDSR_CBIC_HCOEF 0x31341695#define OSDSR_ABIC_VCOEF 0x31351696#define OSDSR_YBIC_VCOEF 0x31361697#define OSDSR_CBIC_VCOEF 0x31371698#define OSDSR_VAR_PARA 0x31381699#define OSDSR_CONST_PARA 0x31391700#define OSDSR_RKE_EXTWIN 0x313a1701#define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b1702#define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c1703#define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d1704#define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e1705#define OSDSR_UK_BST_GAIN 0x313f1706#define OSDSR_HVBLEND_TH 0x31401707#define OSDSR_DEMO_WIND_TB 0x31411708#define OSDSR_DEMO_WIND_LR 0x31421709#define OSDSR_INT_BLANK_NUM 0x31431710#define OSDSR_FRM_END_STAT 0x31441711#define OSDSR_ABIC_HCOEF0 0x31451712#define OSDSR_YBIC_HCOEF0 0x31461713#define OSDSR_CBIC_HCOEF0 0x31471714#define OSDSR_ABIC_VCOEF0 0x31481715#define OSDSR_YBIC_VCOEF0 0x31491716#define OSDSR_CBIC_VCOEF0 0x314a1717 1718/* osd afbcd on gxtvbb */1719#define OSD1_AFBCD_ENABLE 0x31a01720#define OSD1_AFBCD_ID_FIFO_THRD GENMASK(15, 9)1721#define OSD1_AFBCD_DEC_ENABLE BIT(8)1722#define OSD1_AFBCD_FRM_START BIT(0)1723#define OSD1_AFBCD_MODE 0x31a11724#define OSD1_AFBCD_SOFT_RESET BIT(31)1725#define OSD1_AFBCD_AXI_REORDER_MODE BIT(28)1726#define OSD1_AFBCD_MIF_URGENT GENMASK(25, 24)1727#define OSD1_AFBCD_HOLD_LINE_NUM GENMASK(22, 16)1728#define OSD1_AFBCD_RGBA_EXCHAN_CTRL GENMASK(15, 8)1729#define OSD1_AFBCD_HREG_BLOCK_SPLIT BIT(6)1730#define OSD1_AFBCD_HREG_HALF_BLOCK BIT(5)1731#define OSD1_AFBCD_HREG_PIXEL_PACKING_FMT GENMASK(4, 0)1732#define OSD1_AFBCD_SIZE_IN 0x31a21733#define OSD1_AFBCD_HREG_VSIZE_IN GENMASK(31, 16)1734#define OSD1_AFBCD_HREG_HSIZE_IN GENMASK(15, 0)1735#define OSD1_AFBCD_HDR_PTR 0x31a31736#define OSD1_AFBCD_FRAME_PTR 0x31a41737#define OSD1_AFBCD_CHROMA_PTR 0x31a51738#define OSD1_AFBCD_CONV_CTRL 0x31a61739#define OSD1_AFBCD_CONV_LBUF_LEN GENMASK(15, 0)1740#define OSD1_AFBCD_STATUS 0x31a81741#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a91742#define OSD1_AFBCD_DEC_PIXEL_BGN_H GENMASK(31, 16)1743#define OSD1_AFBCD_DEC_PIXEL_END_H GENMASK(15, 0)1744#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa1745#define OSD1_AFBCD_DEC_PIXEL_BGN_V GENMASK(31, 16)1746#define OSD1_AFBCD_DEC_PIXEL_END_V GENMASK(15, 0)1747 1748/* add for gxm and 962e dv core2 */1749#define DOLBY_CORE2A_SWAP_CTRL1 0x34341750#define DOLBY_CORE2A_SWAP_CTRL2 0x34351751 1752/* osd afbc on g12a */1753#define VPU_MAFBC_BLOCK_ID 0x3a001754#define VPU_MAFBC_IRQ_RAW_STATUS 0x3a011755#define VPU_MAFBC_IRQ_CLEAR 0x3a021756#define VPU_MAFBC_IRQ_MASK 0x3a031757#define VPU_MAFBC_IRQ_STATUS 0x3a041758#define VPU_MAFBC_IRQ_SECURE_ID_ERROR BIT(5)1759#define VPU_MAFBC_IRQ_AXI_ERROR BIT(4)1760#define VPU_MAFBC_IRQ_DETILING_ERROR BIT(3)1761#define VPU_MAFBC_IRQ_DECODE_ERROR BIT(2)1762#define VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED BIT(1)1763#define VPU_MAFBC_IRQ_SURFACES_COMPLETED BIT(0)1764#define VPU_MAFBC_COMMAND 0x3a051765#define VPU_MAFBC_PENDING_SWAP BIT(1)1766#define VPU_MAFBC_DIRECT_SWAP BIT(0)1767#define VPU_MAFBC_STATUS 0x3a061768#define VPU_MAFBC_ERROR BIT(2)1769#define VPU_MAFBC_SWAPPING BIT(1)1770#define VPU_MAFBC_ACTIVE BIT(0)1771#define VPU_MAFBC_SURFACE_CFG 0x3a071772#define VPU_MAFBC_CONTINUOUS_DECODING_ENABLE BIT(16)1773#define VPU_MAFBC_S3_ENABLE BIT(3)1774#define VPU_MAFBC_S2_ENABLE BIT(2)1775#define VPU_MAFBC_S1_ENABLE BIT(1)1776#define VPU_MAFBC_S0_ENABLE BIT(0)1777#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a101778#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a111779#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a121780#define VPU_MAFBC_PAYLOAD_LIMIT_EN BIT(19)1781#define VPU_MAFBC_TILED_HEADER_EN BIT(18)1782#define VPU_MAFBC_SUPER_BLOCK_ASPECT GENMASK(17, 16)1783#define VPU_MAFBC_BLOCK_SPLIT BIT(9)1784#define VPU_MAFBC_YUV_TRANSFORM BIT(8)1785#define VPU_MAFBC_PIXEL_FORMAT GENMASK(3, 0)1786#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a131787#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a141788#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a151789#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a161790#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a171791#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a181792#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a191793#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a1794#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b1795#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c1796#define VPU_MAFBC_PREFETCH_READ_DIRECTION_Y BIT(1)1797#define VPU_MAFBC_PREFETCH_READ_DIRECTION_X BIT(0)1798 1799#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a301800#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a311801#define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a321802#define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a331803#define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a341804#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a351805#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a361806#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a371807#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a381808#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a391809#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a1810#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b1811#define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c1812 1813#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a501814#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a511815#define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a521816#define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a531817#define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a541818#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a551819#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a561820#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a571821#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a581822#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a591823#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a1824#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b1825#define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c1826 1827#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a701828#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a711829#define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a721830#define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a731831#define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a741832#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a751833#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a761834#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a771835#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a781836#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a791837#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a1838#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b1839#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c1840 1841#define DOLBY_PATH_CTRL 0x1a0c1842#define DOLBY_BYPASS_EN(val) (val & 0xf)1843#define OSD_PATH_MISC_CTRL 0x1a0e1844#define OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD BIT(4)1845#define OSD_PATH_OSD_AXI_SEL_OSD2_AFBCD BIT(5)1846#define OSD_PATH_OSD_AXI_SEL_OSD3_AFBCD BIT(6)1847#define MALI_AFBCD_TOP_CTRL 0x1a0f1848#define MALI_AFBCD_MANUAL_RESET BIT(23)1849 1850#define VIU_OSD_BLEND_CTRL 0x39b01851#define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))1852#define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20)1853#define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24)1854#define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25)1855#define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26)1856#define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)1857#define VIU_OSD_BLEND_HOLD_LINES(lines) ((lines & 0x7) << 29)1858#define VIU_OSD_BLEND_CTRL1 0x39c01859#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b11860#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b21861#define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b31862#define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b41863#define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b51864#define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b61865#define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b71866#define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b81867#define VIU_OSD_BLEND_DUMMY_DATA0 0x39b91868#define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba1869#define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb1870#define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc1871#define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf1872 1873#define VPP_OUT_H_V_SIZE 0x1da51874 1875#define VPP_VD2_HDR_IN_SIZE 0x1df01876#define VPP_OSD1_IN_SIZE 0x1df11877#define VPP_GCLK_CTRL2 0x1df21878#define VD2_PPS_DUMMY_DATA 0x1df41879#define VPP_OSD1_BLD_H_SCOPE 0x1df51880#define VPP_OSD1_BLD_V_SCOPE 0x1df61881#define VPP_OSD2_BLD_H_SCOPE 0x1df71882#define VPP_OSD2_BLD_V_SCOPE 0x1df81883#define VPP_WRBAK_CTRL 0x1df91884#define VPP_SLEEP_CTRL 0x1dfa1885#define VD1_BLEND_SRC_CTRL 0x1dfb1886#define VD2_BLEND_SRC_CTRL 0x1dfc1887#define VD_BLEND_PREBLD_SRC_VD1 (1 << 0)1888#define VD_BLEND_PREBLD_SRC_VD2 (2 << 0)1889#define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0)1890#define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0)1891#define VD_BLEND_PREBLD_PREMULT_EN BIT(4)1892#define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8)1893#define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8)1894#define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8)1895#define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8)1896#define VD_BLEND_POSTBLD_PREMULT_EN BIT(16)1897#define OSD1_BLEND_SRC_CTRL 0x1dfd1898#define OSD2_BLEND_SRC_CTRL 0x1dfe1899#define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8)1900#define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8)1901#define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8)1902#define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8)1903#define OSD_BLEND_PATH_SEL_ENABLE BIT(20)1904 1905#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x39681906#define VPP_POST_BLEND_DUMMY_ALPHA 0x39691907#define VPP_RDARB_MODE 0x39781908#define VPP_RDARB_REQEN_SLV 0x39791909 1910#endif /* __MESON_REGISTERS_H */1911