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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */3 4#ifndef __A6XX_GPU_H__5#define __A6XX_GPU_H__6 7 8#include "adreno_gpu.h"9#include "a6xx.xml.h"10 11#include "a6xx_gmu.h"12 13extern bool hang_debug;14 15/**16 * struct a6xx_info - a6xx specific information from device table17 *18 * @hwcg: hw clock gating register sequence19 * @protect: CP_PROTECT settings20 */21struct a6xx_info {22 const struct adreno_reglist *hwcg;23 const struct adreno_protect *protect;24 u32 gmu_chipid;25 u32 gmu_cgc_mode;26 u32 prim_fifo_threshold;27};28 29struct a6xx_gpu {30 struct adreno_gpu base;31 32 struct drm_gem_object *sqe_bo;33 uint64_t sqe_iova;34 35 struct msm_ringbuffer *cur_ring;36 37 struct a6xx_gmu gmu;38 39 struct drm_gem_object *shadow_bo;40 uint64_t shadow_iova;41 uint32_t *shadow;42 43 bool has_whereami;44 45 void __iomem *llc_mmio;46 void *llc_slice;47 void *htw_llc_slice;48 bool have_mmu500;49 bool hung;50};51 52#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)53 54/*55 * Given a register and a count, return a value to program into56 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for57 * _len + 1 registers starting at _reg.58 */59#define A6XX_PROTECT_NORDWR(_reg, _len) \60 ((1 << 31) | \61 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))62 63/*64 * Same as above, but allow reads over the range. For areas of mixed use (such65 * as performance counters) this allows us to protect a much larger range with a66 * single register67 */68#define A6XX_PROTECT_RDONLY(_reg, _len) \69 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))70 71static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)72{73 if(adreno_is_a630(gpu))74 return false;75 76 return true;77}78 79static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)80{81 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);82}83 84static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)85{86 return readl(a6xx_gpu->llc_mmio + (reg << 2));87}88 89static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)90{91 writel(value, a6xx_gpu->llc_mmio + (reg << 2));92}93 94#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \95 ((_ring)->id * sizeof(uint32_t)))96 97int a6xx_gmu_resume(struct a6xx_gpu *gpu);98int a6xx_gmu_stop(struct a6xx_gpu *gpu);99 100int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);101 102bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);103 104int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);105void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);106 107int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);108int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);109void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);110 111void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,112 bool suspended);113unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);114 115void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,116 struct drm_printer *p);117 118struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);119int a6xx_gpu_state_put(struct msm_gpu_state *state);120 121void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);122void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);123 124#endif /* __A6XX_GPU_H__ */125