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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2013-2014 Red Hat4 * Author: Rob Clark <robdclark@gmail.com>5 *6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.7 */8 9#include "adreno_gpu.h"10 11bool hang_debug = false;12MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");13module_param_named(hang_debug, hang_debug, bool, 0600);14 15bool snapshot_debugbus = false;16MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");17module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);18 19bool allow_vram_carveout = false;20MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");21module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);22 23extern const struct adreno_gpulist a2xx_gpulist;24extern const struct adreno_gpulist a3xx_gpulist;25extern const struct adreno_gpulist a4xx_gpulist;26extern const struct adreno_gpulist a5xx_gpulist;27extern const struct adreno_gpulist a6xx_gpulist;28extern const struct adreno_gpulist a7xx_gpulist;29 30static const struct adreno_gpulist *gpulists[] = {31 &a2xx_gpulist,32 &a3xx_gpulist,33 &a4xx_gpulist,34 &a5xx_gpulist,35 &a6xx_gpulist,36 &a7xx_gpulist,37};38 39static const struct adreno_info *adreno_info(uint32_t chip_id)40{41 /* identify gpu: */42 for (int i = 0; i < ARRAY_SIZE(gpulists); i++) {43 for (int j = 0; j < gpulists[i]->gpus_count; j++) {44 const struct adreno_info *info = &gpulists[i]->gpus[j];45 46 if (info->machine && !of_machine_is_compatible(info->machine))47 continue;48 49 for (int k = 0; info->chip_ids[k]; k++)50 if (info->chip_ids[k] == chip_id)51 return info;52 }53 }54 55 return NULL;56}57 58struct msm_gpu *adreno_load_gpu(struct drm_device *dev)59{60 struct msm_drm_private *priv = dev->dev_private;61 struct platform_device *pdev = priv->gpu_pdev;62 struct msm_gpu *gpu = NULL;63 struct adreno_gpu *adreno_gpu;64 int ret;65 66 if (pdev)67 gpu = dev_to_gpu(&pdev->dev);68 69 if (!gpu) {70 dev_err_once(dev->dev, "no GPU device was found\n");71 return NULL;72 }73 74 adreno_gpu = to_adreno_gpu(gpu);75 76 /*77 * The number one reason for HW init to fail is if the firmware isn't78 * loaded yet. Try that first and don't bother continuing on79 * otherwise80 */81 82 ret = adreno_load_fw(adreno_gpu);83 if (ret)84 return NULL;85 86 if (gpu->funcs->ucode_load) {87 ret = gpu->funcs->ucode_load(gpu);88 if (ret)89 return NULL;90 }91 92 /*93 * Now that we have firmware loaded, and are ready to begin94 * booting the gpu, go ahead and enable runpm:95 */96 pm_runtime_enable(&pdev->dev);97 98 ret = pm_runtime_get_sync(&pdev->dev);99 if (ret < 0) {100 pm_runtime_put_noidle(&pdev->dev);101 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);102 goto err_disable_rpm;103 }104 105 mutex_lock(&gpu->lock);106 ret = msm_gpu_hw_init(gpu);107 mutex_unlock(&gpu->lock);108 if (ret) {109 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);110 goto err_put_rpm;111 }112 113 pm_runtime_put_autosuspend(&pdev->dev);114 115#ifdef CONFIG_DEBUG_FS116 if (gpu->funcs->debugfs_init) {117 gpu->funcs->debugfs_init(gpu, dev->primary);118 gpu->funcs->debugfs_init(gpu, dev->render);119 }120#endif121 122 return gpu;123 124err_put_rpm:125 pm_runtime_put_sync_suspend(&pdev->dev);126err_disable_rpm:127 pm_runtime_disable(&pdev->dev);128 129 return NULL;130}131 132static int find_chipid(struct device *dev, uint32_t *chipid)133{134 struct device_node *node = dev->of_node;135 const char *compat;136 int ret;137 138 /* first search the compat strings for qcom,adreno-XYZ.W: */139 ret = of_property_read_string_index(node, "compatible", 0, &compat);140 if (ret == 0) {141 unsigned int r, patch;142 143 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||144 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {145 uint32_t core, major, minor;146 147 core = r / 100;148 r %= 100;149 major = r / 10;150 r %= 10;151 minor = r;152 153 *chipid = (core << 24) |154 (major << 16) |155 (minor << 8) |156 patch;157 158 return 0;159 }160 161 if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)162 return 0;163 }164 165 /* and if that fails, fall back to legacy "qcom,chipid" property: */166 ret = of_property_read_u32(node, "qcom,chipid", chipid);167 if (ret) {168 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);169 return ret;170 }171 172 dev_warn(dev, "Using legacy qcom,chipid binding!\n");173 174 return 0;175}176 177static int adreno_bind(struct device *dev, struct device *master, void *data)178{179 static struct adreno_platform_config config = {};180 const struct adreno_info *info;181 struct msm_drm_private *priv = dev_get_drvdata(master);182 struct drm_device *drm = priv->dev;183 struct msm_gpu *gpu;184 int ret;185 186 ret = find_chipid(dev, &config.chip_id);187 if (ret)188 return ret;189 190 dev->platform_data = &config;191 priv->gpu_pdev = to_platform_device(dev);192 193 info = adreno_info(config.chip_id);194 if (!info) {195 dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",196 ADRENO_CHIPID_ARGS(config.chip_id));197 return -ENXIO;198 }199 200 config.info = info;201 202 DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));203 204 priv->is_a2xx = info->family < ADRENO_3XX;205 priv->has_cached_coherent =206 !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);207 208 gpu = info->init(drm);209 if (IS_ERR(gpu)) {210 dev_warn(drm->dev, "failed to load adreno gpu\n");211 return PTR_ERR(gpu);212 }213 214 ret = dev_pm_opp_of_find_icc_paths(dev, NULL);215 if (ret)216 return ret;217 218 return 0;219}220 221static int adreno_system_suspend(struct device *dev);222static void adreno_unbind(struct device *dev, struct device *master,223 void *data)224{225 struct msm_drm_private *priv = dev_get_drvdata(master);226 struct msm_gpu *gpu = dev_to_gpu(dev);227 228 if (pm_runtime_enabled(dev))229 WARN_ON_ONCE(adreno_system_suspend(dev));230 gpu->funcs->destroy(gpu);231 232 priv->gpu_pdev = NULL;233}234 235static const struct component_ops a3xx_ops = {236 .bind = adreno_bind,237 .unbind = adreno_unbind,238};239 240static void adreno_device_register_headless(void)241{242 /* on imx5, we don't have a top-level mdp/dpu node243 * this creates a dummy node for the driver for that case244 */245 struct platform_device_info dummy_info = {246 .parent = NULL,247 .name = "msm",248 .id = -1,249 .res = NULL,250 .num_res = 0,251 .data = NULL,252 .size_data = 0,253 .dma_mask = ~0,254 };255 platform_device_register_full(&dummy_info);256}257 258static int adreno_probe(struct platform_device *pdev)259{260 261 int ret;262 263 ret = component_add(&pdev->dev, &a3xx_ops);264 if (ret)265 return ret;266 267 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))268 adreno_device_register_headless();269 270 return 0;271}272 273static void adreno_remove(struct platform_device *pdev)274{275 component_del(&pdev->dev, &a3xx_ops);276}277 278static void adreno_shutdown(struct platform_device *pdev)279{280 WARN_ON_ONCE(adreno_system_suspend(&pdev->dev));281}282 283static const struct of_device_id dt_match[] = {284 { .compatible = "qcom,adreno" },285 { .compatible = "qcom,adreno-3xx" },286 /* for compatibility with imx5 gpu: */287 { .compatible = "amd,imageon" },288 /* for backwards compat w/ downstream kgsl DT files: */289 { .compatible = "qcom,kgsl-3d0" },290 {}291};292 293static int adreno_runtime_resume(struct device *dev)294{295 struct msm_gpu *gpu = dev_to_gpu(dev);296 297 return gpu->funcs->pm_resume(gpu);298}299 300static int adreno_runtime_suspend(struct device *dev)301{302 struct msm_gpu *gpu = dev_to_gpu(dev);303 304 /*305 * We should be holding a runpm ref, which will prevent306 * runtime suspend. In the system suspend path, we've307 * already waited for active jobs to complete.308 */309 WARN_ON_ONCE(gpu->active_submits);310 311 return gpu->funcs->pm_suspend(gpu);312}313 314static void suspend_scheduler(struct msm_gpu *gpu)315{316 int i;317 318 /*319 * Shut down the scheduler before we force suspend, so that320 * suspend isn't racing with scheduler kthread feeding us321 * more work.322 *323 * Note, we just want to park the thread, and let any jobs324 * that are already on the hw queue complete normally, as325 * opposed to the drm_sched_stop() path used for handling326 * faulting/timed-out jobs. We can't really cancel any jobs327 * already on the hw queue without racing with the GPU.328 */329 for (i = 0; i < gpu->nr_rings; i++) {330 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;331 332 drm_sched_wqueue_stop(sched);333 }334}335 336static void resume_scheduler(struct msm_gpu *gpu)337{338 int i;339 340 for (i = 0; i < gpu->nr_rings; i++) {341 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;342 343 drm_sched_wqueue_start(sched);344 }345}346 347static int adreno_system_suspend(struct device *dev)348{349 struct msm_gpu *gpu = dev_to_gpu(dev);350 int remaining, ret;351 352 if (!gpu)353 return 0;354 355 suspend_scheduler(gpu);356 357 remaining = wait_event_timeout(gpu->retire_event,358 gpu->active_submits == 0,359 msecs_to_jiffies(1000));360 if (remaining == 0) {361 dev_err(dev, "Timeout waiting for GPU to suspend\n");362 ret = -EBUSY;363 goto out;364 }365 366 ret = pm_runtime_force_suspend(dev);367out:368 if (ret)369 resume_scheduler(gpu);370 371 return ret;372}373 374static int adreno_system_resume(struct device *dev)375{376 struct msm_gpu *gpu = dev_to_gpu(dev);377 378 if (!gpu)379 return 0;380 381 resume_scheduler(gpu);382 return pm_runtime_force_resume(dev);383}384 385static const struct dev_pm_ops adreno_pm_ops = {386 SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume)387 RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL)388};389 390static struct platform_driver adreno_driver = {391 .probe = adreno_probe,392 .remove_new = adreno_remove,393 .shutdown = adreno_shutdown,394 .driver = {395 .name = "adreno",396 .of_match_table = dt_match,397 .pm = &adreno_pm_ops,398 },399};400 401void __init adreno_register(void)402{403 platform_driver_register(&adreno_driver);404}405 406void __exit adreno_unregister(void)407{408 platform_driver_unregister(&adreno_driver);409}410