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1// SPDX-License-Identifier: GPL-2.0-only2/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.3 */4 5#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__6#include "dpu_encoder_phys.h"7#include "dpu_hw_interrupts.h"8#include "dpu_hw_merge3d.h"9#include "dpu_core_irq.h"10#include "dpu_formats.h"11#include "dpu_trace.h"12#include "disp/msm_disp_snapshot.h"13 14#include <drm/display/drm_dsc_helper.h>15#include <drm/drm_managed.h>16 17#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \18 (e) && (e)->parent ? \19 (e)->parent->base.id : -1, \20 (e) && (e)->hw_intf ? \21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)22 23#define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \24 (e) && (e)->parent ? \25 (e)->parent->base.id : -1, \26 (e) && (e)->hw_intf ? \27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)28 29#define to_dpu_encoder_phys_vid(x) \30 container_of(x, struct dpu_encoder_phys_vid, base)31 32static bool dpu_encoder_phys_vid_is_master(33 struct dpu_encoder_phys *phys_enc)34{35 bool ret = false;36 37 if (phys_enc->split_role != ENC_ROLE_SLAVE)38 ret = true;39 40 return ret;41}42 43static void drm_mode_to_intf_timing_params(44 const struct dpu_encoder_phys *phys_enc,45 const struct drm_display_mode *mode,46 struct dpu_hw_intf_timing_params *timing)47{48 memset(timing, 0, sizeof(*timing));49 50 if ((mode->htotal < mode->hsync_end)51 || (mode->hsync_start < mode->hdisplay)52 || (mode->vtotal < mode->vsync_end)53 || (mode->vsync_start < mode->vdisplay)54 || (mode->hsync_end < mode->hsync_start)55 || (mode->vsync_end < mode->vsync_start)) {56 DPU_ERROR(57 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",58 mode->hsync_start, mode->hsync_end,59 mode->htotal, mode->hdisplay);60 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",61 mode->vsync_start, mode->vsync_end,62 mode->vtotal, mode->vdisplay);63 return;64 }65 66 /*67 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html68 * Active Region Front Porch Sync Back Porch69 * <-----------------><------------><-----><----------->70 * <- [hv]display --->71 * <--------- [hv]sync_start ------>72 * <----------------- [hv]sync_end ------->73 * <---------------------------- [hv]total ------------->74 */75 timing->width = mode->hdisplay; /* active width */76 timing->height = mode->vdisplay; /* active height */77 timing->xres = timing->width;78 timing->yres = timing->height;79 timing->h_back_porch = mode->htotal - mode->hsync_end;80 timing->h_front_porch = mode->hsync_start - mode->hdisplay;81 timing->v_back_porch = mode->vtotal - mode->vsync_end;82 timing->v_front_porch = mode->vsync_start - mode->vdisplay;83 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;84 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;85 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;86 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;87 timing->border_clr = 0;88 timing->underflow_clr = 0xff;89 timing->hsync_skew = mode->hskew;90 91 /* DSI controller cannot handle active-low sync signals. */92 if (phys_enc->hw_intf->cap->type == INTF_DSI) {93 timing->hsync_polarity = 0;94 timing->vsync_polarity = 0;95 }96 97 /* for DP/EDP, Shift timings to align it to bottom right */98 if (phys_enc->hw_intf->cap->type == INTF_DP) {99 timing->h_back_porch += timing->h_front_porch;100 timing->h_front_porch = 0;101 timing->v_back_porch += timing->v_front_porch;102 timing->v_front_porch = 0;103 }104 105 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);106 timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);107 108 /*109 * for DP, divide the horizonal parameters by 2 when110 * widebus is enabled111 */112 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {113 timing->width = timing->width >> 1;114 timing->xres = timing->xres >> 1;115 timing->h_back_porch = timing->h_back_porch >> 1;116 timing->h_front_porch = timing->h_front_porch >> 1;117 timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;118 }119 120 /*121 * for DSI, if compression is enabled, then divide the horizonal active122 * timing parameters by compression ratio. bits of 3 components(R/G/B)123 * is compressed into bits of 1 pixel.124 */125 if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {126 struct drm_dsc_config *dsc =127 dpu_encoder_get_dsc_config(phys_enc->parent);128 /*129 * TODO: replace drm_dsc_get_bpp_int with logic to handle130 * fractional part if there is fraction131 */132 timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /133 (dsc->bits_per_component * 3);134 timing->xres = timing->width;135 }136}137 138static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)139{140 u32 active = timing->xres;141 u32 inactive =142 timing->h_back_porch + timing->h_front_porch +143 timing->hsync_pulse_width;144 return active + inactive;145}146 147static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)148{149 u32 active = timing->yres;150 u32 inactive =151 timing->v_back_porch + timing->v_front_porch +152 timing->vsync_pulse_width;153 return active + inactive;154}155 156/*157 * programmable_fetch_get_num_lines:158 * Number of fetch lines in vertical front porch159 * @timing: Pointer to the intf timing information for the requested mode160 *161 * Returns the number of fetch lines in vertical front porch at which mdp162 * can start fetching the next frame.163 *164 * Number of needed prefetch lines is anything that cannot be absorbed in the165 * start of frame time (back porch + vsync pulse width).166 *167 * Some panels have very large VFP, however we only need a total number of168 * lines based on the chip worst case latencies.169 */170static u32 programmable_fetch_get_num_lines(171 struct dpu_encoder_phys *phys_enc,172 const struct dpu_hw_intf_timing_params *timing)173{174 u32 worst_case_needed_lines =175 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;176 u32 start_of_frame_lines =177 timing->v_back_porch + timing->vsync_pulse_width;178 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;179 u32 actual_vfp_lines = 0;180 181 /* Fetch must be outside active lines, otherwise undefined. */182 if (start_of_frame_lines >= worst_case_needed_lines) {183 DPU_DEBUG_VIDENC(phys_enc,184 "prog fetch is not needed, large vbp+vsw\n");185 actual_vfp_lines = 0;186 } else if (timing->v_front_porch < needed_vfp_lines) {187 /* Warn fetch needed, but not enough porch in panel config */188 pr_warn_once189 ("low vbp+vfp may lead to perf issues in some cases\n");190 DPU_DEBUG_VIDENC(phys_enc,191 "less vfp than fetch req, using entire vfp\n");192 actual_vfp_lines = timing->v_front_porch;193 } else {194 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");195 actual_vfp_lines = needed_vfp_lines;196 }197 198 DPU_DEBUG_VIDENC(phys_enc,199 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",200 timing->v_front_porch, timing->v_back_porch,201 timing->vsync_pulse_width);202 DPU_DEBUG_VIDENC(phys_enc,203 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",204 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);205 206 return actual_vfp_lines;207}208 209/*210 * programmable_fetch_config: Programs HW to prefetch lines by offsetting211 * the start of fetch into the vertical front porch for cases where the212 * vsync pulse width and vertical back porch time is insufficient213 *214 * Gets # of lines to pre-fetch, then calculate VSYNC counter value.215 * HW layer requires VSYNC counter of first pixel of tgt VFP line.216 *217 * @timing: Pointer to the intf timing information for the requested mode218 */219static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,220 const struct dpu_hw_intf_timing_params *timing)221{222 struct dpu_hw_intf_prog_fetch f = { 0 };223 u32 vfp_fetch_lines = 0;224 u32 horiz_total = 0;225 u32 vert_total = 0;226 u32 vfp_fetch_start_vsync_counter = 0;227 unsigned long lock_flags;228 229 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))230 return;231 232 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);233 if (vfp_fetch_lines) {234 vert_total = get_vertical_total(timing);235 horiz_total = get_horizontal_total(timing);236 vfp_fetch_start_vsync_counter =237 (vert_total - vfp_fetch_lines) * horiz_total + 1;238 f.enable = 1;239 f.fetch_start = vfp_fetch_start_vsync_counter;240 }241 242 DPU_DEBUG_VIDENC(phys_enc,243 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",244 vfp_fetch_lines, vfp_fetch_start_vsync_counter);245 246 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);247 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);248 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);249}250 251static void dpu_encoder_phys_vid_setup_timing_engine(252 struct dpu_encoder_phys *phys_enc)253{254 struct drm_display_mode mode;255 struct dpu_hw_intf_timing_params timing_params = { 0 };256 const struct msm_format *fmt = NULL;257 u32 fmt_fourcc;258 unsigned long lock_flags;259 struct dpu_hw_intf_cfg intf_cfg = { 0 };260 261 drm_mode_init(&mode, &phys_enc->cached_mode);262 263 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {264 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);265 return;266 }267 268 if (!phys_enc->hw_intf->ops.setup_timing_gen) {269 DPU_ERROR("timing engine setup is not supported\n");270 return;271 }272 273 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");274 drm_mode_debug_printmodeline(&mode);275 276 fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);277 278 if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == DRM_FORMAT_YUV420) {279 mode.hdisplay >>= 1;280 mode.htotal >>= 1;281 mode.hsync_start >>= 1;282 mode.hsync_end >>= 1;283 mode.hskew >>= 1;284 285 DPU_DEBUG_VIDENC(phys_enc,286 "split_role %d, halve horizontal %d %d %d %d %d\n",287 phys_enc->split_role,288 mode.hdisplay, mode.htotal,289 mode.hsync_start, mode.hsync_end,290 mode.hskew);291 }292 293 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);294 295 fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);296 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);297 298 if (phys_enc->hw_cdm)299 intf_cfg.cdm = phys_enc->hw_cdm->idx;300 intf_cfg.intf = phys_enc->hw_intf->idx;301 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;302 intf_cfg.stream_sel = 0; /* Don't care value for video mode */303 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);304 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);305 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d)306 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;307 308 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);309 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,310 &timing_params, fmt,311 phys_enc->dpu_kms->catalog->mdss_ver);312 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);313 314 /* setup which pp blk will connect to this intf */315 if (phys_enc->hw_intf->ops.bind_pingpong_blk)316 phys_enc->hw_intf->ops.bind_pingpong_blk(317 phys_enc->hw_intf,318 phys_enc->hw_pp->idx);319 320 if (phys_enc->hw_pp->merge_3d)321 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);322 323 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);324 325 programmable_fetch_config(phys_enc, &timing_params);326}327 328static void dpu_encoder_phys_vid_vblank_irq(void *arg)329{330 struct dpu_encoder_phys *phys_enc = arg;331 struct dpu_hw_ctl *hw_ctl;332 unsigned long lock_flags;333 u32 flush_register = 0;334 335 hw_ctl = phys_enc->hw_ctl;336 337 DPU_ATRACE_BEGIN("vblank_irq");338 339 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);340 341 atomic_read(&phys_enc->pending_kickoff_cnt);342 343 /*344 * only decrement the pending flush count if we've actually flushed345 * hardware. due to sw irq latency, vblank may have already happened346 * so we need to double-check with hw that it accepted the flush bits347 */348 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);349 if (hw_ctl->ops.get_flush_register)350 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);351 352 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))353 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);354 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);355 356 /* Signal any waiting atomic commit thread */357 wake_up_all(&phys_enc->pending_kickoff_wq);358 359 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,360 DPU_ENCODER_FRAME_EVENT_DONE);361 362 DPU_ATRACE_END("vblank_irq");363}364 365static void dpu_encoder_phys_vid_underrun_irq(void *arg)366{367 struct dpu_encoder_phys *phys_enc = arg;368 369 dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);370}371 372static bool dpu_encoder_phys_vid_needs_single_flush(373 struct dpu_encoder_phys *phys_enc)374{375 return phys_enc->split_role != ENC_ROLE_SOLO;376}377 378static void dpu_encoder_phys_vid_atomic_mode_set(379 struct dpu_encoder_phys *phys_enc,380 struct drm_crtc_state *crtc_state,381 struct drm_connector_state *conn_state)382{383 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;384 385 phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;386}387 388static int dpu_encoder_phys_vid_control_vblank_irq(389 struct dpu_encoder_phys *phys_enc,390 bool enable)391{392 int ret = 0;393 int refcount;394 395 mutex_lock(&phys_enc->vblank_ctl_lock);396 refcount = phys_enc->vblank_refcount;397 398 /* Slave encoders don't report vblank */399 if (!dpu_encoder_phys_vid_is_master(phys_enc))400 goto end;401 402 /* protect against negative */403 if (!enable && refcount == 0) {404 ret = -EINVAL;405 goto end;406 }407 408 DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,409 refcount);410 411 if (enable) {412 if (phys_enc->vblank_refcount == 0)413 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,414 phys_enc->irq[INTR_IDX_VSYNC],415 dpu_encoder_phys_vid_vblank_irq,416 phys_enc);417 if (!ret)418 phys_enc->vblank_refcount++;419 } else if (!enable) {420 if (phys_enc->vblank_refcount == 1)421 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,422 phys_enc->irq[INTR_IDX_VSYNC]);423 if (!ret)424 phys_enc->vblank_refcount--;425 }426 427end:428 mutex_unlock(&phys_enc->vblank_ctl_lock);429 if (ret) {430 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",431 DRMID(phys_enc->parent),432 phys_enc->hw_intf->idx - INTF_0, ret, enable,433 refcount);434 }435 return ret;436}437 438static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)439{440 struct dpu_hw_ctl *ctl;441 const struct msm_format *fmt;442 u32 fmt_fourcc;443 u32 mode_3d;444 445 ctl = phys_enc->hw_ctl;446 fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);447 fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);448 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);449 450 DPU_DEBUG_VIDENC(phys_enc, "\n");451 452 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))453 return;454 455 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);456 457 dpu_encoder_helper_phys_setup_cdm(phys_enc, fmt, CDM_CDWN_OUTPUT_HDMI);458 459 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);460 461 /*462 * For single flush cases (dual-ctl or pp-split), skip setting the463 * flush bit for the slave intf, since both intfs use same ctl464 * and HW will only flush the master.465 */466 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&467 !dpu_encoder_phys_vid_is_master(phys_enc))468 goto skip_flush;469 470 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);471 if (mode_3d && ctl->ops.update_pending_flush_merge_3d &&472 phys_enc->hw_pp->merge_3d)473 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);474 475 if (ctl->ops.update_pending_flush_cdm && phys_enc->hw_cdm)476 ctl->ops.update_pending_flush_cdm(ctl, phys_enc->hw_cdm->idx);477 478 /*479 * Peripheral flush must be updated whenever flushing SDP packets is needed.480 * SDP packets are required for any YUV format (YUV420, YUV422, YUV444).481 */482 if (ctl->ops.update_pending_flush_periph && dpu_encoder_needs_periph_flush(phys_enc))483 ctl->ops.update_pending_flush_periph(ctl, phys_enc->hw_intf->idx);484 485skip_flush:486 DPU_DEBUG_VIDENC(phys_enc,487 "update pending flush ctl %d intf %d\n",488 ctl->idx - CTL_0, phys_enc->hw_intf->idx);489 490 atomic_set(&phys_enc->underrun_cnt, 0);491 492 /* ctl_flush & timing engine enable will be triggered by framework */493 if (phys_enc->enable_state == DPU_ENC_DISABLED)494 phys_enc->enable_state = DPU_ENC_ENABLING;495}496 497static int dpu_encoder_phys_vid_wait_for_tx_complete(498 struct dpu_encoder_phys *phys_enc)499{500 struct dpu_encoder_wait_info wait_info;501 int ret;502 503 wait_info.wq = &phys_enc->pending_kickoff_wq;504 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;505 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;506 507 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {508 return 0;509 }510 511 /* Wait for kickoff to complete */512 ret = dpu_encoder_helper_wait_for_irq(phys_enc,513 phys_enc->irq[INTR_IDX_VSYNC],514 dpu_encoder_phys_vid_vblank_irq,515 &wait_info);516 517 if (ret == -ETIMEDOUT) {518 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);519 }520 521 return ret;522}523 524static int dpu_encoder_phys_vid_wait_for_commit_done(525 struct dpu_encoder_phys *phys_enc)526{527 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;528 int ret;529 530 if (!hw_ctl)531 return 0;532 533 ret = wait_event_timeout(phys_enc->pending_kickoff_wq,534 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),535 msecs_to_jiffies(50));536 if (ret <= 0) {537 DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl));538 return -ETIMEDOUT;539 }540 541 return 0;542}543 544static void dpu_encoder_phys_vid_prepare_for_kickoff(545 struct dpu_encoder_phys *phys_enc)546{547 struct dpu_hw_ctl *ctl;548 int rc;549 struct drm_encoder *drm_enc;550 551 drm_enc = phys_enc->parent;552 553 ctl = phys_enc->hw_ctl;554 if (!ctl->ops.wait_reset_status)555 return;556 557 /*558 * hw supports hardware initiated ctl reset, so before we kickoff a new559 * frame, need to check and wait for hw initiated ctl reset completion560 */561 rc = ctl->ops.wait_reset_status(ctl);562 if (rc) {563 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",564 ctl->idx, rc);565 msm_disp_snapshot_state(drm_enc->dev);566 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,567 phys_enc->irq[INTR_IDX_VSYNC]);568 }569}570 571static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)572{573 unsigned long lock_flags;574 int ret;575 struct dpu_hw_intf_status intf_status = {0};576 577 if (!phys_enc->parent || !phys_enc->parent->dev) {578 DPU_ERROR("invalid encoder/device\n");579 return;580 }581 582 if (!phys_enc->hw_intf) {583 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",584 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);585 return;586 }587 588 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))589 return;590 591 if (phys_enc->enable_state == DPU_ENC_DISABLED) {592 DPU_ERROR("already disabled\n");593 return;594 }595 596 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);597 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);598 if (dpu_encoder_phys_vid_is_master(phys_enc))599 dpu_encoder_phys_inc_pending(phys_enc);600 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);601 602 /*603 * Wait for a vsync so we know the ENABLE=0 latched before604 * the (connector) source of the vsync's gets disabled,605 * otherwise we end up in a funny state if we re-enable606 * before the disable latches, which results that some of607 * the settings changes for the new modeset (like new608 * scanout buffer) don't latch properly..609 */610 if (dpu_encoder_phys_vid_is_master(phys_enc)) {611 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);612 if (ret) {613 atomic_set(&phys_enc->pending_kickoff_cnt, 0);614 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",615 DRMID(phys_enc->parent),616 phys_enc->hw_intf->idx - INTF_0, ret);617 }618 }619 620 if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)621 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status);622 623 /*624 * Wait for a vsync if timing en status is on after timing engine625 * is disabled.626 */627 if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {628 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);629 dpu_encoder_phys_inc_pending(phys_enc);630 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);631 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);632 if (ret) {633 atomic_set(&phys_enc->pending_kickoff_cnt, 0);634 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",635 DRMID(phys_enc->parent),636 phys_enc->hw_intf->idx - INTF_0, ret);637 }638 }639 640 dpu_encoder_helper_phys_cleanup(phys_enc);641 phys_enc->enable_state = DPU_ENC_DISABLED;642}643 644static void dpu_encoder_phys_vid_handle_post_kickoff(645 struct dpu_encoder_phys *phys_enc)646{647 unsigned long lock_flags;648 649 /*650 * Video mode must flush CTL before enabling timing engine651 * Video encoders need to turn on their interfaces now652 */653 if (phys_enc->enable_state == DPU_ENC_ENABLING) {654 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),655 phys_enc->hw_intf->idx - INTF_0);656 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);657 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);658 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);659 phys_enc->enable_state = DPU_ENC_ENABLED;660 }661}662 663static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc)664{665 int ret;666 667 trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent),668 phys_enc->hw_intf->idx - INTF_0,669 phys_enc->vblank_refcount);670 671 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);672 if (WARN_ON(ret))673 return;674 675 dpu_core_irq_register_callback(phys_enc->dpu_kms,676 phys_enc->irq[INTR_IDX_UNDERRUN],677 dpu_encoder_phys_vid_underrun_irq,678 phys_enc);679}680 681static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc)682{683 trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent),684 phys_enc->hw_intf->idx - INTF_0,685 phys_enc->vblank_refcount);686 687 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);688 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,689 phys_enc->irq[INTR_IDX_UNDERRUN]);690}691 692static int dpu_encoder_phys_vid_get_line_count(693 struct dpu_encoder_phys *phys_enc)694{695 if (!dpu_encoder_phys_vid_is_master(phys_enc))696 return -EINVAL;697 698 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)699 return -EINVAL;700 701 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);702}703 704static int dpu_encoder_phys_vid_get_frame_count(705 struct dpu_encoder_phys *phys_enc)706{707 struct dpu_hw_intf_status s = {0};708 u32 fetch_start = 0;709 struct drm_display_mode mode;710 711 drm_mode_init(&mode, &phys_enc->cached_mode);712 713 if (!dpu_encoder_phys_vid_is_master(phys_enc))714 return -EINVAL;715 716 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)717 return -EINVAL;718 719 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);720 721 if (s.is_prog_fetch_en && s.is_en) {722 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);723 if ((s.line_count > fetch_start) &&724 (s.line_count <= mode.vtotal))725 return s.frame_count + 1;726 }727 728 return s.frame_count;729}730 731static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)732{733 ops->is_master = dpu_encoder_phys_vid_is_master;734 ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;735 ops->enable = dpu_encoder_phys_vid_enable;736 ops->disable = dpu_encoder_phys_vid_disable;737 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;738 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;739 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;740 ops->irq_enable = dpu_encoder_phys_vid_irq_enable;741 ops->irq_disable = dpu_encoder_phys_vid_irq_disable;742 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;743 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;744 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;745 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;746 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;747}748 749struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,750 struct dpu_enc_phys_init_params *p)751{752 struct dpu_encoder_phys *phys_enc = NULL;753 754 if (!p) {755 DPU_ERROR("failed to create encoder due to invalid parameter\n");756 return ERR_PTR(-EINVAL);757 }758 759 phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL);760 if (!phys_enc) {761 DPU_ERROR("failed to create encoder due to memory allocation error\n");762 return ERR_PTR(-ENOMEM);763 }764 765 DPU_DEBUG_VIDENC(phys_enc, "\n");766 767 dpu_encoder_phys_init(phys_enc, p);768 mutex_init(&phys_enc->vblank_ctl_lock);769 phys_enc->vblank_refcount = 0;770 771 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);772 phys_enc->intf_mode = INTF_MODE_VIDEO;773 774 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);775 776 return phys_enc;777}778