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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__7 8#include <linux/debugfs.h>9 10#include <drm/drm_framebuffer.h>11#include <drm/drm_managed.h>12 13#include "dpu_encoder_phys.h"14#include "dpu_formats.h"15#include "dpu_hw_top.h"16#include "dpu_hw_wb.h"17#include "dpu_hw_lm.h"18#include "dpu_hw_merge3d.h"19#include "dpu_hw_interrupts.h"20#include "dpu_core_irq.h"21#include "dpu_vbif.h"22#include "dpu_crtc.h"23#include "disp/msm_disp_snapshot.h"24 25#define to_dpu_encoder_phys_wb(x) \26 container_of(x, struct dpu_encoder_phys_wb, base)27 28/**29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder30 * @phys_enc: Pointer to physical encoder31 */32static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)33{34 /* there is only one physical enc for dpu_writeback */35 return true;36}37 38static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,39 struct dpu_hw_mdp *mdp,40 bool enable, bool *forced_on)41{42 if (wb->ops.setup_clk_force_ctrl) {43 *forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);44 return true;45 }46 47 if (mdp->ops.setup_clk_force_ctrl) {48 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);49 return true;50 }51 52 return false;53}54 55/**56 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface57 * @phys_enc: Pointer to physical encoder58 */59static void dpu_encoder_phys_wb_set_ot_limit(60 struct dpu_encoder_phys *phys_enc)61{62 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;63 struct dpu_vbif_set_ot_params ot_params;64 bool forced_on = false;65 66 memset(&ot_params, 0, sizeof(ot_params));67 ot_params.xin_id = hw_wb->caps->xin_id;68 ot_params.num = hw_wb->idx - WB_0;69 ot_params.width = phys_enc->cached_mode.hdisplay;70 ot_params.height = phys_enc->cached_mode.vdisplay;71 ot_params.is_wfd = true;72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);73 ot_params.vbif_idx = hw_wb->caps->vbif_idx;74 ot_params.rd = false;75 76 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,77 true, &forced_on))78 return;79 80 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);81 82 if (forced_on)83 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,84 false, &forced_on);85}86 87/**88 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback89 * @phys_enc: Pointer to physical encoder90 */91static void dpu_encoder_phys_wb_set_qos_remap(92 struct dpu_encoder_phys *phys_enc)93{94 struct dpu_hw_wb *hw_wb;95 struct dpu_vbif_set_qos_params qos_params;96 bool forced_on = false;97 98 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {99 DPU_ERROR("invalid arguments\n");100 return;101 }102 103 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {104 DPU_ERROR("invalid writeback hardware\n");105 return;106 }107 108 hw_wb = phys_enc->hw_wb;109 110 memset(&qos_params, 0, sizeof(qos_params));111 qos_params.vbif_idx = hw_wb->caps->vbif_idx;112 qos_params.xin_id = hw_wb->caps->xin_id;113 qos_params.num = hw_wb->idx - WB_0;114 qos_params.is_rt = false;115 116 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",117 qos_params.num,118 qos_params.vbif_idx,119 qos_params.xin_id, qos_params.is_rt);120 121 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,122 true, &forced_on))123 return;124 125 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);126 127 if (forced_on)128 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,129 false, &forced_on);130}131 132/**133 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback134 * @phys_enc: Pointer to physical encoder135 */136static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)137{138 struct dpu_hw_wb *hw_wb;139 struct dpu_hw_qos_cfg qos_cfg;140 const struct dpu_mdss_cfg *catalog;141 const struct dpu_qos_lut_tbl *qos_lut_tb;142 143 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {144 DPU_ERROR("invalid parameter(s)\n");145 return;146 }147 148 catalog = phys_enc->dpu_kms->catalog;149 150 hw_wb = phys_enc->hw_wb;151 152 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));153 qos_cfg.danger_safe_en = true;154 qos_cfg.danger_lut =155 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];156 157 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];158 159 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];160 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);161 162 if (hw_wb->ops.setup_qos_lut)163 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);164}165 166/**167 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer168 * @phys_enc: Pointer to physical encoder169 * @fb: Pointer to output framebuffer170 */171static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,172 struct drm_framebuffer *fb)173{174 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);175 struct dpu_hw_wb *hw_wb;176 struct dpu_hw_wb_cfg *wb_cfg;177 178 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {179 DPU_ERROR("invalid encoder\n");180 return;181 }182 183 hw_wb = phys_enc->hw_wb;184 wb_cfg = &wb_enc->wb_cfg;185 186 wb_cfg->intf_mode = phys_enc->intf_mode;187 wb_cfg->roi.x1 = 0;188 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;189 wb_cfg->roi.y1 = 0;190 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;191 192 if (hw_wb->ops.setup_roi)193 hw_wb->ops.setup_roi(hw_wb, wb_cfg);194 195 if (hw_wb->ops.setup_outformat)196 hw_wb->ops.setup_outformat(hw_wb, wb_cfg);197 198 if (hw_wb->ops.setup_cdp) {199 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;200 201 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,202 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);203 }204 205 if (hw_wb->ops.setup_outaddress)206 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);207}208 209/**210 * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path211 * @phys_enc:Pointer to physical encoder212 */213static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)214{215 struct dpu_hw_wb *hw_wb;216 struct dpu_hw_ctl *ctl;217 struct dpu_hw_cdm *hw_cdm;218 219 if (!phys_enc) {220 DPU_ERROR("invalid encoder\n");221 return;222 }223 224 hw_wb = phys_enc->hw_wb;225 ctl = phys_enc->hw_ctl;226 hw_cdm = phys_enc->hw_cdm;227 228 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&229 (phys_enc->hw_ctl &&230 phys_enc->hw_ctl->ops.setup_intf_cfg)) {231 struct dpu_hw_intf_cfg intf_cfg = {0};232 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;233 enum dpu_3d_blend_mode mode_3d;234 235 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);236 237 intf_cfg.intf = DPU_NONE;238 intf_cfg.wb = hw_wb->idx;239 240 if (mode_3d && hw_pp && hw_pp->merge_3d)241 intf_cfg.merge_3d = hw_pp->merge_3d->idx;242 243 if (hw_cdm)244 intf_cfg.cdm = hw_cdm->idx;245 246 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)247 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,248 mode_3d);249 250 /* setup which pp blk will connect to this wb */251 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)252 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,253 phys_enc->hw_pp->idx);254 255 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);256 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {257 struct dpu_hw_intf_cfg intf_cfg = {0};258 259 intf_cfg.intf = DPU_NONE;260 intf_cfg.wb = hw_wb->idx;261 intf_cfg.mode_3d =262 dpu_encoder_helper_get_3d_blend_mode(phys_enc);263 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);264 }265}266 267/**268 * _dpu_encoder_phys_wb_update_flush - flush hardware update269 * @phys_enc: Pointer to physical encoder270 */271static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)272{273 struct dpu_hw_wb *hw_wb;274 struct dpu_hw_ctl *hw_ctl;275 struct dpu_hw_pingpong *hw_pp;276 struct dpu_hw_cdm *hw_cdm;277 u32 pending_flush = 0;278 u32 mode_3d;279 280 if (!phys_enc)281 return;282 283 hw_wb = phys_enc->hw_wb;284 hw_pp = phys_enc->hw_pp;285 hw_ctl = phys_enc->hw_ctl;286 hw_cdm = phys_enc->hw_cdm;287 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);288 289 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);290 291 if (!hw_ctl) {292 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);293 return;294 }295 296 if (hw_ctl->ops.update_pending_flush_wb)297 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);298 299 if (mode_3d && hw_ctl->ops.update_pending_flush_merge_3d &&300 hw_pp && hw_pp->merge_3d)301 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,302 hw_pp->merge_3d->idx);303 304 if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)305 hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);306 307 if (hw_ctl->ops.get_pending_flush)308 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);309 310 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",311 hw_ctl->idx - CTL_0, pending_flush,312 hw_wb->idx - WB_0);313}314 315/**316 * dpu_encoder_phys_wb_setup - setup writeback encoder317 * @phys_enc: Pointer to physical encoder318 */319static void dpu_encoder_phys_wb_setup(320 struct dpu_encoder_phys *phys_enc)321{322 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;323 struct drm_display_mode mode = phys_enc->cached_mode;324 struct drm_framebuffer *fb = NULL;325 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);326 struct drm_writeback_job *wb_job;327 const struct msm_format *format;328 const struct msm_format *dpu_fmt;329 330 wb_job = wb_enc->wb_job;331 format = msm_framebuffer_format(wb_enc->wb_job->fb);332 dpu_fmt = mdp_get_format(&phys_enc->dpu_kms->base, format->pixel_format, wb_job->fb->modifier);333 334 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",335 hw_wb->idx - WB_0, mode.name,336 mode.hdisplay, mode.vdisplay);337 338 dpu_encoder_phys_wb_set_ot_limit(phys_enc);339 340 dpu_encoder_phys_wb_set_qos_remap(phys_enc);341 342 dpu_encoder_phys_wb_set_qos(phys_enc);343 344 dpu_encoder_phys_wb_setup_fb(phys_enc, fb);345 346 dpu_encoder_helper_phys_setup_cdm(phys_enc, dpu_fmt, CDM_CDWN_OUTPUT_WB);347 348 dpu_encoder_phys_wb_setup_ctl(phys_enc);349}350 351/**352 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler353 * @arg: Pointer to writeback encoder354 */355static void dpu_encoder_phys_wb_done_irq(void *arg)356{357 struct dpu_encoder_phys *phys_enc = arg;358 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);359 360 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;361 unsigned long lock_flags;362 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;363 364 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);365 366 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);367 368 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);369 370 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);371 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);372 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);373 374 if (wb_enc->wb_conn)375 drm_writeback_signal_completion(wb_enc->wb_conn, 0);376 377 /* Signal any waiting atomic commit thread */378 wake_up_all(&phys_enc->pending_kickoff_wq);379}380 381/**382 * dpu_encoder_phys_wb_irq_enable - irq control of WB383 * @phys: Pointer to physical encoder384 */385static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys)386{387 388 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);389 390 if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1)391 dpu_core_irq_register_callback(phys->dpu_kms,392 phys->irq[INTR_IDX_WB_DONE],393 dpu_encoder_phys_wb_done_irq,394 phys);395}396 397/**398 * dpu_encoder_phys_wb_irq_disable - irq control of WB399 * @phys: Pointer to physical encoder400 */401static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)402{403 404 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);405 406 if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0)407 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);408}409 410static void dpu_encoder_phys_wb_atomic_mode_set(411 struct dpu_encoder_phys *phys_enc,412 struct drm_crtc_state *crtc_state,413 struct drm_connector_state *conn_state)414{415 416 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;417}418 419static void _dpu_encoder_phys_wb_handle_wbdone_timeout(420 struct dpu_encoder_phys *phys_enc)421{422 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);423 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;424 425 wb_enc->wb_done_timeout_cnt++;426 427 if (wb_enc->wb_done_timeout_cnt == 1)428 msm_disp_snapshot_state(phys_enc->parent->dev);429 430 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);431 432 /* request a ctl reset before the next kickoff */433 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;434 435 if (wb_enc->wb_conn)436 drm_writeback_signal_completion(wb_enc->wb_conn, 0);437 438 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);439}440 441/**442 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed443 * @phys_enc: Pointer to physical encoder444 */445static int dpu_encoder_phys_wb_wait_for_commit_done(446 struct dpu_encoder_phys *phys_enc)447{448 unsigned long ret;449 struct dpu_encoder_wait_info wait_info;450 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);451 452 wait_info.wq = &phys_enc->pending_kickoff_wq;453 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;454 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;455 456 ret = dpu_encoder_helper_wait_for_irq(phys_enc,457 phys_enc->irq[INTR_IDX_WB_DONE],458 dpu_encoder_phys_wb_done_irq, &wait_info);459 if (ret == -ETIMEDOUT)460 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);461 else if (!ret)462 wb_enc->wb_done_timeout_cnt = 0;463 464 return ret;465}466 467/**468 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing469 * @phys_enc: Pointer to physical encoder470 * Returns: Zero on success471 */472static void dpu_encoder_phys_wb_prepare_for_kickoff(473 struct dpu_encoder_phys *phys_enc)474{475 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);476 struct drm_connector *drm_conn;477 struct drm_connector_state *state;478 479 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);480 481 if (!wb_enc->wb_conn || !wb_enc->wb_job) {482 DPU_ERROR("invalid wb_conn or wb_job\n");483 return;484 }485 486 drm_conn = &wb_enc->wb_conn->base;487 state = drm_conn->state;488 489 if (wb_enc->wb_conn && wb_enc->wb_job)490 drm_writeback_queue_job(wb_enc->wb_conn, state);491 492 dpu_encoder_phys_wb_setup(phys_enc);493 494 _dpu_encoder_phys_wb_update_flush(phys_enc);495}496 497/**498 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing499 * @phys_enc: Pointer to physical encoder500 */501static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)502{503 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);504 return false;505}506 507/**508 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing509 * @phys_enc: Pointer to physical encoder510 */511static void dpu_encoder_phys_wb_handle_post_kickoff(512 struct dpu_encoder_phys *phys_enc)513{514 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);515 516}517 518/**519 * dpu_encoder_phys_wb_enable - enable writeback encoder520 * @phys_enc: Pointer to physical encoder521 */522static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)523{524 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);525 phys_enc->enable_state = DPU_ENC_ENABLED;526}527/**528 * dpu_encoder_phys_wb_disable - disable writeback encoder529 * @phys_enc: Pointer to physical encoder530 */531static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)532{533 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;534 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;535 536 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);537 538 if (phys_enc->enable_state == DPU_ENC_DISABLED) {539 DPU_ERROR("encoder is already disabled\n");540 return;541 }542 543 /* reset h/w before final flush */544 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);545 546 /*547 * New CTL reset sequence from 5.0 MDP onwards.548 * If has_3d_merge_reset is not set, legacy reset549 * sequence is executed.550 *551 * Legacy reset sequence has not been implemented yet.552 * Any target earlier than SM8150 will need it and when553 * WB support is added to those targets will need to add554 * the legacy teardown sequence as well.555 */556 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))557 dpu_encoder_helper_phys_cleanup(phys_enc);558 559 phys_enc->enable_state = DPU_ENC_DISABLED;560}561 562static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,563 struct drm_writeback_job *job)564{565 const struct msm_format *format;566 struct msm_gem_address_space *aspace;567 struct dpu_hw_wb_cfg *wb_cfg;568 int ret;569 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);570 571 if (!job->fb)572 return;573 574 wb_enc->wb_job = job;575 wb_enc->wb_conn = job->connector;576 aspace = phys_enc->dpu_kms->base.aspace;577 578 wb_cfg = &wb_enc->wb_cfg;579 580 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));581 582 ret = msm_framebuffer_prepare(job->fb, aspace, false);583 if (ret) {584 DPU_ERROR("prep fb failed, %d\n", ret);585 return;586 }587 588 format = msm_framebuffer_format(job->fb);589 590 wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base,591 format->pixel_format, job->fb->modifier);592 if (!wb_cfg->dest.format) {593 /* this error should be detected during atomic_check */594 DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format);595 return;596 }597 598 ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest);599 if (ret) {600 DPU_DEBUG("failed to populate layout %d\n", ret);601 return;602 }603 604 wb_cfg->dest.width = job->fb->width;605 wb_cfg->dest.height = job->fb->height;606 wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;607 608 if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&609 (wb_cfg->dest.format->element[0] == C1_B_Cb))610 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);611 612 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",613 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],614 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);615 616 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",617 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],618 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);619}620 621static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,622 struct drm_writeback_job *job)623{624 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);625 struct msm_gem_address_space *aspace;626 627 if (!job->fb)628 return;629 630 aspace = phys_enc->dpu_kms->base.aspace;631 632 msm_framebuffer_cleanup(job->fb, aspace, false);633 wb_enc->wb_job = NULL;634 wb_enc->wb_conn = NULL;635}636 637static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)638{639 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);640 641 if (wb_enc->wb_job)642 return true;643 else644 return false;645}646 647/**648 * dpu_encoder_phys_wb_init_ops - initialize writeback operations649 * @ops: Pointer to encoder operation table650 */651static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)652{653 ops->is_master = dpu_encoder_phys_wb_is_master;654 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;655 ops->enable = dpu_encoder_phys_wb_enable;656 ops->disable = dpu_encoder_phys_wb_disable;657 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;658 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;659 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;660 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;661 ops->trigger_start = dpu_encoder_helper_trigger_start;662 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;663 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;664 ops->irq_enable = dpu_encoder_phys_wb_irq_enable;665 ops->irq_disable = dpu_encoder_phys_wb_irq_disable;666 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;667 668}669 670/**671 * dpu_encoder_phys_wb_init - initialize writeback encoder672 * @dev: Corresponding device for devres management673 * @p: Pointer to init info structure with initialization params674 */675struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,676 struct dpu_enc_phys_init_params *p)677{678 struct dpu_encoder_phys *phys_enc = NULL;679 struct dpu_encoder_phys_wb *wb_enc = NULL;680 681 DPU_DEBUG("\n");682 683 if (!p || !p->parent) {684 DPU_ERROR("invalid params\n");685 return ERR_PTR(-EINVAL);686 }687 688 wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);689 if (!wb_enc) {690 DPU_ERROR("failed to allocate wb phys_enc enc\n");691 return ERR_PTR(-ENOMEM);692 }693 694 phys_enc = &wb_enc->base;695 696 dpu_encoder_phys_init(phys_enc, p);697 698 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);699 phys_enc->intf_mode = INTF_MODE_WB_LINE;700 701 atomic_set(&wb_enc->wbirq_refcount, 0);702 703 wb_enc->wb_done_timeout_cnt = 0;704 705 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);706 707 return phys_enc;708}709