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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#ifndef _DPU_HW_CTL_H7#define _DPU_HW_CTL_H8 9#include "dpu_hw_mdss.h"10#include "dpu_hw_util.h"11#include "dpu_hw_catalog.h"12#include "dpu_hw_sspp.h"13 14/**15 * dpu_ctl_mode_sel: Interface mode selection16 * DPU_CTL_MODE_SEL_VID: Video mode interface17 * DPU_CTL_MODE_SEL_CMD: Command mode interface18 */19enum dpu_ctl_mode_sel {20 DPU_CTL_MODE_SEL_VID = 0,21 DPU_CTL_MODE_SEL_CMD22};23 24struct dpu_hw_ctl;25/**26 * struct dpu_hw_stage_cfg - blending stage cfg27 * @stage : SSPP_ID at each stage28 * @multirect_index: index of the rectangle of SSPP.29 */30struct dpu_hw_stage_cfg {31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];32 enum dpu_sspp_multirect_index multirect_index33 [DPU_STAGE_MAX][PIPES_PER_STAGE];34};35 36/**37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface38 * @intf : Interface id39 * @mode_3d: 3d mux configuration40 * @merge_3d: 3d merge block used41 * @intf_mode_sel: Interface mode, cmd / vid42 * @cdm: CDM block used43 * @stream_sel: Stream selection for multi-stream interfaces44 * @dsc: DSC BIT masks used45 */46struct dpu_hw_intf_cfg {47 enum dpu_intf intf;48 enum dpu_wb wb;49 enum dpu_3d_blend_mode mode_3d;50 enum dpu_merge_3d merge_3d;51 enum dpu_ctl_mode_sel intf_mode_sel;52 enum dpu_cdm cdm;53 int stream_sel;54 unsigned int dsc;55};56 57/**58 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions59 * Assumption is these functions will be called after clocks are enabled60 */61struct dpu_hw_ctl_ops {62 /**63 * kickoff hw operation for Sw controlled interfaces64 * DSI cmd mode and WB interface are SW controlled65 * @ctx : ctl path ctx pointer66 */67 void (*trigger_start)(struct dpu_hw_ctl *ctx);68 69 /**70 * check if the ctl is started71 * @ctx : ctl path ctx pointer72 * @Return: true if started, false if stopped73 */74 bool (*is_started)(struct dpu_hw_ctl *ctx);75 76 /**77 * kickoff prepare is in progress hw operation for sw78 * controlled interfaces: DSI cmd mode and WB interface79 * are SW controlled80 * @ctx : ctl path ctx pointer81 */82 void (*trigger_pending)(struct dpu_hw_ctl *ctx);83 84 /**85 * Clear the value of the cached pending_flush_mask86 * No effect on hardware.87 * Required to be implemented.88 * @ctx : ctl path ctx pointer89 */90 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);91 92 /**93 * Query the value of the cached pending_flush_mask94 * No effect on hardware95 * @ctx : ctl path ctx pointer96 */97 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);98 99 /**100 * OR in the given flushbits to the cached pending_flush_mask101 * No effect on hardware102 * @ctx : ctl path ctx pointer103 * @flushbits : module flushmask104 */105 void (*update_pending_flush)(struct dpu_hw_ctl *ctx,106 u32 flushbits);107 108 /**109 * OR in the given flushbits to the cached pending_(wb_)flush_mask110 * No effect on hardware111 * @ctx : ctl path ctx pointer112 * @blk : writeback block index113 */114 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,115 enum dpu_wb blk);116 117 /**118 * OR in the given flushbits to the cached pending_(intf_)flush_mask119 * No effect on hardware120 * @ctx : ctl path ctx pointer121 * @blk : interface block index122 */123 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,124 enum dpu_intf blk);125 126 /**127 * OR in the given flushbits to the cached pending_(periph_)flush_mask128 * No effect on hardware129 * @ctx : ctl path ctx pointer130 * @blk : interface block index131 */132 void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,133 enum dpu_intf blk);134 135 /**136 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask137 * No effect on hardware138 * @ctx : ctl path ctx pointer139 * @blk : interface block index140 */141 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,142 enum dpu_merge_3d blk);143 144 /**145 * OR in the given flushbits to the cached pending_flush_mask146 * No effect on hardware147 * @ctx : ctl path ctx pointer148 * @blk : SSPP block index149 */150 void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx,151 enum dpu_sspp blk);152 153 /**154 * OR in the given flushbits to the cached pending_flush_mask155 * No effect on hardware156 * @ctx : ctl path ctx pointer157 * @blk : LM block index158 */159 void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx,160 enum dpu_lm blk);161 162 /**163 * OR in the given flushbits to the cached pending_flush_mask164 * No effect on hardware165 * @ctx : ctl path ctx pointer166 * @blk : DSPP block index167 * @dspp_sub_blk : DSPP sub-block index168 */169 void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,170 enum dpu_dspp blk, u32 dspp_sub_blk);171 172 /**173 * OR in the given flushbits to the cached pending_(dsc_)flush_mask174 * No effect on hardware175 * @ctx: ctl path ctx pointer176 * @blk: interface block index177 */178 void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,179 enum dpu_dsc blk);180 181 /**182 * OR in the given flushbits to the cached pending_(cdm_)flush_mask183 * No effect on hardware184 * @ctx: ctl path ctx pointer185 * @cdm_num: idx of cdm to be flushed186 */187 void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);188 189 /**190 * Write the value of the pending_flush_mask to hardware191 * @ctx : ctl path ctx pointer192 */193 void (*trigger_flush)(struct dpu_hw_ctl *ctx);194 195 /**196 * Read the value of the flush register197 * @ctx : ctl path ctx pointer198 * @Return: value of the ctl flush register.199 */200 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);201 202 /**203 * Setup ctl_path interface config204 * @ctx205 * @cfg : interface config structure pointer206 */207 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,208 struct dpu_hw_intf_cfg *cfg);209 210 /**211 * reset ctl_path interface config212 * @ctx : ctl path ctx pointer213 * @cfg : interface config structure pointer214 */215 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,216 struct dpu_hw_intf_cfg *cfg);217 218 int (*reset)(struct dpu_hw_ctl *c);219 220 /*221 * wait_reset_status - checks ctl reset status222 * @ctx : ctl path ctx pointer223 *224 * This function checks the ctl reset status bit.225 * If the reset bit is set, it keeps polling the status till the hw226 * reset is complete.227 * Returns: 0 on success or -error if reset incomplete within interval228 */229 int (*wait_reset_status)(struct dpu_hw_ctl *ctx);230 231 /**232 * Set all blend stages to disabled233 * @ctx : ctl path ctx pointer234 */235 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);236 237 /**238 * Configure layer mixer to pipe configuration239 * @ctx : ctl path ctx pointer240 * @lm : layer mixer enumeration241 * @cfg : blend stage configuration242 */243 void (*setup_blendstage)(struct dpu_hw_ctl *ctx,244 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);245 246 void (*set_active_pipes)(struct dpu_hw_ctl *ctx,247 unsigned long *fetch_active);248};249 250/**251 * struct dpu_hw_ctl : CTL PATH driver object252 * @base: hardware block base structure253 * @hw: block register map object254 * @idx: control path index255 * @caps: control path capabilities256 * @mixer_count: number of mixers257 * @mixer_hw_caps: mixer hardware capabilities258 * @pending_flush_mask: storage for pending ctl_flush managed via ops259 * @pending_intf_flush_mask: pending INTF flush260 * @pending_wb_flush_mask: pending WB flush261 * @pending_dsc_flush_mask: pending DSC flush262 * @pending_cdm_flush_mask: pending CDM flush263 * @ops: operation list264 */265struct dpu_hw_ctl {266 struct dpu_hw_blk base;267 struct dpu_hw_blk_reg_map hw;268 269 /* ctl path */270 int idx;271 const struct dpu_ctl_cfg *caps;272 int mixer_count;273 const struct dpu_lm_cfg *mixer_hw_caps;274 u32 pending_flush_mask;275 u32 pending_intf_flush_mask;276 u32 pending_wb_flush_mask;277 u32 pending_periph_flush_mask;278 u32 pending_merge_3d_flush_mask;279 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];280 u32 pending_dsc_flush_mask;281 u32 pending_cdm_flush_mask;282 283 /* ops */284 struct dpu_hw_ctl_ops ops;285};286 287/**288 * dpu_hw_ctl - convert base object dpu_hw_base to container289 * @hw: Pointer to base hardware block290 * return: Pointer to hardware block container291 */292static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)293{294 return container_of(hw, struct dpu_hw_ctl, base);295}296 297/**298 * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.299 * Should be called before accessing any ctl_path register.300 * @dev: Corresponding device for devres management301 * @cfg: ctl_path catalog entry for which driver object is required302 * @addr: mapped register io address of MDP303 * @mixer_count: Number of mixers in @mixer304 * @mixer: Pointer to an array of Layer Mixers defined in the catalog305 */306struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,307 const struct dpu_ctl_cfg *cfg,308 void __iomem *addr,309 u32 mixer_count,310 const struct dpu_lm_cfg *mixer);311 312#endif /*_DPU_HW_CTL_H */313