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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.5 */6 7#include <drm/drm_managed.h>8 9#include "dpu_kms.h"10#include "dpu_hw_catalog.h"11#include "dpu_hwio.h"12#include "dpu_hw_lm.h"13#include "dpu_hw_mdss.h"14 15#define LM_OP_MODE 0x0016#define LM_OUT_SIZE 0x0417#define LM_BORDER_COLOR_0 0x0818#define LM_BORDER_COLOR_1 0x01019 20/* These register are offset to mixer base + stage base */21#define LM_BLEND0_OP 0x0022#define LM_BLEND0_CONST_ALPHA 0x0423#define LM_FG_COLOR_FILL_COLOR_0 0x0824#define LM_FG_COLOR_FILL_COLOR_1 0x0C25#define LM_FG_COLOR_FILL_SIZE 0x1026#define LM_FG_COLOR_FILL_XY 0x1427 28#define LM_BLEND0_FG_ALPHA 0x0429#define LM_BLEND0_BG_ALPHA 0x0830 31#define LM_MISR_CTRL 0x31032#define LM_MISR_SIGNATURE 0x31433 34 35/**36 * _stage_offset(): returns the relative offset of the blend registers37 * for the stage to be setup38 * @ctx: mixer ctx contains the mixer to be programmed39 * @stage: stage index to setup40 */41static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)42{43 const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;44 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages)45 return sblk->blendstage_base[stage - DPU_STAGE_0];46 47 return -EINVAL;48}49 50static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,51 struct dpu_hw_mixer_cfg *mixer)52{53 struct dpu_hw_blk_reg_map *c = &ctx->hw;54 u32 outsize;55 u32 op_mode;56 57 op_mode = DPU_REG_READ(c, LM_OP_MODE);58 59 outsize = mixer->out_height << 16 | mixer->out_width;60 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);61 62 /* SPLIT_LEFT_RIGHT */63 if (mixer->right_mixer)64 op_mode |= BIT(31);65 else66 op_mode &= ~BIT(31);67 DPU_REG_WRITE(c, LM_OP_MODE, op_mode);68}69 70static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,71 struct dpu_mdss_color *color,72 u8 border_en)73{74 struct dpu_hw_blk_reg_map *c = &ctx->hw;75 76 if (border_en) {77 DPU_REG_WRITE(c, LM_BORDER_COLOR_0,78 (color->color_0 & 0xFFF) |79 ((color->color_1 & 0xFFF) << 0x10));80 DPU_REG_WRITE(c, LM_BORDER_COLOR_1,81 (color->color_2 & 0xFFF) |82 ((color->color_3 & 0xFFF) << 0x10));83 }84}85 86static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)87{88 dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);89}90 91static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)92{93 return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);94}95 96static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,97 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)98{99 struct dpu_hw_blk_reg_map *c = &ctx->hw;100 int stage_off;101 u32 const_alpha;102 103 if (stage == DPU_STAGE_BASE)104 return;105 106 stage_off = _stage_offset(ctx, stage);107 if (WARN_ON(stage_off < 0))108 return;109 110 const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);111 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);112 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);113}114 115static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,116 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)117{118 struct dpu_hw_blk_reg_map *c = &ctx->hw;119 int stage_off;120 121 if (stage == DPU_STAGE_BASE)122 return;123 124 stage_off = _stage_offset(ctx, stage);125 if (WARN_ON(stage_off < 0))126 return;127 128 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);129 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);130 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);131}132 133static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,134 uint32_t mixer_op_mode)135{136 struct dpu_hw_blk_reg_map *c = &ctx->hw;137 int op_mode;138 139 /* read the existing op_mode configuration */140 op_mode = DPU_REG_READ(c, LM_OP_MODE);141 142 op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;143 144 DPU_REG_WRITE(c, LM_OP_MODE, op_mode);145}146 147static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops,148 unsigned long features)149{150 ops->setup_mixer_out = dpu_hw_lm_setup_out;151 if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features))152 ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;153 else154 ops->setup_blend_config = dpu_hw_lm_setup_blend_config;155 ops->setup_alpha_out = dpu_hw_lm_setup_color3;156 ops->setup_border_color = dpu_hw_lm_setup_border_color;157 ops->setup_misr = dpu_hw_lm_setup_misr;158 ops->collect_misr = dpu_hw_lm_collect_misr;159}160 161struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,162 const struct dpu_lm_cfg *cfg,163 void __iomem *addr)164{165 struct dpu_hw_mixer *c;166 167 if (cfg->pingpong == PINGPONG_NONE) {168 DPU_DEBUG("skip mixer %d without pingpong\n", cfg->id);169 return NULL;170 }171 172 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);173 if (!c)174 return ERR_PTR(-ENOMEM);175 176 c->hw.blk_addr = addr + cfg->base;177 c->hw.log_mask = DPU_DBG_MASK_LM;178 179 /* Assign ops */180 c->idx = cfg->id;181 c->cap = cfg;182 _setup_mixer_ops(&c->ops, c->cap->features);183 184 return c;185}186