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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.3 */4 5#ifndef _DPU_HW_MDSS_H6#define _DPU_HW_MDSS_H7 8#include <linux/kernel.h>9#include <linux/err.h>10 11#include "msm_drv.h"12 13#include "disp/mdp_format.h"14 15#define DPU_DBG_NAME "dpu"16 17#define DPU_NONE 018 19#ifndef DPU_CSC_MATRIX_COEFF_SIZE20#define DPU_CSC_MATRIX_COEFF_SIZE 921#endif22 23#ifndef DPU_CSC_CLAMP_SIZE24#define DPU_CSC_CLAMP_SIZE 625#endif26 27#ifndef DPU_CSC_BIAS_SIZE28#define DPU_CSC_BIAS_SIZE 329#endif30 31#ifndef DPU_MAX_PLANES32#define DPU_MAX_PLANES 433#endif34 35#define PIPES_PER_STAGE 236#ifndef DPU_MAX_DE_CURVES37#define DPU_MAX_DE_CURVES 338#endif39 40#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)41#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)42#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)43#define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)44#define DPU_BLEND_FG_INV_ALPHA (1 << 2)45#define DPU_BLEND_FG_MOD_ALPHA (1 << 3)46#define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4)47#define DPU_BLEND_FG_TRANSP_EN (1 << 5)48#define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8)49#define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8)50#define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)51#define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)52#define DPU_BLEND_BG_INV_ALPHA (1 << 10)53#define DPU_BLEND_BG_MOD_ALPHA (1 << 11)54#define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)55#define DPU_BLEND_BG_TRANSP_EN (1 << 13)56 57enum dpu_vsync_source {58 DPU_VSYNC_SOURCE_GPIO_0,59 DPU_VSYNC_SOURCE_GPIO_1,60 DPU_VSYNC_SOURCE_GPIO_2,61 DPU_VSYNC_SOURCE_INTF_0 = 3,62 DPU_VSYNC_SOURCE_INTF_1,63 DPU_VSYNC_SOURCE_INTF_2,64 DPU_VSYNC_SOURCE_INTF_3,65 DPU_VSYNC_SOURCE_WD_TIMER_4 = 11,66 DPU_VSYNC_SOURCE_WD_TIMER_3,67 DPU_VSYNC_SOURCE_WD_TIMER_2,68 DPU_VSYNC_SOURCE_WD_TIMER_1,69 DPU_VSYNC_SOURCE_WD_TIMER_0,70};71 72enum dpu_hw_blk_type {73 DPU_HW_BLK_TOP = 0,74 DPU_HW_BLK_SSPP,75 DPU_HW_BLK_LM,76 DPU_HW_BLK_CTL,77 DPU_HW_BLK_PINGPONG,78 DPU_HW_BLK_INTF,79 DPU_HW_BLK_WB,80 DPU_HW_BLK_DSPP,81 DPU_HW_BLK_MERGE_3D,82 DPU_HW_BLK_DSC,83 DPU_HW_BLK_CDM,84 DPU_HW_BLK_MAX,85};86 87enum dpu_sspp {88 SSPP_NONE,89 SSPP_VIG0,90 SSPP_VIG1,91 SSPP_VIG2,92 SSPP_VIG3,93 SSPP_RGB0,94 SSPP_RGB1,95 SSPP_RGB2,96 SSPP_RGB3,97 SSPP_DMA0,98 SSPP_DMA1,99 SSPP_DMA2,100 SSPP_DMA3,101 SSPP_DMA4,102 SSPP_DMA5,103 SSPP_CURSOR0,104 SSPP_CURSOR1,105 SSPP_MAX106};107 108enum dpu_sspp_type {109 SSPP_TYPE_VIG,110 SSPP_TYPE_RGB,111 SSPP_TYPE_DMA,112 SSPP_TYPE_CURSOR,113 SSPP_TYPE_MAX114};115 116enum dpu_lm {117 LM_0 = 1,118 LM_1,119 LM_2,120 LM_3,121 LM_4,122 LM_5,123 LM_6,124 LM_MAX125};126 127enum dpu_stage {128 DPU_STAGE_BASE = 0,129 DPU_STAGE_0,130 DPU_STAGE_1,131 DPU_STAGE_2,132 DPU_STAGE_3,133 DPU_STAGE_4,134 DPU_STAGE_5,135 DPU_STAGE_6,136 DPU_STAGE_7,137 DPU_STAGE_8,138 DPU_STAGE_9,139 DPU_STAGE_10,140 DPU_STAGE_MAX141};142enum dpu_dspp {143 DSPP_0 = 1,144 DSPP_1,145 DSPP_2,146 DSPP_3,147 DSPP_MAX148};149 150enum dpu_ctl {151 CTL_0 = 1,152 CTL_1,153 CTL_2,154 CTL_3,155 CTL_4,156 CTL_5,157 CTL_MAX158};159 160enum dpu_dsc {161 DSC_NONE = 0,162 DSC_0,163 DSC_1,164 DSC_2,165 DSC_3,166 DSC_4,167 DSC_5,168 DSC_MAX169};170 171enum dpu_cdm {172 CDM_0 = 1,173 CDM_MAX174};175 176enum dpu_pingpong {177 PINGPONG_NONE,178 PINGPONG_0,179 PINGPONG_1,180 PINGPONG_2,181 PINGPONG_3,182 PINGPONG_4,183 PINGPONG_5,184 PINGPONG_6,185 PINGPONG_7,186 PINGPONG_8,187 PINGPONG_9,188 PINGPONG_S0,189 PINGPONG_MAX190};191 192enum dpu_merge_3d {193 MERGE_3D_0 = 1,194 MERGE_3D_1,195 MERGE_3D_2,196 MERGE_3D_3,197 MERGE_3D_4,198 MERGE_3D_MAX199};200 201enum dpu_intf {202 INTF_0 = 1,203 INTF_1,204 INTF_2,205 INTF_3,206 INTF_4,207 INTF_5,208 INTF_6,209 INTF_7,210 INTF_8,211 INTF_MAX212};213 214/*215 * Historically these values correspond to the values written to the216 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP217 * generations this register is NOP, but we keep the values for historical218 * reasons.219 */220enum dpu_intf_type {221 INTF_NONE = 0x0,222 INTF_DSI = 0x1,223 INTF_HDMI = 0x3,224 INTF_LCDC = 0x5,225 /* old eDP found on 8x74 and 8x84 */226 INTF_EDP = 0x9,227 /* both DP and eDP, handled by the new DP driver */228 INTF_DP = 0xa,229 230 /* virtual interfaces */231 INTF_WB = 0x100,232};233 234enum dpu_intf_mode {235 INTF_MODE_NONE = 0,236 INTF_MODE_CMD,237 INTF_MODE_VIDEO,238 INTF_MODE_WB_BLOCK,239 INTF_MODE_WB_LINE,240 INTF_MODE_MAX241};242 243enum dpu_wb {244 WB_0 = 1,245 WB_1,246 WB_2,247 WB_3,248 WB_MAX249};250 251enum dpu_cwb {252 CWB_0 = 0x1,253 CWB_1,254 CWB_2,255 CWB_3,256 CWB_MAX257};258 259enum dpu_wd_timer {260 WD_TIMER_0 = 0x1,261 WD_TIMER_1,262 WD_TIMER_2,263 WD_TIMER_3,264 WD_TIMER_4,265 WD_TIMER_5,266 WD_TIMER_MAX267};268 269enum dpu_vbif {270 VBIF_RT,271 VBIF_NRT,272 VBIF_MAX,273};274 275/**276 * enum dpu_3d_blend_mode277 * Desribes how the 3d data is blended278 * @BLEND_3D_NONE : 3d blending not enabled279 * @BLEND_3D_FRAME_INT : Frame interleaving280 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving281 * @BLEND_3D_V_ROW_INT : vertical row interleaving282 * @BLEND_3D_COL_INT : column interleaving283 * @BLEND_3D_MAX :284 */285enum dpu_3d_blend_mode {286 BLEND_3D_NONE = 0,287 BLEND_3D_FRAME_INT,288 BLEND_3D_H_ROW_INT,289 BLEND_3D_V_ROW_INT,290 BLEND_3D_COL_INT,291 BLEND_3D_MAX292};293 294/**295 * struct dpu_hw_fmt_layout - format information of the source pixel data296 * @format: pixel format parameters297 * @num_planes: number of planes (including meta data planes)298 * @width: image width299 * @height: image height300 * @total_size: total size in bytes301 * @plane_addr: address of each plane302 * @plane_size: length of each plane303 * @plane_pitch: pitch of each plane304 */305struct dpu_hw_fmt_layout {306 const struct msm_format *format;307 uint32_t num_planes;308 uint32_t width;309 uint32_t height;310 uint32_t total_size;311 uint32_t plane_addr[DPU_MAX_PLANES];312 uint32_t plane_size[DPU_MAX_PLANES];313 uint32_t plane_pitch[DPU_MAX_PLANES];314};315 316struct dpu_csc_cfg {317 /* matrix coefficients in S15.16 format */318 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];319 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];320 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];321 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];322 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];323};324 325/**326 * struct dpu_mdss_color - mdss color description327 * color 0 : green328 * color 1 : blue329 * color 2 : red330 * color 3 : alpha331 */332struct dpu_mdss_color {333 u32 color_0;334 u32 color_1;335 u32 color_2;336 u32 color_3;337};338 339/*340 * Define bit masks for h/w logging.341 */342#define DPU_DBG_MASK_NONE (1 << 0)343#define DPU_DBG_MASK_INTF (1 << 1)344#define DPU_DBG_MASK_LM (1 << 2)345#define DPU_DBG_MASK_CTL (1 << 3)346#define DPU_DBG_MASK_PINGPONG (1 << 4)347#define DPU_DBG_MASK_SSPP (1 << 5)348#define DPU_DBG_MASK_WB (1 << 6)349#define DPU_DBG_MASK_TOP (1 << 7)350#define DPU_DBG_MASK_VBIF (1 << 8)351#define DPU_DBG_MASK_ROT (1 << 9)352#define DPU_DBG_MASK_DSPP (1 << 10)353#define DPU_DBG_MASK_DSC (1 << 11)354#define DPU_DBG_MASK_CDM (1 << 12)355 356/**357 * struct dpu_hw_tear_check - Struct contains parameters to configure358 * tear-effect module. This structure is used to configure tear-check359 * logic present either in ping-pong or in interface module.360 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided361 * by no of lines362 * @sync_cfg_height: Total vertical lines (display height - 1)363 * @vsync_init_val: Init value to which the read pointer gets loaded at364 * vsync edge365 * @sync_threshold_start: Read pointer threshold start ROI for write operation366 * @sync_threshold_continue: The minimum number of lines the write pointer367 * needs to be above the read pointer368 * @start_pos: The position from which the start_threshold value is added369 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated370 * @hw_vsync_mode: Sync with external frame sync input371 */372struct dpu_hw_tear_check {373 /*374 * This is ratio of MDP VSYNC clk freq(Hz) to375 * refresh rate divided by no of lines376 */377 u32 vsync_count;378 u32 sync_cfg_height;379 u32 vsync_init_val;380 u32 sync_threshold_start;381 u32 sync_threshold_continue;382 u32 start_pos;383 u32 rd_ptr_irq;384 u8 hw_vsync_mode;385};386 387/**388 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure389 * read and write pointers for command mode panels390 * @rd_ptr_init_val: Value of rd pointer at vsync edge391 * @rd_ptr_frame_count: Num frames sent since enabling interface392 * @rd_ptr_line_count: Current line on panel (rd ptr)393 * @wr_ptr_line_count: Current line within pp fifo (wr ptr)394 * @intf_frame_count: Frames read from intf395 */396struct dpu_hw_pp_vsync_info {397 u32 rd_ptr_init_val;398 u32 rd_ptr_frame_count;399 u32 rd_ptr_line_count;400 u32 wr_ptr_line_count;401 u32 intf_frame_count;402};403 404#endif /* _DPU_HW_MDSS_H */405