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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.5 */6 7#ifndef _DPU_HW_UTIL_H8#define _DPU_HW_UTIL_H9 10#include <linux/io.h>11#include <linux/slab.h>12#include "dpu_hw_mdss.h"13#include "dpu_hw_catalog.h"14 15#define REG_MASK(n) ((BIT(n)) - 1)16#define MISR_FRAME_COUNT 0x117#define MISR_CTRL_ENABLE BIT(8)18#define MISR_CTRL_STATUS BIT(9)19#define MISR_CTRL_STATUS_CLEAR BIT(10)20#define MISR_CTRL_FREE_RUN_MASK BIT(31)21 22#define TO_S15D16(_x_)((_x_) << 7)23 24extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L;25extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L;26extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l;27 28/*29 * This is the common struct maintained by each sub block30 * for mapping the register offsets in this block to the31 * absoulute IO address32 * @blk_addr: hw block register mapped address33 * @log_mask: log mask for this block34 */35struct dpu_hw_blk_reg_map {36 void __iomem *blk_addr;37 u32 log_mask;38};39 40/**41 * struct dpu_hw_blk - opaque hardware block object42 */43struct dpu_hw_blk {44 /* opaque */45};46 47/**48 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration49 * @enable: detail enhancer enable/disable50 * @sharpen_level1: sharpening strength for noise51 * @sharpen_level2: sharpening strength for signal52 * @ clip: clip shift53 * @ limit: limit value54 * @ thr_quiet: quiet threshold55 * @ thr_dieout: dieout threshold56 * @ thr_high: low threshold57 * @ thr_high: high threshold58 * @ prec_shift: precision shift59 * @ adjust_a: A-coefficients for mapping curve60 * @ adjust_b: B-coefficients for mapping curve61 * @ adjust_c: C-coefficients for mapping curve62 */63struct dpu_hw_scaler3_de_cfg {64 u32 enable;65 int16_t sharpen_level1;66 int16_t sharpen_level2;67 uint16_t clip;68 uint16_t limit;69 uint16_t thr_quiet;70 uint16_t thr_dieout;71 uint16_t thr_low;72 uint16_t thr_high;73 uint16_t prec_shift;74 int16_t adjust_a[DPU_MAX_DE_CURVES];75 int16_t adjust_b[DPU_MAX_DE_CURVES];76 int16_t adjust_c[DPU_MAX_DE_CURVES];77};78 79 80/**81 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration82 * @enable: scaler enable83 * @dir_en: direction detection block enable84 * @ init_phase_x: horizontal initial phase85 * @ phase_step_x: horizontal phase step86 * @ init_phase_y: vertical initial phase87 * @ phase_step_y: vertical phase step88 * @ preload_x: horizontal preload value89 * @ preload_y: vertical preload value90 * @ src_width: source width91 * @ src_height: source height92 * @ dst_width: destination width93 * @ dst_height: destination height94 * @ y_rgb_filter_cfg: y/rgb plane filter configuration95 * @ uv_filter_cfg: uv plane filter configuration96 * @ alpha_filter_cfg: alpha filter configuration97 * @ blend_cfg: blend coefficients configuration98 * @ lut_flag: scaler LUT update flags99 * 0x1 swap LUT bank100 * 0x2 update 2D filter LUT101 * 0x4 update y circular filter LUT102 * 0x8 update uv circular filter LUT103 * 0x10 update y separable filter LUT104 * 0x20 update uv separable filter LUT105 * @ dir_lut_idx: 2D filter LUT index106 * @ y_rgb_cir_lut_idx: y circular filter LUT index107 * @ uv_cir_lut_idx: uv circular filter LUT index108 * @ y_rgb_sep_lut_idx: y circular filter LUT index109 * @ uv_sep_lut_idx: uv separable filter LUT index110 * @ dir_lut: pointer to 2D LUT111 * @ cir_lut: pointer to circular filter LUT112 * @ sep_lut: pointer to separable filter LUT113 * @ de: detail enhancer configuration114 * @ dir_weight: Directional weight115 */116struct dpu_hw_scaler3_cfg {117 u32 enable;118 u32 dir_en;119 int32_t init_phase_x[DPU_MAX_PLANES];120 int32_t phase_step_x[DPU_MAX_PLANES];121 int32_t init_phase_y[DPU_MAX_PLANES];122 int32_t phase_step_y[DPU_MAX_PLANES];123 124 u32 preload_x[DPU_MAX_PLANES];125 u32 preload_y[DPU_MAX_PLANES];126 u32 src_width[DPU_MAX_PLANES];127 u32 src_height[DPU_MAX_PLANES];128 129 u32 dst_width;130 u32 dst_height;131 132 u32 y_rgb_filter_cfg;133 u32 uv_filter_cfg;134 u32 alpha_filter_cfg;135 u32 blend_cfg;136 137 u32 lut_flag;138 u32 dir_lut_idx;139 140 u32 y_rgb_cir_lut_idx;141 u32 uv_cir_lut_idx;142 u32 y_rgb_sep_lut_idx;143 u32 uv_sep_lut_idx;144 u32 *dir_lut;145 size_t dir_len;146 u32 *cir_lut;147 size_t cir_len;148 u32 *sep_lut;149 size_t sep_len;150 151 /*152 * Detail enhancer settings153 */154 struct dpu_hw_scaler3_de_cfg de;155 156 u32 dir_weight;157};158 159/**160 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure161 * @num_ext_pxls_lr: Number of total horizontal pixels162 * @num_ext_pxls_tb: Number of total vertical lines163 * @left_ftch: Number of extra pixels to overfetch from left164 * @right_ftch: Number of extra pixels to overfetch from right165 * @top_ftch: Number of extra lines to overfetch from top166 * @btm_ftch: Number of extra lines to overfetch from bottom167 * @left_rpt: Number of extra pixels to repeat from left168 * @right_rpt: Number of extra pixels to repeat from right169 * @top_rpt: Number of extra lines to repeat from top170 * @btm_rpt: Number of extra lines to repeat from bottom171 */172struct dpu_drm_pix_ext_v1 {173 /*174 * Number of pixels ext in left, right, top and bottom direction175 * for all color components.176 */177 int32_t num_ext_pxls_lr[DPU_MAX_PLANES];178 int32_t num_ext_pxls_tb[DPU_MAX_PLANES];179 180 /*181 * Number of pixels needs to be overfetched in left, right, top182 * and bottom directions from source image for scaling.183 */184 int32_t left_ftch[DPU_MAX_PLANES];185 int32_t right_ftch[DPU_MAX_PLANES];186 int32_t top_ftch[DPU_MAX_PLANES];187 int32_t btm_ftch[DPU_MAX_PLANES];188 /*189 * Number of pixels needs to be repeated in left, right, top and190 * bottom directions for scaling.191 */192 int32_t left_rpt[DPU_MAX_PLANES];193 int32_t right_rpt[DPU_MAX_PLANES];194 int32_t top_rpt[DPU_MAX_PLANES];195 int32_t btm_rpt[DPU_MAX_PLANES];196 197};198 199/**200 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure201 * @enable: Enables/disables detail enhancer202 * @sharpen_level1: Sharpening strength for noise203 * @sharpen_level2: Sharpening strength for context204 * @clip: Clip coefficient205 * @limit: Detail enhancer limit factor206 * @thr_quiet: Quite zone threshold207 * @thr_dieout: Die-out zone threshold208 * @thr_low: Linear zone left threshold209 * @thr_high: Linear zone right threshold210 * @prec_shift: Detail enhancer precision211 * @adjust_a: Mapping curves A coefficients212 * @adjust_b: Mapping curves B coefficients213 * @adjust_c: Mapping curves C coefficients214 */215struct dpu_drm_de_v1 {216 uint32_t enable;217 int16_t sharpen_level1;218 int16_t sharpen_level2;219 uint16_t clip;220 uint16_t limit;221 uint16_t thr_quiet;222 uint16_t thr_dieout;223 uint16_t thr_low;224 uint16_t thr_high;225 uint16_t prec_shift;226 int16_t adjust_a[DPU_MAX_DE_CURVES];227 int16_t adjust_b[DPU_MAX_DE_CURVES];228 int16_t adjust_c[DPU_MAX_DE_CURVES];229};230 231/**232 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler233 * @enable: Scaler enable234 * @dir_en: Detail enhancer enable235 * @pe: Pixel extension settings236 * @horz_decimate: Horizontal decimation factor237 * @vert_decimate: Vertical decimation factor238 * @init_phase_x: Initial scaler phase values for x239 * @phase_step_x: Phase step values for x240 * @init_phase_y: Initial scaler phase values for y241 * @phase_step_y: Phase step values for y242 * @preload_x: Horizontal preload value243 * @preload_y: Vertical preload value244 * @src_width: Source width245 * @src_height: Source height246 * @dst_width: Destination width247 * @dst_height: Destination height248 * @y_rgb_filter_cfg: Y/RGB plane filter configuration249 * @uv_filter_cfg: UV plane filter configuration250 * @alpha_filter_cfg: Alpha filter configuration251 * @blend_cfg: Selection of blend coefficients252 * @lut_flag: LUT configuration flags253 * @dir_lut_idx: 2d 4x4 LUT index254 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index255 * @uv_cir_lut_idx: UV circular LUT index256 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index257 * @uv_sep_lut_idx: UV separable LUT index258 * @de: Detail enhancer settings259 */260struct dpu_drm_scaler_v2 {261 /*262 * General definitions263 */264 uint32_t enable;265 uint32_t dir_en;266 267 /*268 * Pix ext settings269 */270 struct dpu_drm_pix_ext_v1 pe;271 272 /*273 * Decimation settings274 */275 uint32_t horz_decimate;276 uint32_t vert_decimate;277 278 /*279 * Phase settings280 */281 int32_t init_phase_x[DPU_MAX_PLANES];282 int32_t phase_step_x[DPU_MAX_PLANES];283 int32_t init_phase_y[DPU_MAX_PLANES];284 int32_t phase_step_y[DPU_MAX_PLANES];285 286 uint32_t preload_x[DPU_MAX_PLANES];287 uint32_t preload_y[DPU_MAX_PLANES];288 uint32_t src_width[DPU_MAX_PLANES];289 uint32_t src_height[DPU_MAX_PLANES];290 291 uint32_t dst_width;292 uint32_t dst_height;293 294 uint32_t y_rgb_filter_cfg;295 uint32_t uv_filter_cfg;296 uint32_t alpha_filter_cfg;297 uint32_t blend_cfg;298 299 uint32_t lut_flag;300 uint32_t dir_lut_idx;301 302 /* for Y(RGB) and UV planes*/303 uint32_t y_rgb_cir_lut_idx;304 uint32_t uv_cir_lut_idx;305 uint32_t y_rgb_sep_lut_idx;306 uint32_t uv_sep_lut_idx;307 308 /*309 * Detail enhancer settings310 */311 struct dpu_drm_de_v1 de;312};313 314/**315 * struct dpu_hw_qos_cfg: pipe QoS configuration316 * @danger_lut: LUT for generate danger level based on fill level317 * @safe_lut: LUT for generate safe level based on fill level318 * @creq_lut: LUT for generate creq level based on fill level319 * @creq_vblank: creq value generated to vbif during vertical blanking320 * @danger_vblank: danger value generated during vertical blanking321 * @vblank_en: enable creq_vblank and danger_vblank during vblank322 * @danger_safe_en: enable danger safe generation323 */324struct dpu_hw_qos_cfg {325 u32 danger_lut;326 u32 safe_lut;327 u64 creq_lut;328 bool danger_safe_en;329};330 331u32 *dpu_hw_util_get_log_mask_ptr(void);332 333void dpu_reg_write(struct dpu_hw_blk_reg_map *c,334 u32 reg_off,335 u32 val,336 const char *name);337int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);338 339#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)340#define DPU_REG_READ(c, off) dpu_reg_read(c, off)341 342void *dpu_hw_util_get_dir(void);343 344void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,345 struct dpu_hw_scaler3_cfg *scaler3_cfg,346 u32 scaler_offset, u32 scaler_version,347 const struct msm_format *format);348 349void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,350 u32 csc_reg_off,351 const struct dpu_csc_cfg *data, bool csc10);352 353void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,354 const struct msm_format *fmt, bool enable);355 356u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,357 u32 total_fl);358 359void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,360 bool qos_8lvl,361 const struct dpu_hw_qos_cfg *cfg);362 363void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,364 u32 misr_ctrl_offset, u8 input_sel);365 366int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,367 u32 misr_ctrl_offset,368 u32 misr_signature_offset,369 u32 *misr_value);370 371bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,372 const struct dpu_clk_ctrl_reg *clk_ctrl_reg,373 bool enable);374 375#endif /* _DPU_HW_UTIL_H */376