74 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.3 */4 5#ifndef _DPU_HWIO_H6#define _DPU_HWIO_H7 8#include "dpu_hw_util.h"9 10/**11 * MDP TOP block Register and bit fields and defines12 */13#define DISP_INTF_SEL 0x00414#define INTR_EN 0x01015#define INTR_STATUS 0x01416#define INTR_CLEAR 0x01817#define INTR2_EN 0x00818#define INTR2_STATUS 0x00c19#define SSPP_SPARE 0x02820#define INTR2_CLEAR 0x02c21#define HIST_INTR_EN 0x01c22#define HIST_INTR_STATUS 0x02023#define HIST_INTR_CLEAR 0x02424#define SPLIT_DISPLAY_EN 0x2F425#define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F826#define DSPP_IGC_COLOR0_RAM_LUTN 0x30027#define DSPP_IGC_COLOR1_RAM_LUTN 0x30428#define DSPP_IGC_COLOR2_RAM_LUTN 0x30829#define DANGER_STATUS 0x36030#define SAFE_STATUS 0x36431#define HW_EVENTS_CTL 0x37C32#define MDP_WD_TIMER_0_CTL 0x38033#define MDP_WD_TIMER_0_CTL2 0x38434#define MDP_WD_TIMER_0_LOAD_VALUE 0x38835#define MDP_WD_TIMER_1_CTL 0x39036#define MDP_WD_TIMER_1_CTL2 0x39437#define MDP_WD_TIMER_1_LOAD_VALUE 0x39838#define CLK_CTRL3 0x3A839#define CLK_STATUS3 0x3AC40#define CLK_CTRL4 0x3B041#define CLK_STATUS4 0x3B442#define CLK_CTRL5 0x3B843#define CLK_STATUS5 0x3BC44#define CLK_CTRL7 0x3D045#define CLK_STATUS7 0x3D446#define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F047#define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F448#define INTF_SW_RESET_MASK 0x3FC49#define HDMI_DP_CORE_SELECT 0x40850#define MDP_OUT_CTL_0 0x41051#define MDP_VSYNC_SEL 0x41452#define MDP_WD_TIMER_2_CTL 0x42053#define MDP_WD_TIMER_2_CTL2 0x42454#define MDP_WD_TIMER_2_LOAD_VALUE 0x42855#define MDP_WD_TIMER_3_CTL 0x43056#define MDP_WD_TIMER_3_CTL2 0x43457#define MDP_WD_TIMER_3_LOAD_VALUE 0x43858#define MDP_WD_TIMER_4_CTL 0x44059#define MDP_WD_TIMER_4_CTL2 0x44460#define MDP_WD_TIMER_4_LOAD_VALUE 0x44861#define DCE_SEL 0x45062 63#define MDP_DP_PHY_INTF_SEL 0x46064#define MDP_DP_PHY_INTF_SEL_INTF0 GENMASK(2, 0)65#define MDP_DP_PHY_INTF_SEL_INTF1 GENMASK(5, 3)66#define MDP_DP_PHY_INTF_SEL_PHY0 GENMASK(8, 6)67#define MDP_DP_PHY_INTF_SEL_PHY1 GENMASK(11, 9)68#define MDP_DP_PHY_INTF_SEL_PHY2 GENMASK(14, 12)69 70#define MDP_PERIPH_TOP0 MDP_WD_TIMER_0_CTL71#define MDP_PERIPH_TOP0_END CLK_CTRL372 73#endif /*_DPU_HWIO_H */74