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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2013 Red Hat4 * Author: Rob Clark <robdclark@gmail.com>5 */6 7#ifndef __MDP5_KMS_H__8#define __MDP5_KMS_H__9 10#include "msm_drv.h"11#include "msm_kms.h"12#include "disp/mdp_kms.h"13#include "mdp5_cfg.h" /* must be included before mdp5.xml.h */14#include "mdp5.xml.h"15#include "mdp5_pipe.h"16#include "mdp5_mixer.h"17#include "mdp5_ctl.h"18#include "mdp5_smp.h"19 20struct mdp5_kms {21 struct mdp_kms base;22 23 struct drm_device *dev;24 25 struct platform_device *pdev;26 27 unsigned num_hwpipes;28 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];29 30 unsigned num_hwmixers;31 struct mdp5_hw_mixer *hwmixers[8];32 33 unsigned num_intfs;34 struct mdp5_interface *intfs[5];35 36 struct mdp5_cfg_handler *cfg;37 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */38 39 /*40 * Global private object state, Do not access directly, use41 * mdp5_global_get_state()42 */43 struct drm_private_obj glob_state;44 45 struct mdp5_smp *smp;46 struct mdp5_ctl_manager *ctlm;47 48 /* io/register spaces: */49 void __iomem *mmio;50 51 struct clk *axi_clk;52 struct clk *ahb_clk;53 struct clk *core_clk;54 struct clk *lut_clk;55 struct clk *tbu_clk;56 struct clk *tbu_rt_clk;57 struct clk *vsync_clk;58 59 /*60 * lock to protect access to global resources: ie., following register:61 * - REG_MDP5_DISP_INTF_SEL62 */63 spinlock_t resource_lock;64 65 bool rpm_enabled;66 67 struct mdp_irq error_handler;68 69 int enable_count;70};71#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)72 73/* Global private object state for tracking resources that are shared across74 * multiple kms objects (planes/crtcs/etc).75 */76#define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)77struct mdp5_global_state {78 struct drm_private_state base;79 80 struct drm_atomic_state *state;81 struct mdp5_kms *mdp5_kms;82 83 struct mdp5_hw_pipe_state hwpipe;84 struct mdp5_hw_mixer_state hwmixer;85 struct mdp5_smp_state smp;86};87 88struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);89struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s);90 91/* Atomic plane state. Subclasses the base drm_plane_state in order to92 * track assigned hwpipe and hw specific state.93 */94struct mdp5_plane_state {95 struct drm_plane_state base;96 97 struct mdp5_hw_pipe *hwpipe;98 struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */99 100 /* assigned by crtc blender */101 enum mdp_mixer_stage_id stage;102 103 /* whether attached CRTC needs pixel data explicitly flushed to104 * display (ex. DSI command mode display)105 */106 bool needs_dirtyfb;107};108#define to_mdp5_plane_state(x) \109 container_of(x, struct mdp5_plane_state, base)110 111struct mdp5_pipeline {112 struct mdp5_interface *intf;113 struct mdp5_hw_mixer *mixer;114 struct mdp5_hw_mixer *r_mixer; /* right mixer */115};116 117struct mdp5_crtc_state {118 struct drm_crtc_state base;119 120 struct mdp5_ctl *ctl;121 struct mdp5_pipeline pipeline;122 123 /* these are derivatives of intf/mixer state in mdp5_pipeline */124 u32 vblank_irqmask;125 u32 err_irqmask;126 u32 pp_done_irqmask;127 128 bool cmd_mode;129 130 /* should we not write CTL[n].START register on flush? If the131 * encoder has changed this is set to true, since encoder->enable()132 * is called after crtc state is committed, but we only want to133 * write the CTL[n].START register once. This lets us defer134 * writing CTL[n].START until encoder->enable()135 */136 bool defer_start;137};138#define to_mdp5_crtc_state(x) \139 container_of(x, struct mdp5_crtc_state, base)140 141enum mdp5_intf_mode {142 MDP5_INTF_MODE_NONE = 0,143 144 /* Modes used for DSI interface (INTF_DSI type): */145 MDP5_INTF_DSI_MODE_VIDEO,146 MDP5_INTF_DSI_MODE_COMMAND,147 148 /* Modes used for WB interface (INTF_WB type): */149 MDP5_INTF_WB_MODE_BLOCK,150 MDP5_INTF_WB_MODE_LINE,151};152 153struct mdp5_interface {154 int idx;155 int num; /* display interface number */156 enum mdp5_intf_type type;157 enum mdp5_intf_mode mode;158};159 160struct mdp5_encoder {161 struct drm_encoder base;162 spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */163 bool enabled;164 uint32_t bsc;165 166 struct mdp5_interface *intf;167 struct mdp5_ctl *ctl;168};169#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)170 171static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)172{173 WARN_ON(mdp5_kms->enable_count <= 0);174 writel(data, mdp5_kms->mmio + reg);175}176 177static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)178{179 WARN_ON(mdp5_kms->enable_count <= 0);180 return readl(mdp5_kms->mmio + reg);181}182 183static inline const char *stage2name(enum mdp_mixer_stage_id stage)184{185 static const char *names[] = {186#define NAME(n) [n] = #n187 NAME(STAGE_UNUSED), NAME(STAGE_BASE),188 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),189 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),190#undef NAME191 };192 return names[stage];193}194 195static inline const char *pipe2name(enum mdp5_pipe pipe)196{197 static const char *names[] = {198#define NAME(n) [SSPP_ ## n] = #n199 NAME(VIG0), NAME(VIG1), NAME(VIG2),200 NAME(RGB0), NAME(RGB1), NAME(RGB2),201 NAME(DMA0), NAME(DMA1),202 NAME(VIG3), NAME(RGB3),203 NAME(CURSOR0), NAME(CURSOR1),204#undef NAME205 };206 return names[pipe];207}208 209static inline int pipe2nclients(enum mdp5_pipe pipe)210{211 switch (pipe) {212 case SSPP_RGB0:213 case SSPP_RGB1:214 case SSPP_RGB2:215 case SSPP_RGB3:216 return 1;217 default:218 return 3;219 }220}221 222static inline uint32_t intf2err(int intf_num)223{224 switch (intf_num) {225 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;226 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;227 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;228 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;229 default: return 0;230 }231}232 233static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,234 struct mdp5_interface *intf)235{236 /*237 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ238 * acts as a Vblank signal. The Ping Pong buffer used is bound to239 * layer mixer.240 */241 242 if ((intf->type == INTF_DSI) &&243 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))244 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;245 246 if (intf->type == INTF_WB)247 return MDP5_IRQ_WB_2_DONE;248 249 switch (intf->num) {250 case 0: return MDP5_IRQ_INTF0_VSYNC;251 case 1: return MDP5_IRQ_INTF1_VSYNC;252 case 2: return MDP5_IRQ_INTF2_VSYNC;253 case 3: return MDP5_IRQ_INTF3_VSYNC;254 default: return 0;255 }256}257 258static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)259{260 return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;261}262 263void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,264 uint32_t old_irqmask);265void mdp5_irq_preinstall(struct msm_kms *kms);266int mdp5_irq_postinstall(struct msm_kms *kms);267void mdp5_irq_uninstall(struct msm_kms *kms);268irqreturn_t mdp5_irq(struct msm_kms *kms);269int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);270void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);271int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);272void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);273 274uint32_t mdp5_plane_get_flush(struct drm_plane *plane);275enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);276enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);277struct drm_plane *mdp5_plane_init(struct drm_device *dev,278 enum drm_plane_type type);279 280struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);281uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);282 283struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);284struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);285void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);286void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);287struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,288 struct drm_plane *plane,289 struct drm_plane *cursor_plane, int id);290 291struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,292 struct mdp5_interface *intf, struct mdp5_ctl *ctl);293void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);294int mdp5_encoder_get_linecount(struct drm_encoder *encoder);295u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);296 297#ifdef CONFIG_DRM_MSM_DSI298void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,299 struct drm_display_mode *mode,300 struct drm_display_mode *adjusted_mode);301void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);302void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);303#else304static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,305 struct drm_display_mode *mode,306 struct drm_display_mode *adjusted_mode)307{308}309static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)310{311}312static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)313{314}315#endif316 317#endif /* __MDP5_KMS_H__ */318