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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/delay.h>8 9#include "dsi_phy.h"10#include "dsi.xml.h"11#include "dsi_phy_28nm_8960.xml.h"12 13/*14 * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):15 *16 *17 * +------+18 * dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock)19 * F * byte_clk | +------+20 * | bit clock divider (F / 8)21 * |22 * | +------+23 * o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG24 * | +------+ | (sets parent rate)25 * | byte clock divider (F) |26 * | |27 * | o---> To esc RCG28 * | (doesn't set parent rate)29 * |30 * | +------+31 * o-----| DIV3 |----dsi0pll------o---> To dsi RCG32 * +------+ | (sets parent rate)33 * dsi clock divider (F * magic) |34 * |35 * o---> To pixel rcg36 * (doesn't set parent rate)37 */38 39#define POLL_MAX_READS 800040#define POLL_TIMEOUT_US 141 42#define VCO_REF_CLK_RATE 2700000043#define VCO_MIN_RATE 60000000044#define VCO_MAX_RATE 120000000045 46#define VCO_PREF_DIV_RATIO 2747 48struct pll_28nm_cached_state {49 unsigned long vco_rate;50 u8 postdiv3;51 u8 postdiv2;52 u8 postdiv1;53};54 55struct clk_bytediv {56 struct clk_hw hw;57 void __iomem *reg;58};59 60struct dsi_pll_28nm {61 struct clk_hw clk_hw;62 63 struct msm_dsi_phy *phy;64 65 struct pll_28nm_cached_state cached_state;66};67 68#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw)69 70static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,71 int nb_tries, int timeout_us)72{73 bool pll_locked = false;74 u32 val;75 76 while (nb_tries--) {77 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);78 pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);79 80 if (pll_locked)81 break;82 83 udelay(timeout_us);84 }85 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");86 87 return pll_locked;88}89 90/*91 * Clock Callbacks92 */93static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,94 unsigned long parent_rate)95{96 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);97 void __iomem *base = pll_28nm->phy->pll_base;98 u32 val, temp, fb_divider;99 100 DBG("rate=%lu, parent's=%lu", rate, parent_rate);101 102 temp = rate / 10;103 val = VCO_REF_CLK_RATE / 10;104 fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;105 fb_divider = fb_divider / 2 - 1;106 writel(fb_divider & 0xff, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);107 108 val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);109 110 val |= (fb_divider >> 8) & 0x07;111 112 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);113 114 val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);115 116 val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;117 118 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);119 120 writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6);121 122 val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);123 val |= 0x7 << 4;124 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);125 126 return 0;127}128 129static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)130{131 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);132 133 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,134 POLL_TIMEOUT_US);135}136 137static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,138 unsigned long parent_rate)139{140 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);141 void __iomem *base = pll_28nm->phy->pll_base;142 unsigned long vco_rate;143 u32 status, fb_divider, temp, ref_divider;144 145 VERB("parent_rate=%lu", parent_rate);146 147 status = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);148 149 if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {150 fb_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);151 fb_divider &= 0xff;152 temp = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;153 fb_divider = (temp << 8) | fb_divider;154 fb_divider += 1;155 156 ref_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);157 ref_divider &= 0x3f;158 ref_divider += 1;159 160 /* multiply by 2 */161 vco_rate = (parent_rate / ref_divider) * fb_divider * 2;162 } else {163 vco_rate = 0;164 }165 166 DBG("returning vco rate = %lu", vco_rate);167 168 return vco_rate;169}170 171static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)172{173 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);174 struct device *dev = &pll_28nm->phy->pdev->dev;175 void __iomem *base = pll_28nm->phy->pll_base;176 bool locked;177 unsigned int bit_div, byte_div;178 int max_reads = 1000, timeout_us = 100;179 u32 val;180 181 DBG("id=%d", pll_28nm->phy->id);182 183 if (unlikely(pll_28nm->phy->pll_on))184 return 0;185 186 /*187 * before enabling the PLL, configure the bit clock divider since we188 * don't expose it as a clock to the outside world189 * 1: read back the byte clock divider that should already be set190 * 2: divide by 8 to get bit clock divider191 * 3: write it to POSTDIV1192 */193 val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);194 byte_div = val + 1;195 bit_div = byte_div / 8;196 197 val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);198 val &= ~0xf;199 val |= (bit_div - 1);200 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);201 202 /* enable the PLL */203 writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE,204 base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);205 206 locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);207 208 if (unlikely(!locked)) {209 DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");210 return -EINVAL;211 }212 213 DBG("DSI PLL lock success");214 pll_28nm->phy->pll_on = true;215 216 return 0;217}218 219static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)220{221 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);222 223 DBG("id=%d", pll_28nm->phy->id);224 225 if (unlikely(!pll_28nm->phy->pll_on))226 return;227 228 writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);229 230 pll_28nm->phy->pll_on = false;231}232 233static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,234 unsigned long rate, unsigned long *parent_rate)235{236 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw);237 238 if (rate < pll_28nm->phy->cfg->min_pll_rate)239 return pll_28nm->phy->cfg->min_pll_rate;240 else if (rate > pll_28nm->phy->cfg->max_pll_rate)241 return pll_28nm->phy->cfg->max_pll_rate;242 else243 return rate;244}245 246static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {247 .round_rate = dsi_pll_28nm_clk_round_rate,248 .set_rate = dsi_pll_28nm_clk_set_rate,249 .recalc_rate = dsi_pll_28nm_clk_recalc_rate,250 .prepare = dsi_pll_28nm_vco_prepare,251 .unprepare = dsi_pll_28nm_vco_unprepare,252 .is_enabled = dsi_pll_28nm_clk_is_enabled,253};254 255/*256 * Custom byte clock divier clk_ops257 *258 * This clock is the entry point to configuring the PLL. The user (dsi host)259 * will set this clock's rate to the desired byte clock rate. The VCO lock260 * frequency is a multiple of the byte clock rate. The multiplication factor261 * (shown as F in the diagram above) is a function of the byte clock rate.262 *263 * This custom divider clock ensures that its parent (VCO) is set to the264 * desired rate, and that the byte clock postdivider (POSTDIV2) is configured265 * accordingly266 */267#define to_clk_bytediv(_hw) container_of(_hw, struct clk_bytediv, hw)268 269static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw,270 unsigned long parent_rate)271{272 struct clk_bytediv *bytediv = to_clk_bytediv(hw);273 unsigned int div;274 275 div = readl(bytediv->reg) & 0xff;276 277 return parent_rate / (div + 1);278}279 280/* find multiplication factor(wrt byte clock) at which the VCO should be set */281static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate)282{283 unsigned long bit_mhz;284 285 /* convert to bit clock in Mhz */286 bit_mhz = (byte_clk_rate * 8) / 1000000;287 288 if (bit_mhz < 125)289 return 64;290 else if (bit_mhz < 250)291 return 32;292 else if (bit_mhz < 600)293 return 16;294 else295 return 8;296}297 298static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate,299 unsigned long *prate)300{301 unsigned long best_parent;302 unsigned int factor;303 304 factor = get_vco_mul_factor(rate);305 306 best_parent = rate * factor;307 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);308 309 return *prate / factor;310}311 312static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate,313 unsigned long parent_rate)314{315 struct clk_bytediv *bytediv = to_clk_bytediv(hw);316 u32 val;317 unsigned int factor;318 319 factor = get_vco_mul_factor(rate);320 321 val = readl(bytediv->reg);322 val |= (factor - 1) & 0xff;323 writel(val, bytediv->reg);324 325 return 0;326}327 328/* Our special byte clock divider ops */329static const struct clk_ops clk_bytediv_ops = {330 .round_rate = clk_bytediv_round_rate,331 .set_rate = clk_bytediv_set_rate,332 .recalc_rate = clk_bytediv_recalc_rate,333};334 335/*336 * PLL Callbacks337 */338static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy)339{340 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);341 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;342 void __iomem *base = pll_28nm->phy->pll_base;343 344 cached_state->postdiv3 =345 readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);346 cached_state->postdiv2 =347 readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);348 cached_state->postdiv1 =349 readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);350 351 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);352}353 354static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)355{356 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);357 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;358 void __iomem *base = pll_28nm->phy->pll_base;359 int ret;360 361 ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,362 cached_state->vco_rate, 0);363 if (ret) {364 DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,365 "restore vco rate failed. ret=%d\n", ret);366 return ret;367 }368 369 writel(cached_state->postdiv3, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);370 writel(cached_state->postdiv2, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);371 writel(cached_state->postdiv1, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);372 373 return 0;374}375 376static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)377{378 char clk_name[32];379 struct clk_init_data vco_init = {380 .parent_data = &(const struct clk_parent_data) {381 .fw_name = "ref",382 },383 .num_parents = 1,384 .flags = CLK_IGNORE_UNUSED,385 .ops = &clk_ops_dsi_pll_28nm_vco,386 };387 struct device *dev = &pll_28nm->phy->pdev->dev;388 struct clk_hw *hw;389 struct clk_bytediv *bytediv;390 struct clk_init_data bytediv_init = { };391 int ret;392 393 DBG("%d", pll_28nm->phy->id);394 395 bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL);396 if (!bytediv)397 return -ENOMEM;398 399 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id);400 vco_init.name = clk_name;401 402 pll_28nm->clk_hw.init = &vco_init;403 404 ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw);405 if (ret)406 return ret;407 408 /* prepare and register bytediv */409 bytediv->hw.init = &bytediv_init;410 bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;411 412 snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id + 1);413 414 bytediv_init.name = clk_name;415 bytediv_init.ops = &clk_bytediv_ops;416 bytediv_init.flags = CLK_SET_RATE_PARENT;417 bytediv_init.parent_hws = (const struct clk_hw*[]){418 &pll_28nm->clk_hw,419 };420 bytediv_init.num_parents = 1;421 422 /* DIV2 */423 ret = devm_clk_hw_register(dev, &bytediv->hw);424 if (ret)425 return ret;426 provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;427 428 snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id + 1);429 /* DIV3 */430 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,431 &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base +432 REG_DSI_28nm_8960_PHY_PLL_CTRL_10,433 0, 8, 0, NULL);434 if (IS_ERR(hw))435 return PTR_ERR(hw);436 provided_clocks[DSI_PIXEL_PLL_CLK] = hw;437 438 return 0;439}440 441static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)442{443 struct platform_device *pdev = phy->pdev;444 struct dsi_pll_28nm *pll_28nm;445 int ret;446 447 if (!pdev)448 return -ENODEV;449 450 pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);451 if (!pll_28nm)452 return -ENOMEM;453 454 pll_28nm->phy = phy;455 456 ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);457 if (ret) {458 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);459 return ret;460 }461 462 phy->vco_hw = &pll_28nm->clk_hw;463 464 return 0;465}466 467static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,468 struct msm_dsi_dphy_timing *timing)469{470 void __iomem *base = phy->base;471 472 writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),473 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0);474 writel(DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),475 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1);476 writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),477 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2);478 writel(0, base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3);479 writel(DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),480 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4);481 writel(DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),482 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5);483 writel(DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),484 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6);485 writel(DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),486 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7);487 writel(DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),488 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8);489 writel(DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |490 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),491 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9);492 writel(DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),493 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10);494 writel(DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0),495 base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11);496}497 498static void dsi_28nm_phy_regulator_init(struct msm_dsi_phy *phy)499{500 void __iomem *base = phy->reg_base;501 502 writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);503 writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);504 writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);505 writel(0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);506 writel(0x100, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);507}508 509static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy)510{511 void __iomem *base = phy->reg_base;512 513 writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);514 writel(0xa, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);515 writel(0x4, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);516 writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);517 writel(0x20, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);518}519 520static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy)521{522 void __iomem *base = phy->reg_base;523 u32 status;524 int i = 5000;525 526 writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG);527 528 writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2);529 writel(0x5a, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1);530 writel(0x10, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3);531 writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4);532 writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0);533 534 writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);535 usleep_range(5000, 6000);536 writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);537 538 do {539 status = readl(base +540 REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS);541 542 if (!(status & DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY))543 break;544 545 udelay(1);546 } while (--i > 0);547}548 549static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy)550{551 void __iomem *base = phy->base;552 int i;553 554 for (i = 0; i < 4; i++) {555 writel(0x80, base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i));556 writel(0x45, base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i));557 writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i));558 writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i));559 writel(0x01, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i));560 writel(0x66, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i));561 }562 563 writel(0x40, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0);564 writel(0x67, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1);565 writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2);566 writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH);567 writel(0x1, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0);568 writel(0x88, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1);569}570 571static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,572 struct msm_dsi_phy_clk_request *clk_req)573{574 struct msm_dsi_dphy_timing *timing = &phy->timing;575 void __iomem *base = phy->base;576 577 DBG("");578 579 if (msm_dsi_dphy_timing_calc(timing, clk_req)) {580 DRM_DEV_ERROR(&phy->pdev->dev,581 "%s: D-PHY timing calculation failed\n",582 __func__);583 return -EINVAL;584 }585 586 dsi_28nm_phy_regulator_init(phy);587 588 writel(0x04, base + REG_DSI_28nm_8960_PHY_LDO_CTRL);589 590 /* strength control */591 writel(0xff, base + REG_DSI_28nm_8960_PHY_STRENGTH_0);592 writel(0x00, base + REG_DSI_28nm_8960_PHY_STRENGTH_1);593 writel(0x06, base + REG_DSI_28nm_8960_PHY_STRENGTH_2);594 595 /* phy ctrl */596 writel(0x5f, base + REG_DSI_28nm_8960_PHY_CTRL_0);597 writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_1);598 writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_2);599 writel(0x10, base + REG_DSI_28nm_8960_PHY_CTRL_3);600 601 dsi_28nm_phy_regulator_ctrl(phy);602 603 dsi_28nm_phy_calibration(phy);604 605 dsi_28nm_phy_lane_config(phy);606 607 writel(0x0f, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);608 writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1);609 writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0);610 writel(0x0, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);611 612 dsi_28nm_dphy_set_timing(phy, timing);613 614 return 0;615}616 617static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)618{619 writel(0x0, phy->base + REG_DSI_28nm_8960_PHY_CTRL_0);620 621 /*622 * Wait for the registers writes to complete in order to623 * ensure that the phy is completely disabled624 */625 wmb();626}627 628static const struct regulator_bulk_data dsi_phy_28nm_8960_regulators[] = {629 { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */630};631 632const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {633 .has_phy_regulator = true,634 .regulator_data = dsi_phy_28nm_8960_regulators,635 .num_regulators = ARRAY_SIZE(dsi_phy_28nm_8960_regulators),636 .ops = {637 .enable = dsi_28nm_phy_enable,638 .disable = dsi_28nm_phy_disable,639 .pll_init = dsi_pll_28nm_8960_init,640 .save_pll_state = dsi_28nm_pll_save_state,641 .restore_pll_state = dsi_28nm_pll_restore_state,642 },643 .min_pll_rate = VCO_MIN_RATE,644 .max_pll_rate = VCO_MAX_RATE,645 .io_start = { 0x4700300, 0x5800300 },646 .num_dsi_phy = 2,647};648