brintos / linux-shallow public Read only

1<?xml version="1.0" encoding="UTF-8"?>2<database xmlns="http://nouveau.freedesktop.org/"3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">5<import file="freedreno_copyright.xml"/>6<import file="adreno/adreno_common.xml"/>7<import file="adreno/adreno_pm4.xml"/>8 9<enum name="a3xx_tile_mode">10	<value name="LINEAR" value="0"/>11	<value name="TILE_4X4" value="1"/>    <!-- "normal" case for textures -->12	<value name="TILE_32X32" value="2"/>  <!-- only used in GMEM -->13	<value name="TILE_4X2" value="3"/>    <!-- only used for CrCb -->14</enum>15 16<enum name="a3xx_state_block_id">17	<value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>18	<value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>19	<value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>20	<value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>21</enum>22 23<enum name="a3xx_cache_opcode">24	<value name="INVALIDATE" value="1"/>25</enum>26 27<enum name="a3xx_vtx_fmt">28	<value name="VFMT_32_FLOAT" value="0x0"/>29	<value name="VFMT_32_32_FLOAT" value="0x1"/>30	<value name="VFMT_32_32_32_FLOAT" value="0x2"/>31	<value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>32 33	<value name="VFMT_16_FLOAT" value="0x4"/>34	<value name="VFMT_16_16_FLOAT" value="0x5"/>35	<value name="VFMT_16_16_16_FLOAT" value="0x6"/>36	<value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>37 38	<value name="VFMT_32_FIXED" value="0x8"/>39	<value name="VFMT_32_32_FIXED" value="0x9"/>40	<value name="VFMT_32_32_32_FIXED" value="0xa"/>41	<value name="VFMT_32_32_32_32_FIXED" value="0xb"/>42 43	<value name="VFMT_16_SINT" value="0x10"/>44	<value name="VFMT_16_16_SINT" value="0x11"/>45	<value name="VFMT_16_16_16_SINT" value="0x12"/>46	<value name="VFMT_16_16_16_16_SINT" value="0x13"/>47	<value name="VFMT_16_UINT" value="0x14"/>48	<value name="VFMT_16_16_UINT" value="0x15"/>49	<value name="VFMT_16_16_16_UINT" value="0x16"/>50	<value name="VFMT_16_16_16_16_UINT" value="0x17"/>51	<value name="VFMT_16_SNORM" value="0x18"/>52	<value name="VFMT_16_16_SNORM" value="0x19"/>53	<value name="VFMT_16_16_16_SNORM" value="0x1a"/>54	<value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>55	<value name="VFMT_16_UNORM" value="0x1c"/>56	<value name="VFMT_16_16_UNORM" value="0x1d"/>57	<value name="VFMT_16_16_16_UNORM" value="0x1e"/>58	<value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>59 60	<!-- seems to be no NORM variants for 32bit.. -->61	<value name="VFMT_32_UINT" value="0x20"/>62	<value name="VFMT_32_32_UINT" value="0x21"/>63	<value name="VFMT_32_32_32_UINT" value="0x22"/>64	<value name="VFMT_32_32_32_32_UINT" value="0x23"/>65	<value name="VFMT_32_SINT" value="0x24"/>66	<value name="VFMT_32_32_SINT" value="0x25"/>67	<value name="VFMT_32_32_32_SINT" value="0x26"/>68	<value name="VFMT_32_32_32_32_SINT" value="0x27"/>69 70	<value name="VFMT_8_UINT" value="0x28"/>71	<value name="VFMT_8_8_UINT" value="0x29"/>72	<value name="VFMT_8_8_8_UINT" value="0x2a"/>73	<value name="VFMT_8_8_8_8_UINT" value="0x2b"/>74	<value name="VFMT_8_UNORM" value="0x2c"/>75	<value name="VFMT_8_8_UNORM" value="0x2d"/>76	<value name="VFMT_8_8_8_UNORM" value="0x2e"/>77	<value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>78	<value name="VFMT_8_SINT" value="0x30"/>79	<value name="VFMT_8_8_SINT" value="0x31"/>80	<value name="VFMT_8_8_8_SINT" value="0x32"/>81	<value name="VFMT_8_8_8_8_SINT" value="0x33"/>82	<value name="VFMT_8_SNORM" value="0x34"/>83	<value name="VFMT_8_8_SNORM" value="0x35"/>84	<value name="VFMT_8_8_8_SNORM" value="0x36"/>85	<value name="VFMT_8_8_8_8_SNORM" value="0x37"/>86	<value name="VFMT_10_10_10_2_UINT" value="0x38"/>87	<value name="VFMT_10_10_10_2_UNORM" value="0x39"/>88	<value name="VFMT_10_10_10_2_SINT" value="0x3a"/>89	<value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>90	<value name="VFMT_2_10_10_10_UINT" value="0x3c"/>91	<value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>92	<value name="VFMT_2_10_10_10_SINT" value="0x3e"/>93	<value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>94 95	<value name="VFMT_NONE" value="0xff"/>96</enum>97 98<enum name="a3xx_tex_fmt">99	<value name="TFMT_5_6_5_UNORM" value="0x4"/>100	<value name="TFMT_5_5_5_1_UNORM" value="0x5"/>101	<value name="TFMT_4_4_4_4_UNORM" value="0x7"/>102	<value name="TFMT_Z16_UNORM" value="0x9"/>103	<value name="TFMT_X8Z24_UNORM" value="0xa"/>104	<value name="TFMT_Z32_FLOAT" value="0xb"/>105 106	<!--107		The NV12 tiled/linear formats seem to require gang'd sampler108		slots (ie. sampler state N plus N+1) for Y and UV planes.109		They fetch yuv in single sam instruction, but still require110		colorspace conversion in the shader.111	 -->112	<value name="TFMT_UV_64X32" value="0x10"/>113	<value name="TFMT_VU_64X32" value="0x11"/>114	<value name="TFMT_Y_64X32" value="0x12"/>115	<value name="TFMT_NV12_64X32" value="0x13"/>116	<value name="TFMT_UV_LINEAR" value="0x14"/>117	<value name="TFMT_VU_LINEAR" value="0x15"/>118	<value name="TFMT_Y_LINEAR" value="0x16"/>119	<value name="TFMT_NV12_LINEAR" value="0x17"/>120	<value name="TFMT_I420_Y" value="0x18"/>121	<value name="TFMT_I420_U" value="0x1a"/>122	<value name="TFMT_I420_V" value="0x1b"/>123 124	<value name="TFMT_ATC_RGB" value="0x20"/>125	<value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>126	<value name="TFMT_ETC1" value="0x22"/>127	<value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>128 129	<value name="TFMT_DXT1" value="0x24"/>130	<value name="TFMT_DXT3" value="0x25"/>131	<value name="TFMT_DXT5" value="0x26"/>132 133	<value name="TFMT_2_10_10_10_UNORM" value="0x28"/>134	<value name="TFMT_10_10_10_2_UNORM" value="0x29"/>135	<value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>136	<value name="TFMT_11_11_10_FLOAT" value="0x2b"/>137	<value name="TFMT_A8_UNORM" value="0x2c"/>    <!-- GL_ALPHA -->138	<value name="TFMT_L8_UNORM" value="0x2d"/>139	<value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->140 141	<!--142		NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way143		to float16, float32.. but they seem to use non-standard swizzle too..144		perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,145		0xn3 for 1, 2, 3, 4 components respectively..146 147		Only formats filled in below are the ones that have been observed by148		the blob or tested.. you can guess what the missing ones are..149	 -->150 151	<value name="TFMT_8_UNORM" value="0x30"/>     <!-- GL_LUMINANCE -->152	<value name="TFMT_8_8_UNORM" value="0x31"/>153	<value name="TFMT_8_8_8_UNORM" value="0x32"/>154	<value name="TFMT_8_8_8_8_UNORM" value="0x33"/>155 156	<value name="TFMT_8_SNORM" value="0x34"/>157	<value name="TFMT_8_8_SNORM" value="0x35"/>158	<value name="TFMT_8_8_8_SNORM" value="0x36"/>159	<value name="TFMT_8_8_8_8_SNORM" value="0x37"/>160 161	<value name="TFMT_8_UINT" value="0x38"/>162	<value name="TFMT_8_8_UINT" value="0x39"/>163	<value name="TFMT_8_8_8_UINT" value="0x3a"/>164	<value name="TFMT_8_8_8_8_UINT" value="0x3b"/>165 166	<value name="TFMT_8_SINT" value="0x3c"/>167	<value name="TFMT_8_8_SINT" value="0x3d"/>168	<value name="TFMT_8_8_8_SINT" value="0x3e"/>169	<value name="TFMT_8_8_8_8_SINT" value="0x3f"/>170 171	<value name="TFMT_16_FLOAT" value="0x40"/>172	<value name="TFMT_16_16_FLOAT" value="0x41"/>173	<!-- TFMT_FLOAT_16_16_16 -->174	<value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>175 176	<value name="TFMT_16_UINT" value="0x44"/>177	<value name="TFMT_16_16_UINT" value="0x45"/>178	<value name="TFMT_16_16_16_16_UINT" value="0x47"/>179 180	<value name="TFMT_16_SINT" value="0x48"/>181	<value name="TFMT_16_16_SINT" value="0x49"/>182	<value name="TFMT_16_16_16_16_SINT" value="0x4b"/>183 184	<value name="TFMT_16_UNORM" value="0x4c"/>185	<value name="TFMT_16_16_UNORM" value="0x4d"/>186	<value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>187 188	<value name="TFMT_16_SNORM" value="0x50"/>189	<value name="TFMT_16_16_SNORM" value="0x51"/>190	<value name="TFMT_16_16_16_16_SNORM" value="0x53"/>191 192	<value name="TFMT_32_FLOAT" value="0x54"/>193	<value name="TFMT_32_32_FLOAT" value="0x55"/>194	<!-- TFMT_32_32_32_FLOAT -->195	<value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>196 197	<value name="TFMT_32_UINT" value="0x58"/>198	<value name="TFMT_32_32_UINT" value="0x59"/>199	<value name="TFMT_32_32_32_32_UINT" value="0x5b"/>200 201	<value name="TFMT_32_SINT" value="0x5c"/>202	<value name="TFMT_32_32_SINT" value="0x5d"/>203	<value name="TFMT_32_32_32_32_SINT" value="0x5f"/>204 205	<value name="TFMT_2_10_10_10_UINT" value="0x60"/>206	<value name="TFMT_10_10_10_2_UINT" value="0x61"/>207 208	<value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>209	<value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>210	<value name="TFMT_ETC2_R11_SNORM" value="0x72"/>211	<value name="TFMT_ETC2_R11_UNORM" value="0x73"/>212	<value name="TFMT_ETC2_RGBA8" value="0x74"/>213	<value name="TFMT_ETC2_RGB8A1" value="0x75"/>214	<value name="TFMT_ETC2_RGB8" value="0x76"/>215 216	<value name="TFMT_NONE" value="0xff"/>217</enum>218 219<enum name="a3xx_color_fmt">220	<value name="RB_R5G6B5_UNORM"       value="0x00"/>221	<value name="RB_R5G5B5A1_UNORM"     value="0x01"/>222	<value name="RB_R4G4B4A4_UNORM"     value="0x03"/>223	<value name="RB_R8G8B8_UNORM"	    value="0x04"/>224	<value name="RB_R8G8B8A8_UNORM"	    value="0x08"/>225	<value name="RB_R8G8B8A8_SNORM"	    value="0x09"/>226	<value name="RB_R8G8B8A8_UINT"	    value="0x0a"/>227	<value name="RB_R8G8B8A8_SINT"	    value="0x0b"/>228	<value name="RB_R8G8_UNORM"	    value="0x0c"/>229	<value name="RB_R8G8_SNORM"	    value="0x0d"/>230	<value name="RB_R8G8_UINT"	    value="0x0e"/>231	<value name="RB_R8G8_SINT"	    value="0x0f"/>232	<value name="RB_R10G10B10A2_UNORM"  value="0x10"/>233	<value name="RB_A2R10G10B10_UNORM"  value="0x11"/>234	<value name="RB_R10G10B10A2_UINT"   value="0x12"/>235	<value name="RB_A2R10G10B10_UINT"   value="0x13"/>236 237	<value name="RB_A8_UNORM"	    value="0x14"/>238	<value name="RB_R8_UNORM"	    value="0x15"/>239 240	<value name="RB_R16_FLOAT"          value="0x18"/>241	<value name="RB_R16G16_FLOAT"       value="0x19"/>242	<value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->243	<value name="RB_R11G11B10_FLOAT"    value="0x1c"/>244 245	<value name="RB_R16_SNORM"          value="0x20"/>246	<value name="RB_R16G16_SNORM"       value="0x21"/>247	<value name="RB_R16G16B16A16_SNORM" value="0x23"/>248 249	<value name="RB_R16_UNORM"          value="0x24"/>250	<value name="RB_R16G16_UNORM"       value="0x25"/>251	<value name="RB_R16G16B16A16_UNORM" value="0x27"/>252 253	<value name="RB_R16_SINT"	    value="0x28"/>254	<value name="RB_R16G16_SINT"	    value="0x29"/>255	<value name="RB_R16G16B16A16_SINT"  value="0x2b"/>256 257	<value name="RB_R16_UINT"	    value="0x2c"/>258	<value name="RB_R16G16_UINT"	    value="0x2d"/>259	<value name="RB_R16G16B16A16_UINT"  value="0x2f"/>260 261	<value name="RB_R32_FLOAT"          value="0x30"/>262	<value name="RB_R32G32_FLOAT"       value="0x31"/>263	<value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->264 265	<value name="RB_R32_SINT"	    value="0x34"/>266	<value name="RB_R32G32_SINT"	    value="0x35"/>267	<value name="RB_R32G32B32A32_SINT"  value="0x37"/>268 269	<value name="RB_R32_UINT"	    value="0x38"/>270	<value name="RB_R32G32_UINT"	    value="0x39"/>271	<value name="RB_R32G32B32A32_UINT"  value="0x3b"/>272 273	<value name="RB_NONE"               value="0xff"/>274</enum>275 276<enum name="a3xx_cp_perfcounter_select">277	<value value="0x00" name="CP_ALWAYS_COUNT"/>278	<value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>279	<value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>280	<value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>281	<value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>282	<value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>283	<value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>284	<value value="0x0c" name="CP_RESERVED_12"/>285	<value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>286	<value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>287	<value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>288	<value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>289	<value value="0x11" name="CP_RESERVED_17"/>290	<value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>291	<value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>292	<value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>293	<value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>294	<value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>295	<value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>296	<value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>297	<value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>298	<value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>299	<value value="0x29" name="CP_ME_BUSY_CLOCKS"/>300	<value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>301	<value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>302	<value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>303	<value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>304	<value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>305	<value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>306	<value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>307</enum>308 309<enum name="a3xx_gras_tse_perfcounter_select">310	<value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>311	<value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>312	<value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>313	<value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>314	<value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>315	<value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>316	<value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>317	<value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>318	<value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>319	<value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>320	<value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>321	<value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>322	<value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>323	<value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>324	<value value="0x0e" name="GRAS_TSERASPERF_STALL"/>325</enum>326 327<enum name="a3xx_gras_ras_perfcounter_select">328	<value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>329	<value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>330	<value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>331	<value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>332	<value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>333	<value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>334	<value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>335</enum>336 337<enum name="a3xx_hlsq_perfcounter_select">338	<value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>339	<value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>340	<value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>341	<value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>342	<value value="0x04" name="HLSQ_PERF_TP_STATE"/>343	<value value="0x05" name="HLSQ_PERF_QUADS"/>344	<value value="0x06" name="HLSQ_PERF_PIXELS"/>345	<value value="0x07" name="HLSQ_PERF_VERTICES"/>346	<value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>347	<value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>348	<value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>349	<value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>350	<value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>351	<value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>352	<value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>353	<value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>354	<value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>355	<value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>356	<value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>357	<value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>358	<value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>359	<value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>360	<value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>361	<value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>362	<value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>363	<value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>364	<value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>365	<value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>366	<value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>367</enum>368 369<enum name="a3xx_pc_perfcounter_select">370	<value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>371	<value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>372	<value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>373	<value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>374	<value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>375	<value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>376	<value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>377	<value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>378	<value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>379	<value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>380	<value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>381	<value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>382	<value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>383</enum>384 385<enum name="a3xx_rb_perfcounter_select">386	<value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>387	<value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>388	<value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>389	<value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>390	<value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>391	<value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>392	<value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>393	<value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>394	<value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>395	<value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>396	<value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>397	<value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>398	<value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>399	<value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>400	<value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>401	<value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>402	<value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>403</enum>404 405<enum name="a3xx_rbbm_perfcounter_select">406	<value value="0" name="RBBM_ALAWYS_ON"/>407	<value value="1" name="RBBM_VBIF_BUSY"/>408	<value value="2" name="RBBM_TSE_BUSY"/>409	<value value="3" name="RBBM_RAS_BUSY"/>410	<value value="4" name="RBBM_PC_DCALL_BUSY"/>411	<value value="5" name="RBBM_PC_VSD_BUSY"/>412	<value value="6" name="RBBM_VFD_BUSY"/>413	<value value="7" name="RBBM_VPC_BUSY"/>414	<value value="8" name="RBBM_UCHE_BUSY"/>415	<value value="9" name="RBBM_VSC_BUSY"/>416	<value value="10" name="RBBM_HLSQ_BUSY"/>417	<value value="11" name="RBBM_ANY_RB_BUSY"/>418	<value value="12" name="RBBM_ANY_TEX_BUSY"/>419	<value value="13" name="RBBM_ANY_USP_BUSY"/>420	<value value="14" name="RBBM_ANY_MARB_BUSY"/>421	<value value="15" name="RBBM_ANY_ARB_BUSY"/>422	<value value="16" name="RBBM_AHB_STATUS_BUSY"/>423	<value value="17" name="RBBM_AHB_STATUS_STALLED"/>424	<value value="18" name="RBBM_AHB_STATUS_TXFR"/>425	<value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>426	<value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>427	<value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>428	<value value="22" name="RBBM_RBBM_STATUS_MASKED"/>429</enum>430 431<enum name="a3xx_sp_perfcounter_select">432	<value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>433	<value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>434	<value value="0x02" name="SP_LM_ATOMICS"/>435	<value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>436	<value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>437	<value value="0x05" name="SP_UCHE_ATOMICS"/>438	<value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>439	<value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>440	<value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>441	<value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>442	<value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>443	<value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>444	<value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>445	<value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>446	<value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>447	<value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>448	<value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>449	<value value="0x11" name="SP_VS_INSTRUCTIONS"/>450	<value value="0x12" name="SP_FS_INSTRUCTIONS"/>451	<value value="0x13" name="SP_ADDR_LOCK_COUNT"/>452	<value value="0x14" name="SP_UCHE_READ_TRANS"/>453	<value value="0x15" name="SP_UCHE_WRITE_TRANS"/>454	<value value="0x16" name="SP_EXPORT_VPC_TRANS"/>455	<value value="0x17" name="SP_EXPORT_RB_TRANS"/>456	<value value="0x18" name="SP_PIXELS_KILLED"/>457	<value value="0x19" name="SP_ICL1_REQUESTS"/>458	<value value="0x1a" name="SP_ICL1_MISSES"/>459	<value value="0x1b" name="SP_ICL0_REQUESTS"/>460	<value value="0x1c" name="SP_ICL0_MISSES"/>461	<value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>462	<value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>463	<value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>464	<value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>465	<value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>466	<value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>467	<value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>468	<value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>469</enum>470 471<enum name="a3xx_tp_perfcounter_select">472	<value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>473	<value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>474	<value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>475	<value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>476	<value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>477	<value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>478	<value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>479	<value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>480	<value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>481	<value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>482	<value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>483	<value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>484	<value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>485	<value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>486	<value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>487	<value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>488	<value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>489	<value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>490	<value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>491	<value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>492	<value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>493	<value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>494	<value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>495	<value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>496	<value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>497	<value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>498	<value value="0x1a" name="TPL1_TPPERF_LATENCY"/>499	<value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>500</enum>501 502<enum name="a3xx_vfd_perfcounter_select">503	<value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>504	<value value="1" name="VFD_PERF_UCHE_TRANS"/>505	<value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>506	<value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>507	<value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>508	<value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>509	<value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>510	<value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>511	<value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>512	<value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>513</enum>514 515<enum name="a3xx_vpc_perfcounter_select">516	<value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>517	<value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>518	<value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>519	<value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>520	<value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>521	<value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>522</enum>523 524<enum name="a3xx_uche_perfcounter_select">525	<value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>526	<value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>527	<value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>528	<value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>529	<value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>530	<value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>531	<value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>532	<value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>533	<value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>534	<value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>535	<value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>536	<value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>537	<value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>538	<value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>539	<value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>540	<value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>541	<value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>542	<value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>543</enum>544 545<enum name="a3xx_intp_mode">546	<value name="SMOOTH" value="0"/>547	<value name="FLAT" value="1"/>548	<value name="ZERO" value="2"/>549	<value name="ONE" value="3"/>550</enum>551 552<enum name="a3xx_repl_mode">553	<value name="S" value="1"/>554	<value name="T" value="2"/>555	<value name="ONE_T" value="3"/>556</enum>557 558<domain name="A3XX" width="32">559	<!-- RBBM registers -->560	<reg32 offset="0x0000" name="RBBM_HW_VERSION"/>561	<reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>562	<reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>563	<reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>564	<reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>565	<reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>566	<reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>567	<reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>568	<reg32 offset="0x0022" name="RBBM_AHB_CMD"/>569	<reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>570	<reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>571	<reg32 offset="0x0030" name="RBBM_STATUS">572		<bitfield name="HI_BUSY" pos="0" type="boolean"/>573		<bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>574		<bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>575		<bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>576		<bitfield name="VBIF_BUSY" pos="15" type="boolean"/>577		<bitfield name="TSE_BUSY" pos="16" type="boolean"/>578		<bitfield name="RAS_BUSY" pos="17" type="boolean"/>579		<bitfield name="RB_BUSY" pos="18" type="boolean"/>580		<bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>581		<bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>582		<bitfield name="VFD_BUSY" pos="21" type="boolean"/>583		<bitfield name="VPC_BUSY" pos="22" type="boolean"/>584		<bitfield name="UCHE_BUSY" pos="23" type="boolean"/>585		<bitfield name="SP_BUSY" pos="24" type="boolean"/>586		<bitfield name="TPL1_BUSY" pos="25" type="boolean"/>587		<bitfield name="MARB_BUSY" pos="26" type="boolean"/>588		<bitfield name="VSC_BUSY" pos="27" type="boolean"/>589		<bitfield name="ARB_BUSY" pos="28" type="boolean"/>590		<bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>591		<bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>592		<bitfield name="GPU_BUSY" pos="31" type="boolean"/>593	</reg32>594	<!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->595	<reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>596	<reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>597	<reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>598	<reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>599	<reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>600	<reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>601	<reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>602 603	<bitset name="A3XX_INT0">604		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>605		<bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>606		<bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>607		<bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>608		<bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>609		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>610		<bitfield name="VFD_ERROR" pos="6" type="boolean"/>611		<bitfield name="CP_SW_INT" pos="7" type="boolean"/>612		<bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>613		<bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>614		<bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>615		<bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>616		<bitfield name="CP_DMA" pos="12" type="boolean"/>617		<bitfield name="CP_IB2_INT" pos="13" type="boolean"/>618		<bitfield name="CP_IB1_INT" pos="14" type="boolean"/>619		<bitfield name="CP_RB_INT" pos="15" type="boolean"/>620		<bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>621		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>622		<bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>623		<bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>624		<bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>625		<bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>626		<bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>627		<bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>628	</bitset>629 630 631	<!--632		set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare633		to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx634		way for fw to raise and irq:635	 -->636	<reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>637	<reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>638	<reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>639	<reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>640	<reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">641		<bitfield name="ENABLE" pos="0" type="boolean"/>642	</reg32>643	<reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>644	<reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>645	<reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>646	<reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>647	<reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>648	<reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>649	<reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>650	<reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>651	<reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>652	<reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>653	<reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>654	<reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>655	<reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>656	<reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>657	<reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>658	<reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>659	<reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>660	<reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>661	<reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>662	<reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>663	<reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>664	<reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>665	<reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>666	<reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>667	<reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>668	<reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>669	<reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>670	<reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>671	<reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>672	<reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>673	<reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>674	<reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>675	<reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>676	<reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>677	<reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>678	<reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>679	<reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>680	<reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>681	<reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>682	<reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>683	<reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>684	<reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>685	<reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>686	<reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>687	<reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>688	<reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>689	<reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>690	<reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>691	<reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>692	<reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>693	<reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>694	<reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>695	<reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>696	<reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>697	<reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>698	<reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>699	<reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>700	<reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>701	<reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>702	<reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>703	<reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>704	<reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>705	<reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>706	<reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>707	<reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>708	<reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>709	<reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>710	<reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>711	<reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>712	<reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>713	<reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>714	<reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>715	<reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>716	<reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>717	<reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>718	<reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>719	<reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>720	<reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>721	<reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>722	<reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>723	<reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>724	<reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>725	<reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>726	<reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>727	<reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>728	<reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>729	<reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>730	<reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>731	<reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>732	<reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>733	<reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>734	<reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>735	<reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>736	<reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>737	<reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>738	<reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>739	<reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>740	<reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>741	<reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>742	<reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>743 744	<!-- CP registers -->745	<reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>746	<reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>747	<reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>748	<reg32 offset="0x01cd" name="CP_ROQ_DATA"/>749	<reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>750	<reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>751	<reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>752	<!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->753	<reg32 offset="0x01da" name="CP_MEQ_ADDR"/>754	<reg32 offset="0x01db" name="CP_MEQ_DATA"/>755	<reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>756	<reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>757 758	<reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>759	<reg32 offset="0x045c" name="CP_HW_FAULT"/>760	<reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>761	<reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>762	<array offset="0x0460" name="CP_PROTECT" stride="1" length="16">763		<reg32 offset="0x0" name="REG"/>764	</array>765	<reg32 offset="0x054d" name="CP_AHB_FAULT"/>766 767	<reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>768	<reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>769	<reg32 offset="0x0e1e" name="TP0_CHICKEN"/>770 771	<!-- these I guess or either SP or HLSQ since related to shader core setup: -->772	<reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">773		<doc>774			The pair of MEM_SIZE/ADDR registers get programmed775			in sequence with the size/addr of each buffer.776		</doc>777	</reg32>778	<reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>779 780	<!-- GRAS registers -->781	<reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">782		<bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/>783		<bitfield name="IJ_NON_PERSP_CENTER" pos="13" type="boolean"/>784		<bitfield name="IJ_PERSP_CENTROID" pos="14" type="boolean"/>785		<bitfield name="IJ_NON_PERSP_CENTROID" pos="15" type="boolean"/>786		<bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>787		<bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>788		<bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>789		<bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>790		<bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>791		<bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">792			<doc>aka clip_halfz</doc>793		</bitfield>794		<!-- set when gl_FragCoord.z is enabled in frag shader: -->795		<bitfield name="ZCOORD" pos="23" type="boolean"/>796		<bitfield name="WCOORD" pos="24" type="boolean"/>797		<!-- set when frag shader writes z (so early z test disabled: -->798		<bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>799		<bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>800	</reg32>801	<reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">802		<bitfield name="HORZ" low="0" high="9" type="uint"/>803		<bitfield name="VERT" low="10" high="19" type="uint"/>804	</reg32>805	<reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>806	<reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>807	<reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>808	<reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>809	<reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>810	<reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>811	<reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">812		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>813		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>814	</reg32>815	<reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>816	<reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">817		<bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>818		<doc>range of -8.0 to 8.0</doc>819	</reg32>820	<reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">821		<doc>range of -512.0 to 512.0</doc>822	</reg32>823	<reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">824		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>825		<bitfield name="CULL_BACK" pos="1" type="boolean"/>826		<bitfield name="FRONT_CW" pos="2" type="boolean"/>827		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>828		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>829	</reg32>830	<reg32 offset="0x2072" name="GRAS_SC_CONTROL">831		<!-- complete wild-ass-guess for sizes of these bitfields.. -->832		<bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>833		<bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>834		<bitfield name="RASTER_MODE" low="12" high="15"/>835	</reg32>836 837	<reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>838	<reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>839	<reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>840	<reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>841 842	<!-- RB registers -->843	<reg32 offset="0x20c0" name="RB_MODE_CONTROL">844		<!-- guess on the # of bits here.. -->845		<bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>846		<doc>847			RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS848		</doc>849		<bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>850		<bitfield name="MRT" low="12" high="13" type="uint">851			<doc>render targets - 1</doc>852		</bitfield>853		<bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>854		<bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>855	</reg32>856	<reg32 offset="0x20c1" name="RB_RENDER_CONTROL">857		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>858		<bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>859		<bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>860		<!-- set when gl_FrontFacing is accessed in frag shader: -->861		<bitfield name="FACENESS" pos="3" type="boolean"/>862		<bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>863		<bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>864		<!--865			ENABLE_GMEM not set on mem2gmem..  so possibly it is actually866			controlling blend or readback from GMEM??867		 -->868		<bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>869		<bitfield name="COORD_MASK" low="14" high="17" type="hex"/>870		<bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>871		<bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>872		<bitfield name="ALPHA_TEST" pos="22" type="boolean"/>873		<bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>874		<bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>875		<bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>876	</reg32>877	<reg32 offset="0x20c2" name="RB_MSAA_CONTROL">878		<bitfield name="DISABLE" pos="10" type="boolean"/>879		<bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>880		<bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>881	</reg32>882	<reg32 offset="0x20c3" name="RB_ALPHA_REF">883		<bitfield name="UINT" low="8" high="15" type="hex"/>884		<bitfield name="FLOAT" low="16" high="31" type="float"/>885	</reg32>886	<array offset="0x20c4" name="RB_MRT" stride="4" length="4">887		<reg32 offset="0x0" name="CONTROL">888			<bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>889			<!-- both these bits seem to get set when enabling GL_BLEND.. -->890			<bitfield name="BLEND" pos="4" type="boolean"/>891			<bitfield name="BLEND2" pos="5" type="boolean"/>892			<bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>893			<bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>894			<bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>895		</reg32>896		<reg32 offset="0x1" name="BUF_INFO">897			<bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>898			<bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>899			<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>900			<bitfield name="COLOR_SRGB" pos="14" type="boolean"/>901			<doc>902				Pitch (actually, appears to be pitch in bytes, so really is a stride)903				in GMEM, so pitch of the current tile.904			</doc>905			<bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>906		</reg32>907		<reg32 offset="0x2" name="BUF_BASE">908			<doc>offset into GMEM (or system memory address in bypass mode)</doc>909			<bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>910		</reg32>911		<reg32 offset="0x3" name="BLEND_CONTROL">912			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>913			<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>914			<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>915			<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>916			<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>917			<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>918			<bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>919		</reg32>920	</array>921 922	<reg32 offset="0x20e4" name="RB_BLEND_RED">923		<bitfield name="UINT" low="0" high="7" type="hex"/>924		<bitfield name="FLOAT" low="16" high="31" type="float"/>925	</reg32>926	<reg32 offset="0x20e5" name="RB_BLEND_GREEN">927		<bitfield name="UINT" low="0" high="7" type="hex"/>928		<bitfield name="FLOAT" low="16" high="31" type="float"/>929	</reg32>930	<reg32 offset="0x20e6" name="RB_BLEND_BLUE">931		<bitfield name="UINT" low="0" high="7" type="hex"/>932		<bitfield name="FLOAT" low="16" high="31" type="float"/>933	</reg32>934	<reg32 offset="0x20e7" name="RB_BLEND_ALPHA">935		<bitfield name="UINT" low="0" high="7" type="hex"/>936		<bitfield name="FLOAT" low="16" high="31" type="float"/>937	</reg32>938 939	<reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>940	<reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>941	<reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>942	<reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>943	<reg32 offset="0x20ec" name="RB_COPY_CONTROL">944		<!-- not sure # of bits -->945		<bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>946		<bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>947		<bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>948		<bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>949		<bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>950		<bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->951		<bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>952	</reg32>953	<reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">954		<bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>955	</reg32>956	<reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">957		<doc>actually, appears to be pitch in bytes, so really is a stride</doc>958		<!-- not actually sure about max pitch... -->959		<bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>960	</reg32>961	<reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">962		<bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>963		<bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>964		<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>965		<bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>966		<bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>967		<bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>968	</reg32>969	<reg32 offset="0x2100" name="RB_DEPTH_CONTROL">970		<!--971			guessing that this matches a2xx with the stencil fields972			moved out into RB_STENCIL_CONTROL?973		 -->974		<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>975		<bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>976		<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>977		<bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>978		<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>979		<bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>980		<doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>981		<bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>982	</reg32>983	<reg32 offset="0x2101" name="RB_DEPTH_CLEAR">984		<doc>seems to be always set to 0x00000000</doc>985	</reg32>986	<reg32 offset="0x2102" name="RB_DEPTH_INFO">987		<bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>988		<doc>989			DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie990			bin_w * bin_h / 1024 (possible rounded up to multiple of991			something??  ie. 39 becomes 40, 78 becomes 80.. 75 becomes992			80.. so maybe it needs to be multiple of 8??993		</doc>994		<bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>995	</reg32>996	<reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">997		<doc>998			Pitch of depth buffer or combined depth+stencil buffer999			in z24s8 cases.1000		</doc>1001	</reg32>1002	<reg32 offset="0x2104" name="RB_STENCIL_CONTROL">1003		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>1004		<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>1005		<!--1006			set for stencil operations that require read from stencil1007			buffer, but not for example for stencil clear (which does1008			not require read).. so guessing this is analogous to1009			READ_DEST_ENABLE for color buffer..1010		 -->1011		<bitfield name="STENCIL_READ" pos="2" type="boolean"/>1012		<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>1013		<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>1014		<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>1015		<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>1016		<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>1017		<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>1018		<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>1019		<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>1020	</reg32>1021	<reg32 offset="0x2105" name="RB_STENCIL_CLEAR">1022		<doc>seems to be always set to 0x00000000</doc>1023	</reg32>1024	<reg32 offset="0x2106" name="RB_STENCIL_INFO">1025		<doc>Base address for stencil when not using interleaved depth/stencil</doc>1026		<bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>1027	</reg32>1028	<reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">1029		<doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>1030	</reg32>1031	<reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>1032	<reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>1033	<!-- VSC == visibility stream c?? -->1034	<reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">1035		<doc>seems to be set to 0x00000002 during binning pass</doc>1036		<bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>1037	</reg32>1038	<reg32 offset="0x210e" name="RB_WINDOW_OFFSET">1039		<doc>X/Y offset of current bin</doc>1040		<bitfield name="X" low="0" high="15" type="uint"/>1041		<bitfield name="Y" low="16" high="31" type="uint"/>1042	</reg32>1043	<reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">1044		<bitfield name="RESET" pos="0" type="boolean"/>1045		<bitfield name="COPY" pos="1" type="boolean"/>1046	</reg32>1047	<reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>1048	<reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>1049	<reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>1050 1051	<!-- PC registers -->1052	<reg32 offset="0x21e1" name="VGT_BIN_BASE">1053		<doc>1054			seems to be where firmware writes BIN_DATA_ADDR from1055			CP_SET_BIN_DATA packet..  probably should be called1056			PC_BIN_BASE (just using name from yamato for now)1057		</doc>1058	</reg32>1059	<reg32 offset="0x21e2" name="VGT_BIN_SIZE">1060		<doc>probably should be PC_BIN_SIZE</doc>1061	</reg32>1062	<reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">1063		<doc>SIZE is current pipe width * height (in tiles)</doc>1064		<bitfield name="SIZE" low="16" high="21" type="uint"/>1065		<doc>1066			N is some sort of slot # between 0..(SIZE-1).  In case1067			multiple tiles use same pipe, each tile gets unique slot #1068		</doc>1069		<bitfield name="N" low="22" high="26" type="uint"/>1070	</reg32>1071	<reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>1072	<reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">1073		<doc>1074			STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 41075			(but, in cases where you'd expect 1, the blob driver uses1076			2, so possibly 0 (no varying) or minimum of 2)1077		</doc>1078		<bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>1079		<bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>1080		<bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>1081		<bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>1082		<bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>1083		<bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>1084		<!-- PSIZE bit set if gl_PointSize written: -->1085		<bitfield name="PSIZE" pos="26" type="boolean"/>1086	</reg32>1087	<reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>1088 1089	<!-- HLSQ registers -->1090	<bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">1091		<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>1092		<bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>1093		<bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>1094	</bitset>1095	<bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">1096		<!-- are these a3xx_regid?? -->1097		<bitfield name="STARTENTRY" low="0" high="8"/>1098		<bitfield name="ENDENTRY" low="16" high="24"/>1099	</bitset>1100 1101	<reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">1102		<bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>1103		<bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>1104		<bitfield name="COMPUTEMODE" pos="8" type="boolean"/>1105		<bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>1106		<bitfield name="RESERVED2" pos="10" type="boolean"/>1107		<bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>1108		<bitfield name="FSONLYTEX" pos="25" type="boolean"/>1109		<bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>1110		<bitfield name="CONSTMODE" pos="27" type="uint"/>1111		<bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>1112		<bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>1113		<bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>1114		<bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>1115	</reg32>1116	<reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">1117		<bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>1118		<bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>1119		<bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>1120		<bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>1121	</reg32>1122	<reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">1123		<bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>1124		<bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>1125		<bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>1126	</reg32>1127	<reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">1128		<bitfield name="IJPERSPCENTERREGID" low="0" high="7" type="a3xx_regid"/>1129		<bitfield name="IJNONPERSPCENTERREGID" low="8" high="15" type="a3xx_regid"/>1130		<bitfield name="IJPERSPCENTROIDREGID" low="16" high="23" type="a3xx_regid"/>1131		<bitfield name="IJNONPERSPCENTROIDREGID" low="24" high="31" type="a3xx_regid"/>1132	</reg32>1133	<reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>1134	<reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>1135	<reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>1136	<reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>1137	<reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">1138		<bitfield name="WORKDIM" low="0" high="1" type="uint"/>1139		<bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>1140		<bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>1141		<bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>1142	</reg32>1143	<array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">1144		<doc>indexed by dimension</doc>1145		<reg32 offset="0" name="SIZE" type="uint"/>1146		<reg32 offset="1" name="OFFSET" type="uint"/>1147	</array>1148	<reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>1149	<reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>1150	<reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>1151	<array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">1152		<doc>indexed by dimension, global_size / local_size</doc>1153		<reg32 offset="0" name="RATIO" type="uint"/>1154	</array>1155	<reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>1156	<reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>1157	<reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>1158 1159	<!-- VFD registers -->1160	<reg32 offset="0x2240" name="VFD_CONTROL_0">1161		<doc>1162			TOTALATTRTOVS is # of attributes to vertex shader, in register1163			slots (ie. vec4+vec3 -> 7)1164		</doc>1165		<bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>1166		<bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>1167		<doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>1168		<bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>1169		<doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>1170		<bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>1171	</reg32>1172	<reg32 offset="0x2241" name="VFD_CONTROL_1">1173		<doc>MAXSTORAGE could be # of attributes/vbo's</doc>1174		<bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>1175		<bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>1176		<bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>1177		<bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>1178		<bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>1179	</reg32>1180	<reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>1181	<reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>1182	<reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>1183	<reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>1184	<array offset="0x2246" name="VFD_FETCH" stride="2" length="16">1185		<reg32 offset="0x0" name="INSTR_0">1186			<bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>1187			<bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>1188			<bitfield name="INSTANCED" pos="16" type="boolean"/>1189			<bitfield name="SWITCHNEXT" pos="17" type="boolean"/>1190			<bitfield name="INDEXCODE" low="18" high="23" type="uint"/>1191			<bitfield name="STEPRATE" low="24" high="31" type="uint"/>1192		</reg32>1193		<reg32 offset="0x1" name="INSTR_1"/>1194	</array>1195	<array offset="0x2266" name="VFD_DECODE" stride="1" length="16">1196		<reg32 offset="0x0" name="INSTR">1197			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>1198			<!-- not sure if this is a bit flag and another flag above it, or?? -->1199			<bitfield name="CONSTFILL" pos="4" type="boolean"/>1200			<bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>1201			<bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>1202			<bitfield name="INT" pos="20" type="boolean"/>1203			<doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>1204			<bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>1205			<bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>1206			<bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>1207			<bitfield name="SWITCHNEXT" pos="30" type="boolean"/>1208		</reg32>1209	</array>1210	<reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">1211		<bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>1212		<!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->1213		<bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>1214	</reg32>1215 1216	<!-- VPC registers -->1217	<reg32 offset="0x2280" name="VPC_ATTR">1218		<bitfield name="TOTALATTR" low="0" high="8" type="uint"/>1219		<!-- PSIZE bit set if gl_PointSize written: -->1220		<bitfield name="PSIZE" pos="9" type="boolean"/>1221		<bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>1222		<bitfield name="LMSIZE" low="28" high="31" type="uint"/>1223	</reg32>1224	<reg32 offset="0x2281" name="VPC_PACK">1225		<!-- these are always seem to be set to same as TOTALATTR -->1226		<bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>1227		<bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>1228	</reg32>1229	<!--1230		varying interpolate mode.  One field per scalar/component1231		(since varying slots are scalar, so things don't have to1232		be aligned to vec4).1233		4 regs * 16 scalar components each => 16 vec41234	 -->1235	<array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">1236		<reg32 offset="0x0" name="MODE">1237			<bitfield name="C0" low="0"  high="1"  type="a3xx_intp_mode"/>1238			<bitfield name="C1" low="2"  high="3"  type="a3xx_intp_mode"/>1239			<bitfield name="C2" low="4"  high="5"  type="a3xx_intp_mode"/>1240			<bitfield name="C3" low="6"  high="7"  type="a3xx_intp_mode"/>1241			<bitfield name="C4" low="8"  high="9"  type="a3xx_intp_mode"/>1242			<bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>1243			<bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>1244			<bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>1245			<bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>1246			<bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>1247			<bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>1248			<bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>1249			<bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>1250			<bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>1251			<bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>1252			<bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>1253		</reg32>1254	</array>1255	<array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">1256		<reg32 offset="0x0" name="MODE">1257			<bitfield name="C0" low="0"  high="1"  type="a3xx_repl_mode"/>1258			<bitfield name="C1" low="2"  high="3"  type="a3xx_repl_mode"/>1259			<bitfield name="C2" low="4"  high="5"  type="a3xx_repl_mode"/>1260			<bitfield name="C3" low="6"  high="7"  type="a3xx_repl_mode"/>1261			<bitfield name="C4" low="8"  high="9"  type="a3xx_repl_mode"/>1262			<bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>1263			<bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>1264			<bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>1265			<bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>1266			<bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>1267			<bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>1268			<bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>1269			<bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>1270			<bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>1271			<bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>1272			<bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>1273		</reg32>1274	</array>1275	<reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>1276	<reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>1277 1278	<!-- SP registers -->1279	<bitset name="a3xx_vs_fs_length_reg" inline="yes">1280		<bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>1281	</bitset>1282 1283	<bitset name="sp_vs_fs_obj_offset_reg" inline="yes">1284		<bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>1285		<doc>1286			From register spec:1287			SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object1288			start offset in on chip RAM,1289			128bit aligned1290		</doc>1291		<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>1292		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>1293	</bitset>1294 1295	<reg32 offset="0x22c0" name="SP_SP_CTRL_REG">1296		<!-- this bit is set during resolve pass: -->1297		<bitfield name="RESOLVE" pos="16" type="boolean"/>1298		<bitfield name="CONSTMODE" pos="18" type="uint"/>1299		<bitfield name="BINNING" pos="19" type="boolean"/>1300		<bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>1301		<!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->1302		<bitfield name="L0MODE" low="22" high="23" type="uint"/>1303	</reg32>1304	<reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">1305		<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>1306		<bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>1307		<!-- maybe CACHEINVALID is two bits?? -->1308		<bitfield name="CACHEINVALID" pos="2" type="boolean"/>1309		<bitfield name="ALUSCHMODE" pos="3" type="boolean"/>1310		<doc>1311			The full/half register footprint is in units of four components,1312			so if r0.x is used, that counts as all of r0.[xyzw] as used.1313			There are separate full/half register footprint values as the1314			full and half registers are independent (not overlapping).1315			Presumably the thread scheduler hardware allocates the full/half1316			register names from the actual physical register file and1317			handles the register renaming.1318		</doc>1319		<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>1320		<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>1321		<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>1322		<bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>1323		<doc>1324			From regspec:1325			SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.1326			If bit31 is 1, it means overflow1327			or any long shader.1328		</doc>1329		<bitfield name="LENGTH" low="24" high="31" type="uint"/>1330	</reg32>1331	<reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">1332		<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>1333		<!--1334			not sure about full vs half const.. I can't get blob generate1335			something with a mediump/lowp uniform.1336		 -->1337		<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>1338		<bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>1339	</reg32>1340	<reg32 offset="0x22c6" name="SP_VS_PARAM_REG">1341		<bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>1342		<bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>1343		<bitfield name="POS2DMODE" pos="16" type="boolean"/>1344		<bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>1345	</reg32>1346	<array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">1347		<reg32 offset="0x0" name="REG">1348			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>1349			<bitfield name="A_HALF" pos="8" type="boolean"/>1350			<bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>1351			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>1352			<bitfield name="B_HALF" pos="24" type="boolean"/>1353			<bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>1354		</reg32>1355	</array>1356	<array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">1357		<reg32 offset="0x0" name="REG">1358			<doc>1359				These seem to be offsets for storage of the varyings.1360				Always seems to start from 8, possibly loc 0 and 41361				are for gl_Position and gl_PointSize?1362			</doc>1363			<bitfield name="OUTLOC0" low="0" high="6" type="uint"/>1364			<bitfield name="OUTLOC1" low="8" high="14" type="uint"/>1365			<bitfield name="OUTLOC2" low="16" high="22" type="uint"/>1366			<bitfield name="OUTLOC3" low="24" high="30" type="uint"/>1367		</reg32>1368	</array>1369	<reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>1370	<doc>1371		SP_VS_OBJ_START_REG contains pointer to the vertex shader program,1372		immediately followed by the binning shader program (although I1373		guess that is probably just re-using the same gpu buffer)1374	</doc>1375	<reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>1376	<reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">1377		<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="7">1378			<doc>The size of memory that ldp/stp can address, in 128 byte increments.</doc>1379		</bitfield>1380		<bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>1381		<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>1382	</reg32>1383	<reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">1384		<bitfield name="BURSTLEN" low="0" high="4"/>1385		<bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>1386	</reg32>1387	<reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>1388	<reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>1389	<reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">1390		<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>1391		<bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>1392		<!-- maybe CACHEINVALID is two bits?? -->1393		<bitfield name="CACHEINVALID" pos="2" type="boolean"/>1394		<bitfield name="ALUSCHMODE" pos="3" type="boolean"/>1395		<doc>1396			The full/half register footprint is in units of four components,1397			so if r0.x is used, that counts as all of r0.[xyzw] as used.1398			There are separate full/half register footprint values as the1399			full and half registers are independent (not overlapping).1400			Presumably the thread scheduler hardware allocates the full/half1401			register names from the actual physical register file and1402			handles the register renaming.1403		</doc>1404		<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>1405		<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>1406		<bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>1407		<bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>1408		<bitfield name="OUTORDERED" pos="19" type="boolean"/>1409		<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>1410		<bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>1411		<bitfield name="PIXLODENABLE" pos="22" type="boolean"/>1412		<bitfield name="COMPUTEMODE" pos="23" type="boolean"/>1413		<doc>1414			From regspec:1415			SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.1416			If bit31 is 1, it means overflow1417			or any long shader.1418		</doc>1419		<bitfield name="LENGTH" low="24" high="31" type="uint"/>1420	</reg32>1421	<reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">1422		<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>1423		<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>1424		<bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>1425		<bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>1426	</reg32>1427	<reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>1428	<doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>1429	<reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>1430	<reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">1431		<bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>1432		<bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>1433		<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>1434	</reg32>1435	<reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">1436		<bitfield name="BURSTLEN" low="0" high="4"/>1437		<bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>1438	</reg32>1439	<reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>1440	<reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">1441		<doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>1442	</reg32>1443	<reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">1444		<doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>1445	</reg32>1446	<reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">1447		<bitfield name="MRT" low="0" high="1" type="uint">1448			<doc>render targets - 1</doc>1449		</bitfield>1450		<bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>1451		<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>1452	</reg32>1453	<array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">1454		<reg32 offset="0x0" name="REG">1455			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>1456			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>1457			<bitfield name="SINT" pos="10" type="boolean"/>1458			<bitfield name="UINT" pos="11" type="boolean"/>1459		</reg32>1460	</array>1461	<array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">1462		<reg32 offset="0x0" name="REG">1463			<bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>1464		</reg32>1465	</array>1466	<reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>1467 1468	<reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>1469	<!-- TPL1 registers -->1470	<!-- assume VS/FS_TEX_OFFSET is same -->1471	<bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">1472		<bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>1473		<bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>1474		<!-- not sure the size of this: -->1475		<bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>1476	</bitset>1477	<reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>1478	<reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>1479	<reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>1480	<reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>1481 1482	<!-- VBIF registers -->1483	<reg32 offset="0x3001" name="VBIF_CLKON"/>1484	<reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>1485	<reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>1486	<reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>1487	<reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>1488	<reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>1489	<reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>1490	<reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>1491	<reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>1492	<reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>1493	<reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>1494	<reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>1495	<reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>1496	<reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>1497	<reg32 offset="0x303c" name="VBIF_ARB_CTL"/>1498	<reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>1499	<reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>1500	<reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>1501	<reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>1502 1503	<bitset name="a3xx_vbif_perf_cnt" inline="yes">1504		<bitfield name="CNT0" pos="0" type="boolean"/>1505		<bitfield name="CNT1" pos="1" type="boolean"/>1506		<bitfield name="PWRCNT0" pos="2" type="boolean"/>1507		<bitfield name="PWRCNT1" pos="3" type="boolean"/>1508		<bitfield name="PWRCNT2" pos="4" type="boolean"/>1509	</bitset>1510 1511	<reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>1512	<reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>1513	<reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>1514	<reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>1515	<reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>1516	<reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>1517	<reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>1518	<reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>1519	<reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>1520	<reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>1521	<reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>1522	<reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>1523	<reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>1524 1525 1526	<reg32 offset="0x0c01" name="VSC_BIN_SIZE">1527		<bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>1528		<bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>1529	</reg32>1530 1531	<reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>1532	<array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">1533		<reg32 offset="0x0" name="CONFIG">1534			<doc>1535				Configures the mapping between VSC_PIPE buffer and1536				bin, X/Y specify the bin index in the horiz/vert1537				direction (0,0 is upper left, 0,1 is leftmost bin1538				on second row, and so on).  W/H specify the number1539				of bins assigned to this VSC_PIPE in the horiz/vert1540				dimension.1541			</doc>1542			<bitfield name="X" low="0" high="9" type="uint"/>1543			<bitfield name="Y" low="10" high="19" type="uint"/>1544			<bitfield name="W" low="20" high="23" type="uint"/>1545			<bitfield name="H" low="24" high="27" type="uint"/>1546		</reg32>1547		<reg32 offset="0x1" name="DATA_ADDRESS"/>1548		<reg32 offset="0x2" name="DATA_LENGTH"/>1549	</array>1550	<reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">1551		<doc>seems to be set to 0x00000001 during binning pass</doc>1552		<bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>1553	</reg32>1554	<reg32 offset="0x0c3d" name="UNKNOWN_0C3D">1555		<doc>seems to be always set to 0x00000001</doc>1556	</reg32>1557	<reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>1558	<reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>1559	<reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>1560	<reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>1561	<reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">1562		<doc>seems to be always set to 0x00000001</doc>1563	</reg32>1564 1565	<reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>1566	<reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>1567	<reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>1568	<reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>1569	<array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">1570		<reg32 offset="0x0" name="X"/>1571		<reg32 offset="0x1" name="Y"/>1572		<reg32 offset="0x2" name="Z"/>1573		<reg32 offset="0x3" name="W"/>1574	</array>1575	<reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>1576	<reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>1577	<reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>1578	<reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>1579	<reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">1580		<bitfield name="WIDTH" low="0" high="13" type="uint"/>1581		<bitfield name="HEIGHT" low="14" high="27" type="uint"/>1582	</reg32>1583	<reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>1584	<reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>1585	<reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>1586	<reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>1587	<reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>1588	<reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>1589	<reg32 offset="0x0e43" name="UNKNOWN_0E43">1590		<doc>seems to be always set to 0x00000001</doc>1591	</reg32>1592	<reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>1593	<reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>1594	<reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>1595	<reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>1596	<reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>1597	<reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>1598	<reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>1599	<reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>1600	<reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>1601	<reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>1602	<reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>1603	<reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>1604	<reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>1605	<reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">1606		<!-- might be shifted right by 5, assuming 32byte cache line size.. -->1607		<bitfield name="ADDR" low="0" high="27" type="hex"/>1608	</reg32>1609	<reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">1610		<!-- might be shifted right by 5, assuming 32byte cache line size.. -->1611		<bitfield name="ADDR" low="0" high="27" type="hex"/>1612		<!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->1613		<bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>1614		<bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>1615	</reg32>1616	<reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>1617	<reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>1618	<reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>1619	<reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>1620	<reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>1621	<reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>1622	<reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>1623	<reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>1624	<reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>1625	<reg32 offset="0x0ee0" name="UNKNOWN_0EE0">1626		<doc>seems to be always set to 0x00000003</doc>1627	</reg32>1628	<reg32 offset="0x0f03" name="UNKNOWN_0F03">1629		<doc>seems to be always set to 0x00000001</doc>1630	</reg32>1631	<reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>1632	<reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>1633	<reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>1634	<reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>1635	<reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>1636	<reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>1637 1638	<!-- this seems to be the register that CP_RUN_OPENCL writes: -->1639	<reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>1640 1641	<!-- seems to be same as a2xx according to fwdump.. -->1642	<reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>1643	<reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>1644	<reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>1645</domain>1646 1647<domain name="A3XX_TEX_SAMP" width="32">1648	<doc>Texture sampler dwords</doc>1649	<enum name="a3xx_tex_filter">1650		<value name="A3XX_TEX_NEAREST" value="0"/>1651		<value name="A3XX_TEX_LINEAR" value="1"/>1652		<value name="A3XX_TEX_ANISO" value="2"/>1653	</enum>1654	<enum name="a3xx_tex_clamp">1655		<value name="A3XX_TEX_REPEAT" value="0"/>1656		<value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>1657		<value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>1658		<value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>1659		<value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>1660	</enum>1661	<enum name="a3xx_tex_aniso">1662		<value name="A3XX_TEX_ANISO_1" value="0"/>1663		<value name="A3XX_TEX_ANISO_2" value="1"/>1664		<value name="A3XX_TEX_ANISO_4" value="2"/>1665		<value name="A3XX_TEX_ANISO_8" value="3"/>1666		<value name="A3XX_TEX_ANISO_16" value="4"/>1667	</enum>1668	<reg32 offset="0" name="0">1669		<bitfield name="CLAMPENABLE" pos="0" type="boolean"/>1670		<bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>1671		<bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>1672		<bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>1673		<bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>1674		<bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>1675		<bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>1676		<bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>1677		<bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>1678		<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>1679		<!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->1680		<bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>1681	</reg32>1682	<reg32 offset="1" name="1">1683		<bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>1684		<bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>1685		<bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>1686	</reg32>1687</domain>1688 1689<domain name="A3XX_TEX_CONST" width="32">1690	<doc>Texture constant dwords</doc>1691	<enum name="a3xx_tex_swiz">1692		<!-- same as a2xx? -->1693		<value name="A3XX_TEX_X" value="0"/>1694		<value name="A3XX_TEX_Y" value="1"/>1695		<value name="A3XX_TEX_Z" value="2"/>1696		<value name="A3XX_TEX_W" value="3"/>1697		<value name="A3XX_TEX_ZERO" value="4"/>1698		<value name="A3XX_TEX_ONE" value="5"/>1699	</enum>1700	<enum name="a3xx_tex_type">1701		<value name="A3XX_TEX_1D" value="0"/>1702		<value name="A3XX_TEX_2D" value="1"/>1703		<value name="A3XX_TEX_CUBE" value="2"/>1704		<value name="A3XX_TEX_3D" value="3"/>1705	</enum>1706	<enum name="a3xx_tex_msaa">1707		<value name="A3XX_TPL1_MSAA1X" value="0"/>1708		<value name="A3XX_TPL1_MSAA2X" value="1"/>1709		<value name="A3XX_TPL1_MSAA4X" value="2"/>1710		<value name="A3XX_TPL1_MSAA8X" value="3"/>1711	</enum>1712	<reg32 offset="0" name="0">1713		<bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>1714		<bitfield name="SRGB" pos="2" type="boolean"/>1715		<bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>1716		<bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>1717		<bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>1718		<bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>1719		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>1720		<bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>1721		<bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>1722		<bitfield name="NOCONVERT" pos="29" type="boolean"/>1723		<bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>1724	</reg32>1725	<reg32 offset="1" name="1">1726		<bitfield name="HEIGHT" low="0" high="13" type="uint"/>1727		<bitfield name="WIDTH" low="14" high="27" type="uint"/>1728		<!-- minimum pitch (for mipmap levels): log2(pitchalign / 16) -->1729		<bitfield name="PITCHALIGN" low="28" high="31" type="uint"/>1730	</reg32>1731	<reg32 offset="2" name="2">1732		<doc>INDX is index of texture address(es) in MIPMAP state block</doc>1733		<bitfield name="INDX" low="0" high="8" type="uint"/>1734		<doc>Pitch in bytes (so actually stride)</doc>1735		<bitfield name="PITCH" low="12" high="29" type="uint"/>1736		<doc>SWAP bit is set for BGRA instead of RGBA</doc>1737		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>1738	</reg32>1739	<reg32 offset="3" name="3">1740		<!--1741		Update: the two LAYERSZn seem not to be the same thing.1742		According to Ilia's experimentation the first one goes up1743		to at *least* bit 14..1744		 -->1745		<bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>1746		<bitfield name="DEPTH" low="17" high="27" type="uint"/>1747		<bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>1748	</reg32>1749</domain>1750 1751</database>1752