brintos / linux-shallow public Read only

1<?xml version="1.0" encoding="UTF-8"?>2<database xmlns="http://nouveau.freedesktop.org/"3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">5<import file="freedreno_copyright.xml"/>6<import file="adreno/adreno_common.xml"/>7<import file="adreno/adreno_pm4.xml"/>8 9<!--10Each register that is actually being used by driver should have "usage" defined,11currently there are following usages:12- "cmd" - the register is used outside of renderpass and blits,13		roughly corresponds to registers used in ib1 for Freedreno14- "rp_blit" - the register is used inside renderpass or blits15		(ib2 for Freedreno)16 17It is expected that register with "cmd" usage may be written into only at18the start of the command buffer (ib1), while "rp_blit" usage indicates that register19is either overwritten by renderpass/blit (ib2) or not used if not overwritten20by a particular renderpass/blit.21-->22 23<!-- these might be same as a5xx -->24<enum name="a6xx_tile_mode">25	<value name="TILE6_LINEAR" value="0"/>26	<value name="TILE6_2" value="2"/>27	<value name="TILE6_3" value="3"/>28</enum>29 30<enum name="a6xx_format">31	<value value="0x02" name="FMT6_A8_UNORM"/>32	<value value="0x03" name="FMT6_8_UNORM"/>33	<value value="0x04" name="FMT6_8_SNORM"/>34	<value value="0x05" name="FMT6_8_UINT"/>35	<value value="0x06" name="FMT6_8_SINT"/>36 37	<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>38	<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>39	<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->40	<value value="0x0e" name="FMT6_5_6_5_UNORM"/>41 42	<value value="0x0f" name="FMT6_8_8_UNORM"/>43	<value value="0x10" name="FMT6_8_8_SNORM"/>44	<value value="0x11" name="FMT6_8_8_UINT"/>45	<value value="0x12" name="FMT6_8_8_SINT"/>46	<value value="0x13" name="FMT6_L8_A8_UNORM"/>47 48	<value value="0x15" name="FMT6_16_UNORM"/>49	<value value="0x16" name="FMT6_16_SNORM"/>50	<value value="0x17" name="FMT6_16_FLOAT"/>51	<value value="0x18" name="FMT6_16_UINT"/>52	<value value="0x19" name="FMT6_16_SINT"/>53 54	<value value="0x21" name="FMT6_8_8_8_UNORM"/>55	<value value="0x22" name="FMT6_8_8_8_SNORM"/>56	<value value="0x23" name="FMT6_8_8_8_UINT"/>57	<value value="0x24" name="FMT6_8_8_8_SINT"/>58 59	<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>60	<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->61	<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>62	<value value="0x33" name="FMT6_8_8_8_8_UINT"/>63	<value value="0x34" name="FMT6_8_8_8_8_SINT"/>64 65	<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>66 67	<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>68	<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>69	<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>70	<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>71	<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>72 73	<value value="0x42" name="FMT6_11_11_10_FLOAT"/>74 75	<value value="0x43" name="FMT6_16_16_UNORM"/>76	<value value="0x44" name="FMT6_16_16_SNORM"/>77	<value value="0x45" name="FMT6_16_16_FLOAT"/>78	<value value="0x46" name="FMT6_16_16_UINT"/>79	<value value="0x47" name="FMT6_16_16_SINT"/>80 81	<value value="0x48" name="FMT6_32_UNORM"/>82	<value value="0x49" name="FMT6_32_SNORM"/>83	<value value="0x4a" name="FMT6_32_FLOAT"/>84	<value value="0x4b" name="FMT6_32_UINT"/>85	<value value="0x4c" name="FMT6_32_SINT"/>86	<value value="0x4d" name="FMT6_32_FIXED"/>87 88	<value value="0x58" name="FMT6_16_16_16_UNORM"/>89	<value value="0x59" name="FMT6_16_16_16_SNORM"/>90	<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>91	<value value="0x5b" name="FMT6_16_16_16_UINT"/>92	<value value="0x5c" name="FMT6_16_16_16_SINT"/>93 94	<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>95	<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>96	<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>97	<value value="0x63" name="FMT6_16_16_16_16_UINT"/>98	<value value="0x64" name="FMT6_16_16_16_16_SINT"/>99 100	<value value="0x65" name="FMT6_32_32_UNORM"/>101	<value value="0x66" name="FMT6_32_32_SNORM"/>102	<value value="0x67" name="FMT6_32_32_FLOAT"/>103	<value value="0x68" name="FMT6_32_32_UINT"/>104	<value value="0x69" name="FMT6_32_32_SINT"/>105	<value value="0x6a" name="FMT6_32_32_FIXED"/>106 107	<value value="0x70" name="FMT6_32_32_32_UNORM"/>108	<value value="0x71" name="FMT6_32_32_32_SNORM"/>109	<value value="0x72" name="FMT6_32_32_32_UINT"/>110	<value value="0x73" name="FMT6_32_32_32_SINT"/>111	<value value="0x74" name="FMT6_32_32_32_FLOAT"/>112	<value value="0x75" name="FMT6_32_32_32_FIXED"/>113 114	<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>115	<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>116	<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>117	<value value="0x83" name="FMT6_32_32_32_32_UINT"/>118	<value value="0x84" name="FMT6_32_32_32_32_SINT"/>119	<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>120 121	<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->122	<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->123	<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->124	<value value="0x8f" name="FMT6_NV21"/>125	<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->126 127	<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>128 129	<!-- Note: tiling/UBWC for these may be different from equivalent formats130	For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM131	-->132	<value value="0x94" name="FMT6_NV12_Y"/>133	<value value="0x95" name="FMT6_NV12_UV"/>134	<value value="0x96" name="FMT6_NV12_VU"/>135	<value value="0x97" name="FMT6_NV12_4R"/>136	<value value="0x98" name="FMT6_NV12_4R_Y"/>137	<value value="0x99" name="FMT6_NV12_4R_UV"/>138	<value value="0x9a" name="FMT6_P010"/>139	<value value="0x9b" name="FMT6_P010_Y"/>140	<value value="0x9c" name="FMT6_P010_UV"/>141	<value value="0x9d" name="FMT6_TP10"/>142	<value value="0x9e" name="FMT6_TP10_Y"/>143	<value value="0x9f" name="FMT6_TP10_UV"/>144 145	<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>146 147	<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>148	<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>149	<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>150	<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>151	<value value="0xaf" name="FMT6_ETC1"/>152	<value value="0xb0" name="FMT6_ETC2_RGB8"/>153	<value value="0xb1" name="FMT6_ETC2_RGBA8"/>154	<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>155	<value value="0xb3" name="FMT6_DXT1"/>156	<value value="0xb4" name="FMT6_DXT3"/>157	<value value="0xb5" name="FMT6_DXT5"/>158	<value value="0xb7" name="FMT6_RGTC1_UNORM"/>159	<value value="0xb8" name="FMT6_RGTC1_SNORM"/>160	<value value="0xbb" name="FMT6_RGTC2_UNORM"/>161	<value value="0xbc" name="FMT6_RGTC2_SNORM"/>162	<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>163	<value value="0xbf" name="FMT6_BPTC_FLOAT"/>164	<value value="0xc0" name="FMT6_BPTC"/>165	<value value="0xc1" name="FMT6_ASTC_4x4"/>166	<value value="0xc2" name="FMT6_ASTC_5x4"/>167	<value value="0xc3" name="FMT6_ASTC_5x5"/>168	<value value="0xc4" name="FMT6_ASTC_6x5"/>169	<value value="0xc5" name="FMT6_ASTC_6x6"/>170	<value value="0xc6" name="FMT6_ASTC_8x5"/>171	<value value="0xc7" name="FMT6_ASTC_8x6"/>172	<value value="0xc8" name="FMT6_ASTC_8x8"/>173	<value value="0xc9" name="FMT6_ASTC_10x5"/>174	<value value="0xca" name="FMT6_ASTC_10x6"/>175	<value value="0xcb" name="FMT6_ASTC_10x8"/>176	<value value="0xcc" name="FMT6_ASTC_10x10"/>177	<value value="0xcd" name="FMT6_ASTC_12x10"/>178	<value value="0xce" name="FMT6_ASTC_12x12"/>179 180	<!-- for sampling stencil (integer, 2nd channel), not available on a630 -->181	<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>182 183	<!-- Not a hw enum, used internally in driver -->184	<value value="0xff" name="FMT6_NONE"/>185 186</enum>187 188<!-- probably same as a5xx -->189<enum name="a6xx_polygon_mode">190	<value name="POLYMODE6_POINTS" value="1"/>191	<value name="POLYMODE6_LINES" value="2"/>192	<value name="POLYMODE6_TRIANGLES" value="3"/>193</enum>194 195<enum name="a6xx_depth_format">196	<value name="DEPTH6_NONE" value="0"/>197	<value name="DEPTH6_16" value="1"/>198	<value name="DEPTH6_24_8" value="2"/>199	<value name="DEPTH6_32" value="4"/>200</enum>201 202<bitset name="a6x_cp_protect" inline="yes">203	<bitfield name="BASE_ADDR" low="0" high="17"/>204	<bitfield name="MASK_LEN" low="18" high="30"/>205	<bitfield name="READ" pos="31" type="boolean"/>206</bitset>207 208<enum name="a6xx_shader_id">209	<value value="0x9" name="A6XX_TP0_TMO_DATA"/>210	<value value="0xa" name="A6XX_TP0_SMO_DATA"/>211	<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>212	<value value="0x19" name="A6XX_TP1_TMO_DATA"/>213	<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>214	<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>215	<value value="0x29" name="A6XX_SP_INST_DATA"/>216	<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>217	<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>218	<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>219	<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>220	<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>221	<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>222	<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>223	<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>224	<value value="0x32" name="A6XX_SP_UAV_DATA"/>225	<value value="0x33" name="A6XX_SP_INST_TAG"/>226	<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>227	<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>228	<value value="0x36" name="A6XX_SP_SMO_TAG"/>229	<value value="0x37" name="A6XX_SP_STATE_DATA"/>230	<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>231	<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>232	<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>233	<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>234	<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>235	<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>236	<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>237	<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>238	<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>239	<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>240	<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>241	<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>242	<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>243	<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>244	<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>245	<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>246	<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>247	<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>248	<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>249	<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>250	<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>251	<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>252	<value value="0x70" name="A6XX_SP_LB_6_DATA"/>253	<value value="0x71" name="A6XX_SP_LB_7_DATA"/>254	<value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>255</enum>256 257<enum name="a7xx_statetype_id">258	<value value="0" name="A7XX_TP0_NCTX_REG"/>259	<value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>260	<value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>261	<value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>262	<value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>263	<value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>264	<value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>265	<value value="9" name="A7XX_TP0_TMO_DATA"/>266	<value value="10" name="A7XX_TP0_SMO_DATA"/>267	<value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>268	<value value="32" name="A7XX_SP_NCTX_REG"/>269	<value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>270	<value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>271	<value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>272	<value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>273	<value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>274	<value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>275	<value value="39" name="A7XX_SP_INST_DATA"/>276	<value value="40" name="A7XX_SP_INST_DATA_1"/>277	<value value="41" name="A7XX_SP_LB_0_DATA"/>278	<value value="42" name="A7XX_SP_LB_1_DATA"/>279	<value value="43" name="A7XX_SP_LB_2_DATA"/>280	<value value="44" name="A7XX_SP_LB_3_DATA"/>281	<value value="45" name="A7XX_SP_LB_4_DATA"/>282	<value value="46" name="A7XX_SP_LB_5_DATA"/>283	<value value="47" name="A7XX_SP_LB_6_DATA"/>284	<value value="48" name="A7XX_SP_LB_7_DATA"/>285	<value value="49" name="A7XX_SP_CB_RAM"/>286	<value value="50" name="A7XX_SP_LB_13_DATA"/>287	<value value="51" name="A7XX_SP_LB_14_DATA"/>288	<value value="52" name="A7XX_SP_INST_TAG"/>289	<value value="53" name="A7XX_SP_INST_DATA_2"/>290	<value value="54" name="A7XX_SP_TMO_TAG"/>291	<value value="55" name="A7XX_SP_SMO_TAG"/>292	<value value="56" name="A7XX_SP_STATE_DATA"/>293	<value value="57" name="A7XX_SP_HWAVE_RAM"/>294	<value value="58" name="A7XX_SP_L0_INST_BUF"/>295	<value value="59" name="A7XX_SP_LB_8_DATA"/>296	<value value="60" name="A7XX_SP_LB_9_DATA"/>297	<value value="61" name="A7XX_SP_LB_10_DATA"/>298	<value value="62" name="A7XX_SP_LB_11_DATA"/>299	<value value="63" name="A7XX_SP_LB_12_DATA"/>300	<value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>301	<value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>302	<value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>303	<value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>304	<value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>305	<value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>306	<value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>307	<value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>308	<value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>309	<value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>310	<value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>311	<value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>312	<value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>313	<value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>314	<value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>315	<value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>316	<value value="82" name="A7XX_HLSQ_INST_RAM"/>317	<value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>318	<value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>319	<value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/>320	<value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/>321	<value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/>322	<value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>323	<value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>324	<value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/>325	<value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>326	<value value="92" name="A7XX_HLSQ_INST_RAM_1"/>327	<value value="93" name="A7XX_HLSQ_STPROC_META"/>328	<value value="94" name="A7XX_HLSQ_BV_BE_META"/>329	<value value="95" name="A7XX_HLSQ_INST_RAM_2"/>330	<value value="96" name="A7XX_HLSQ_DATAPATH_META"/>331	<value value="97" name="A7XX_HLSQ_FRONTEND_META"/>332	<value value="98" name="A7XX_HLSQ_INDIRECT_META"/>333	<value value="99" name="A7XX_HLSQ_BACKEND_META"/>334</enum>335 336<enum name="a6xx_debugbus_id">337	<value value="0x1" name="A6XX_DBGBUS_CP"/>338	<value value="0x2" name="A6XX_DBGBUS_RBBM"/>339	<value value="0x3" name="A6XX_DBGBUS_VBIF"/>340	<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>341	<value value="0x5" name="A6XX_DBGBUS_UCHE"/>342	<value value="0x6" name="A6XX_DBGBUS_DPM"/>343	<value value="0x7" name="A6XX_DBGBUS_TESS"/>344	<value value="0x8" name="A6XX_DBGBUS_PC"/>345	<value value="0x9" name="A6XX_DBGBUS_VFDP"/>346	<value value="0xa" name="A6XX_DBGBUS_VPC"/>347	<value value="0xb" name="A6XX_DBGBUS_TSE"/>348	<value value="0xc" name="A6XX_DBGBUS_RAS"/>349	<value value="0xd" name="A6XX_DBGBUS_VSC"/>350	<value value="0xe" name="A6XX_DBGBUS_COM"/>351	<value value="0x10" name="A6XX_DBGBUS_LRZ"/>352	<value value="0x11" name="A6XX_DBGBUS_A2D"/>353	<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>354	<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>355	<value value="0x14" name="A6XX_DBGBUS_RBP"/>356	<value value="0x15" name="A6XX_DBGBUS_DCS"/>357	<value value="0x16" name="A6XX_DBGBUS_DBGC"/>358	<value value="0x17" name="A6XX_DBGBUS_CX"/>359	<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>360	<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>361	<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>362	<value value="0x1d" name="A6XX_DBGBUS_GPC"/>363	<value value="0x1e" name="A6XX_DBGBUS_LARC"/>364	<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>365	<value value="0x20" name="A6XX_DBGBUS_RB_0"/>366	<value value="0x21" name="A6XX_DBGBUS_RB_1"/>367	<value value="0x22" name="A6XX_DBGBUS_RB_2"/>368	<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>369	<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>370	<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>371	<value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>372	<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>373	<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>374	<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>375	<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>376	<value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>377	<value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>378	<value value="0x40" name="A6XX_DBGBUS_SP_0"/>379	<value value="0x41" name="A6XX_DBGBUS_SP_1"/>380	<value value="0x42" name="A6XX_DBGBUS_SP_2"/>381	<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>382	<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>383	<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>384	<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>385	<value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>386	<value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>387	<value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>388	<value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>389	<value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>390	<value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>391	<value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>392	<value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>393</enum>394 395<enum name="a7xx_state_location">396	<value value="0" name="A7XX_HLSQ_STATE"/>397	<value value="1" name="A7XX_HLSQ_DP"/>398	<value value="2" name="A7XX_SP_TOP"/>399	<value value="3" name="A7XX_USPTP"/>400	<value value="4" name="A7XX_HLSQ_DP_STR"/>401</enum>402 403<enum name="a7xx_pipe">404	<value value="0" name="A7XX_PIPE_NONE"/>405	<value value="1" name="A7XX_PIPE_BR"/>406	<value value="2" name="A7XX_PIPE_BV"/>407	<value value="3" name="A7XX_PIPE_LPAC"/>408</enum>409 410<enum name="a7xx_cluster">411	<value value="0" name="A7XX_CLUSTER_NONE"/>412	<value value="1" name="A7XX_CLUSTER_FE"/>413	<value value="2" name="A7XX_CLUSTER_SP_VS"/>414	<value value="3" name="A7XX_CLUSTER_PC_VS"/>415	<value value="4" name="A7XX_CLUSTER_GRAS"/>416	<value value="5" name="A7XX_CLUSTER_SP_PS"/>417	<value value="6" name="A7XX_CLUSTER_VPC_PS"/>418	<value value="7" name="A7XX_CLUSTER_PS"/>419</enum>420 421<enum name="a7xx_debugbus_id">422	<value value="1" name="A7XX_DBGBUS_CP_0_0"/>423	<value value="2" name="A7XX_DBGBUS_CP_0_1"/>424	<value value="3" name="A7XX_DBGBUS_RBBM"/>425	<value value="5" name="A7XX_DBGBUS_GBIF_GX"/>426	<value value="6" name="A7XX_DBGBUS_GBIF_CX"/>427	<value value="7" name="A7XX_DBGBUS_HLSQ"/>428	<value value="9" name="A7XX_DBGBUS_UCHE_0"/>429	<value value="10" name="A7XX_DBGBUS_UCHE_1"/>430	<value value="13" name="A7XX_DBGBUS_TESS_BR"/>431	<value value="14" name="A7XX_DBGBUS_TESS_BV"/>432	<value value="17" name="A7XX_DBGBUS_PC_BR"/>433	<value value="18" name="A7XX_DBGBUS_PC_BV"/>434	<value value="21" name="A7XX_DBGBUS_VFDP_BR"/>435	<value value="22" name="A7XX_DBGBUS_VFDP_BV"/>436	<value value="25" name="A7XX_DBGBUS_VPC_BR"/>437	<value value="26" name="A7XX_DBGBUS_VPC_BV"/>438	<value value="29" name="A7XX_DBGBUS_TSE_BR"/>439	<value value="30" name="A7XX_DBGBUS_TSE_BV"/>440	<value value="33" name="A7XX_DBGBUS_RAS_BR"/>441	<value value="34" name="A7XX_DBGBUS_RAS_BV"/>442	<value value="37" name="A7XX_DBGBUS_VSC"/>443	<value value="39" name="A7XX_DBGBUS_COM_0"/>444	<value value="43" name="A7XX_DBGBUS_LRZ_BR"/>445	<value value="44" name="A7XX_DBGBUS_LRZ_BV"/>446	<value value="47" name="A7XX_DBGBUS_UFC_0"/>447	<value value="48" name="A7XX_DBGBUS_UFC_1"/>448	<value value="55" name="A7XX_DBGBUS_GMU_GX"/>449	<value value="59" name="A7XX_DBGBUS_DBGC"/>450	<value value="60" name="A7XX_DBGBUS_CX"/>451	<value value="61" name="A7XX_DBGBUS_GMU_CX"/>452	<value value="62" name="A7XX_DBGBUS_GPC_BR"/>453	<value value="63" name="A7XX_DBGBUS_GPC_BV"/>454	<value value="66" name="A7XX_DBGBUS_LARC"/>455	<value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/>456	<value value="70" name="A7XX_DBGBUS_RB_0"/>457	<value value="71" name="A7XX_DBGBUS_RB_1"/>458	<value value="72" name="A7XX_DBGBUS_RB_2"/>459	<value value="73" name="A7XX_DBGBUS_RB_3"/>460	<value value="74" name="A7XX_DBGBUS_RB_4"/>461	<value value="75" name="A7XX_DBGBUS_RB_5"/>462	<value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/>463	<value value="106" name="A7XX_DBGBUS_CCU_0"/>464	<value value="107" name="A7XX_DBGBUS_CCU_1"/>465	<value value="108" name="A7XX_DBGBUS_CCU_2"/>466	<value value="109" name="A7XX_DBGBUS_CCU_3"/>467	<value value="110" name="A7XX_DBGBUS_CCU_4"/>468	<value value="111" name="A7XX_DBGBUS_CCU_5"/>469	<value value="138" name="A7XX_DBGBUS_VFD_BR_0"/>470	<value value="139" name="A7XX_DBGBUS_VFD_BR_1"/>471	<value value="140" name="A7XX_DBGBUS_VFD_BR_2"/>472	<value value="141" name="A7XX_DBGBUS_VFD_BR_3"/>473	<value value="142" name="A7XX_DBGBUS_VFD_BR_4"/>474	<value value="143" name="A7XX_DBGBUS_VFD_BR_5"/>475	<value value="144" name="A7XX_DBGBUS_VFD_BR_6"/>476	<value value="145" name="A7XX_DBGBUS_VFD_BR_7"/>477	<value value="202" name="A7XX_DBGBUS_VFD_BV_0"/>478	<value value="203" name="A7XX_DBGBUS_VFD_BV_1"/>479	<value value="204" name="A7XX_DBGBUS_VFD_BV_2"/>480	<value value="205" name="A7XX_DBGBUS_VFD_BV_3"/>481	<value value="234" name="A7XX_DBGBUS_USP_0"/>482	<value value="235" name="A7XX_DBGBUS_USP_1"/>483	<value value="236" name="A7XX_DBGBUS_USP_2"/>484	<value value="237" name="A7XX_DBGBUS_USP_3"/>485	<value value="238" name="A7XX_DBGBUS_USP_4"/>486	<value value="239" name="A7XX_DBGBUS_USP_5"/>487	<value value="266" name="A7XX_DBGBUS_TP_0"/>488	<value value="267" name="A7XX_DBGBUS_TP_1"/>489	<value value="268" name="A7XX_DBGBUS_TP_2"/>490	<value value="269" name="A7XX_DBGBUS_TP_3"/>491	<value value="270" name="A7XX_DBGBUS_TP_4"/>492	<value value="271" name="A7XX_DBGBUS_TP_5"/>493	<value value="272" name="A7XX_DBGBUS_TP_6"/>494	<value value="273" name="A7XX_DBGBUS_TP_7"/>495	<value value="274" name="A7XX_DBGBUS_TP_8"/>496	<value value="275" name="A7XX_DBGBUS_TP_9"/>497	<value value="276" name="A7XX_DBGBUS_TP_10"/>498	<value value="277" name="A7XX_DBGBUS_TP_11"/>499	<value value="330" name="A7XX_DBGBUS_USPTP_0"/>500	<value value="331" name="A7XX_DBGBUS_USPTP_1"/>501	<value value="332" name="A7XX_DBGBUS_USPTP_2"/>502	<value value="333" name="A7XX_DBGBUS_USPTP_3"/>503	<value value="334" name="A7XX_DBGBUS_USPTP_4"/>504	<value value="335" name="A7XX_DBGBUS_USPTP_5"/>505	<value value="336" name="A7XX_DBGBUS_USPTP_6"/>506	<value value="337" name="A7XX_DBGBUS_USPTP_7"/>507	<value value="338" name="A7XX_DBGBUS_USPTP_8"/>508	<value value="339" name="A7XX_DBGBUS_USPTP_9"/>509	<value value="340" name="A7XX_DBGBUS_USPTP_10"/>510	<value value="341" name="A7XX_DBGBUS_USPTP_11"/>511	<value value="396" name="A7XX_DBGBUS_CCHE_0"/>512	<value value="397" name="A7XX_DBGBUS_CCHE_1"/>513	<value value="398" name="A7XX_DBGBUS_CCHE_2"/>514	<value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/>515	<value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/>516	<value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/>517	<value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/>518	<value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/>519	<value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/>520	<value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/>521	<value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/>522	<value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/>523	<value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/>524	<value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/>525	<value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/>526	<value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/>527	<value value="447" name="A7XX_DBGBUS_CGC_CORE"/>528</enum>529 530<enum name="a6xx_cp_perfcounter_select">531	<value value="0" name="PERF_CP_ALWAYS_COUNT"/>532	<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>533	<value value="2" name="PERF_CP_BUSY_CYCLES"/>534	<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>535	<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>536	<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>537	<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>538	<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>539	<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>540	<value value="9" name="PERF_CP_MODE_SWITCH"/>541	<value value="10" name="PERF_CP_ZPASS_DONE"/>542	<value value="11" name="PERF_CP_CONTEXT_DONE"/>543	<value value="12" name="PERF_CP_CACHE_FLUSH"/>544	<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>545	<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>546	<value value="15" name="PERF_CP_SQE_IDLE"/>547	<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>548	<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>549	<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>550	<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>551	<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>552	<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>553	<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>554	<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>555	<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>556	<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>557	<value value="26" name="PERF_CP_SQE_T4_EXEC"/>558	<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>559	<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>560	<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>561	<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>562	<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>563	<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>564	<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>565	<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>566	<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>567	<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>568	<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>569	<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>570	<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>571	<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>572	<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>573	<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>574	<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>575	<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>576	<value value="45" name="PERF_CP_PM4_DATA"/>577	<value value="46" name="PERF_CP_PM4_HEADERS"/>578	<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>579	<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>580	<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>581</enum>582 583<enum name="a6xx_rbbm_perfcounter_select">584	<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>585	<value value="1" name="PERF_RBBM_ALWAYS_ON"/>586	<value value="2" name="PERF_RBBM_TSE_BUSY"/>587	<value value="3" name="PERF_RBBM_RAS_BUSY"/>588	<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>589	<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>590	<value value="6" name="PERF_RBBM_STATUS_MASKED"/>591	<value value="7" name="PERF_RBBM_COM_BUSY"/>592	<value value="8" name="PERF_RBBM_DCOM_BUSY"/>593	<value value="9" name="PERF_RBBM_VBIF_BUSY"/>594	<value value="10" name="PERF_RBBM_VSC_BUSY"/>595	<value value="11" name="PERF_RBBM_TESS_BUSY"/>596	<value value="12" name="PERF_RBBM_UCHE_BUSY"/>597	<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>598</enum>599 600<enum name="a6xx_pc_perfcounter_select">601	<value value="0" name="PERF_PC_BUSY_CYCLES"/>602	<value value="1" name="PERF_PC_WORKING_CYCLES"/>603	<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>604	<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>605	<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>606	<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>607	<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>608	<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>609	<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>610	<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>611	<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>612	<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>613	<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>614	<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>615	<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>616	<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>617	<value value="16" name="PERF_PC_INSTANCES"/>618	<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>619	<value value="18" name="PERF_PC_DEAD_PRIM"/>620	<value value="19" name="PERF_PC_LIVE_PRIM"/>621	<value value="20" name="PERF_PC_VERTEX_HITS"/>622	<value value="21" name="PERF_PC_IA_VERTICES"/>623	<value value="22" name="PERF_PC_IA_PRIMITIVES"/>624	<value value="23" name="PERF_PC_GS_PRIMITIVES"/>625	<value value="24" name="PERF_PC_HS_INVOCATIONS"/>626	<value value="25" name="PERF_PC_DS_INVOCATIONS"/>627	<value value="26" name="PERF_PC_VS_INVOCATIONS"/>628	<value value="27" name="PERF_PC_GS_INVOCATIONS"/>629	<value value="28" name="PERF_PC_DS_PRIMITIVES"/>630	<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>631	<value value="30" name="PERF_PC_3D_DRAWCALLS"/>632	<value value="31" name="PERF_PC_2D_DRAWCALLS"/>633	<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>634	<value value="33" name="PERF_TESS_BUSY_CYCLES"/>635	<value value="34" name="PERF_TESS_WORKING_CYCLES"/>636	<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>637	<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>638	<value value="37" name="PERF_PC_TSE_TRANSACTION"/>639	<value value="38" name="PERF_PC_TSE_VERTEX"/>640	<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>641	<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>642	<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>643</enum>644 645<enum name="a6xx_vfd_perfcounter_select">646	<value value="0" name="PERF_VFD_BUSY_CYCLES"/>647	<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>648	<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>649	<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>650	<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>651	<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>652	<value value="6" name="PERF_VFD_RBUFFER_FULL"/>653	<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>654	<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>655	<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>656	<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>657	<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>658	<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>659	<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>660	<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>661	<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>662	<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>663	<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>664	<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>665	<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>666	<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>667	<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>668	<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>669</enum>670 671<enum name="a6xx_hlsq_perfcounter_select">672	<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>673	<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>674	<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>675	<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>676	<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>677	<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>678	<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>679	<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>680	<value value="8" name="PERF_HLSQ_QUADS"/>681	<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>682	<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>683	<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>684	<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>685	<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>686	<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>687	<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>688	<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>689	<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>690	<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>691	<value value="19" name="PERF_HLSQ_PIXELS"/>692	<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>693</enum>694 695<enum name="a6xx_vpc_perfcounter_select">696	<value value="0" name="PERF_VPC_BUSY_CYCLES"/>697	<value value="1" name="PERF_VPC_WORKING_CYCLES"/>698	<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>699	<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>700	<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>701	<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>702	<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>703	<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>704	<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>705	<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>706	<value value="10" name="PERF_VPC_SP_COMPONENTS"/>707	<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>708	<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>709	<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>710	<value value="14" name="PERF_VPC_LM_TRANSACTION"/>711	<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>712	<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>713	<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>714	<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>715	<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>716	<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>717	<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>718	<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>719	<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>720	<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>721	<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>722	<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>723	<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>724</enum>725 726<enum name="a6xx_tse_perfcounter_select">727	<value value="0" name="PERF_TSE_BUSY_CYCLES"/>728	<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>729	<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>730	<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>731	<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>732	<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>733	<value value="6" name="PERF_TSE_INPUT_PRIM"/>734	<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>735	<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>736	<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>737	<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>738	<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>739	<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>740	<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>741	<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>742	<value value="15" name="PERF_TSE_CINVOCATION"/>743	<value value="16" name="PERF_TSE_CPRIMITIVES"/>744	<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>745	<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>746	<value value="19" name="PERF_TSE_CLIP_PLANES"/>747</enum>748 749<enum name="a6xx_ras_perfcounter_select">750	<value value="0" name="PERF_RAS_BUSY_CYCLES"/>751	<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>752	<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>753	<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>754	<value value="4" name="PERF_RAS_SUPER_TILES"/>755	<value value="5" name="PERF_RAS_8X4_TILES"/>756	<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>757	<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>758	<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>759	<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>760	<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>761	<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>762	<value value="12" name="PERF_RAS_BLOCKS"/>763</enum>764 765<enum name="a6xx_uche_perfcounter_select">766	<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>767	<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>768	<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>769	<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>770	<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>771	<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>772	<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>773	<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>774	<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>775	<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>776	<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>777	<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>778	<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>779	<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>780	<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>781	<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>782	<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>783	<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>784	<value value="18" name="PERF_UCHE_EVICTS"/>785	<value value="19" name="PERF_UCHE_BANK_REQ0"/>786	<value value="20" name="PERF_UCHE_BANK_REQ1"/>787	<value value="21" name="PERF_UCHE_BANK_REQ2"/>788	<value value="22" name="PERF_UCHE_BANK_REQ3"/>789	<value value="23" name="PERF_UCHE_BANK_REQ4"/>790	<value value="24" name="PERF_UCHE_BANK_REQ5"/>791	<value value="25" name="PERF_UCHE_BANK_REQ6"/>792	<value value="26" name="PERF_UCHE_BANK_REQ7"/>793	<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>794	<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>795	<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>796	<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>797	<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>798	<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>799	<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>800	<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>801	<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>802	<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>803	<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>804	<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>805	<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>806</enum>807 808<enum name="a6xx_tp_perfcounter_select">809	<value value="0" name="PERF_TP_BUSY_CYCLES"/>810	<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>811	<value value="2" name="PERF_TP_LATENCY_CYCLES"/>812	<value value="3" name="PERF_TP_LATENCY_TRANS"/>813	<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>814	<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>815	<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>816	<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>817	<value value="8" name="PERF_TP_SP_TP_TRANS"/>818	<value value="9" name="PERF_TP_TP_SP_TRANS"/>819	<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>820	<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>821	<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>822	<value value="13" name="PERF_TP_QUADS_RECEIVED"/>823	<value value="14" name="PERF_TP_QUADS_OFFSET"/>824	<value value="15" name="PERF_TP_QUADS_SHADOW"/>825	<value value="16" name="PERF_TP_QUADS_ARRAY"/>826	<value value="17" name="PERF_TP_QUADS_GRADIENT"/>827	<value value="18" name="PERF_TP_QUADS_1D"/>828	<value value="19" name="PERF_TP_QUADS_2D"/>829	<value value="20" name="PERF_TP_QUADS_BUFFER"/>830	<value value="21" name="PERF_TP_QUADS_3D"/>831	<value value="22" name="PERF_TP_QUADS_CUBE"/>832	<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>833	<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>834	<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>835	<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>836	<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>837	<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>838	<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>839	<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>840	<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>841	<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>842	<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>843	<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>844	<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>845	<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>846	<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>847	<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>848	<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>849	<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>850	<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>851	<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>852	<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>853	<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>854	<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>855	<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>856	<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>857	<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>858	<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>859	<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>860	<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>861	<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>862	<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>863	<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>864	<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>865	<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>866</enum>867 868<enum name="a6xx_sp_perfcounter_select">869	<value value="0" name="PERF_SP_BUSY_CYCLES"/>870	<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>871	<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>872	<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>873	<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>874	<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>875	<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>876	<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>877	<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>878	<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>879	<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>880	<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>881	<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>882	<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>883	<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>884	<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>885	<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>886	<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>887	<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>888	<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>889	<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>890	<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>891	<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>892	<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>893	<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>894	<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>895	<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>896	<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>897	<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>898	<value value="29" name="PERF_SP_LM_ATOMICS"/>899	<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>900	<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>901	<value value="32" name="PERF_SP_GM_ATOMICS"/>902	<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>903	<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>904	<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>905	<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>906	<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>907	<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>908	<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>909	<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>910	<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>911	<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>912	<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>913	<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>914	<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>915	<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>916	<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>917	<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>918	<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>919	<value value="50" name="PERF_SP_PIXELS_KILLED"/>920	<value value="51" name="PERF_SP_ICL1_REQUESTS"/>921	<value value="52" name="PERF_SP_ICL1_MISSES"/>922	<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>923	<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>924	<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>925	<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>926	<value value="57" name="PERF_SP_GPR_READ"/>927	<value value="58" name="PERF_SP_GPR_WRITE"/>928	<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>929	<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>930	<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>931	<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>932	<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>933	<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>934	<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>935	<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>936	<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>937	<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>938	<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>939	<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>940	<value value="71" name="PERF_SP_WORKING_EU"/>941	<value value="72" name="PERF_SP_ANY_EU_WORKING"/>942	<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>943	<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>944	<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>945	<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>946	<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>947	<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>948	<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>949	<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>950	<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>951	<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>952	<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>953	<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>954</enum>955 956<enum name="a6xx_rb_perfcounter_select">957	<value value="0" name="PERF_RB_BUSY_CYCLES"/>958	<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>959	<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>960	<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>961	<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>962	<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>963	<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>964	<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>965	<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>966	<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>967	<value value="10" name="PERF_RB_Z_WORKLOAD"/>968	<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>969	<value value="12" name="PERF_RB_Z_READ"/>970	<value value="13" name="PERF_RB_Z_WRITE"/>971	<value value="14" name="PERF_RB_C_READ"/>972	<value value="15" name="PERF_RB_C_WRITE"/>973	<value value="16" name="PERF_RB_TOTAL_PASS"/>974	<value value="17" name="PERF_RB_Z_PASS"/>975	<value value="18" name="PERF_RB_Z_FAIL"/>976	<value value="19" name="PERF_RB_S_FAIL"/>977	<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>978	<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>979	<value value="22" name="PERF_RB_PS_INVOCATIONS"/>980	<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>981	<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>982	<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>983	<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>984	<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>985	<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>986	<value value="29" name="PERF_RB_3D_PIXELS"/>987	<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>988	<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>989	<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>990	<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>991	<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>992	<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>993	<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>994	<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>995	<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>996	<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>997	<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>998	<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>999	<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>1000	<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>1001	<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>1002	<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>1003	<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>1004	<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>1005</enum>1006 1007<enum name="a6xx_vsc_perfcounter_select">1008	<value value="0" name="PERF_VSC_BUSY_CYCLES"/>1009	<value value="1" name="PERF_VSC_WORKING_CYCLES"/>1010	<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>1011	<value value="3" name="PERF_VSC_EOT_NUM"/>1012	<value value="4" name="PERF_VSC_INPUT_TILES"/>1013</enum>1014 1015<enum name="a6xx_ccu_perfcounter_select">1016	<value value="0" name="PERF_CCU_BUSY_CYCLES"/>1017	<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>1018	<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>1019	<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>1020	<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>1021	<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>1022	<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>1023	<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>1024	<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>1025	<value value="9" name="PERF_CCU_GMEM_READ"/>1026	<value value="10" name="PERF_CCU_GMEM_WRITE"/>1027	<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>1028	<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>1029	<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>1030	<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>1031	<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>1032	<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>1033	<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>1034	<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>1035	<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>1036	<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>1037	<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>1038	<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>1039	<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>1040	<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>1041	<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>1042	<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>1043	<value value="27" name="PERF_CCU_2D_RD_REQ"/>1044	<value value="28" name="PERF_CCU_2D_WR_REQ"/>1045</enum>1046 1047<enum name="a6xx_lrz_perfcounter_select">1048	<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>1049	<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>1050	<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>1051	<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>1052	<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>1053	<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>1054	<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>1055	<value value="7" name="PERF_LRZ_LRZ_READ"/>1056	<value value="8" name="PERF_LRZ_LRZ_WRITE"/>1057	<value value="9" name="PERF_LRZ_READ_LATENCY"/>1058	<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>1059	<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>1060	<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>1061	<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>1062	<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>1063	<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>1064	<value value="16" name="PERF_LRZ_TILE_KILLED"/>1065	<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>1066	<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>1067	<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>1068	<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>1069	<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>1070	<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>1071	<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>1072	<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>1073	<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>1074	<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>1075	<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>1076</enum>1077 1078<enum name="a6xx_cmp_perfcounter_select">1079	<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>1080	<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>1081	<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>1082	<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>1083	<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>1084	<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>1085	<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>1086	<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>1087	<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>1088	<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>1089	<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>1090	<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>1091	<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>1092	<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>1093	<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>1094	<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>1095	<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>1096	<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>1097	<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>1098	<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>1099	<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>1100	<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>1101	<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>1102	<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>1103	<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>1104	<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>1105	<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>1106	<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>1107	<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>1108	<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>1109	<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>1110	<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>1111	<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>1112	<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>1113	<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>1114	<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>1115	<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>1116	<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>1117	<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>1118	<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>1119</enum>1120 1121<!--1122Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the1123component type/size, so I think it relates to internal format used for1124blending?  The one exception is that 16b unorm and 32b float use the1125same value... maybe 16b unorm is uncommon enough that it was just easier1126to upconvert to 32b float internally?1127 1128 8b unorm:  10 (sometimes 0, is the high bit part of something else?)112916b unorm:   41130 113132b int:     7113216b int:     61133 8b int:     51134 113532b float:   4113616b float:   31137 -->1138<enum name="a6xx_2d_ifmt">1139	<value value="0x10" name="R2D_UNORM8"/>1140	<value value="0x7"  name="R2D_INT32"/>1141	<value value="0x6"  name="R2D_INT16"/>1142	<value value="0x5"  name="R2D_INT8"/>1143	<value value="0x4"  name="R2D_FLOAT32"/>1144	<value value="0x3"  name="R2D_FLOAT16"/>1145	<value value="0x1"  name="R2D_UNORM8_SRGB"/>1146	<value value="0x0"  name="R2D_RAW"/>1147</enum>1148 1149<enum name="a6xx_ztest_mode">1150	<doc>Allow early z-test and early-lrz (if applicable)</doc>1151	<value value="0x0" name="A6XX_EARLY_Z"/>1152	<doc>Disable early z-test and early-lrz test (if applicable)</doc>1153	<value value="0x1" name="A6XX_LATE_Z"/>1154	<doc>1155		A special mode that allows early-lrz test but disables1156		early-z test.  Which might sound a bit funny, since1157		lrz-test happens before z-test.  But as long as a couple1158		conditions are maintained this allows using lrz-test in1159		cases where fragment shader has kill/discard:1160 1161		1) Disable lrz-write in cases where it is uncertain during1162		   binning pass that a fragment will pass.  Ie.  if frag1163		   shader has-kill, writes-z, or alpha/stencil test is1164		   enabled.  (For correctness, lrz-write must be disabled1165		   when blend is enabled.)  This is analogous to how a1166		   z-prepass works.1167 1168		2) Disable lrz-write and test if a depth-test direction1169		   reversal is detected.  Due to condition (1), the contents1170		   of the lrz buffer are a conservative estimation of the1171		   depth buffer during the draw pass.  Meaning that geometry1172		   that we know for certain will not be visible will not pass1173		   lrz-test.  But geometry which may be (or contributes to1174		   blend) will pass the lrz-test.1175 1176		This allows us to keep early-lrz-test in cases where the frag1177		shader does not write-z (ie. we know the z-value before FS)1178		and does not have side-effects (image/ssbo writes, etc), but1179		does have kill/discard.  Which turns out to be a common1180		enough case that it is useful to keep early-lrz test against1181		the conservative lrz buffer to discard fragments that we1182		know will definitely not be visible.1183	</doc>1184	<value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>1185	<doc>Not a real hw value, used internally by mesa</doc>1186	<value value="0x3" name="A6XX_INVALID_ZTEST"/>1187</enum>1188 1189<enum name="a6xx_tess_spacing">1190	<value value="0x0" name="TESS_EQUAL"/>1191	<value value="0x2" name="TESS_FRACTIONAL_ODD"/>1192	<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>1193</enum>1194<enum name="a6xx_tess_output">1195	<value value="0x0" name="TESS_POINTS"/>1196	<value value="0x1" name="TESS_LINES"/>1197	<value value="0x2" name="TESS_CW_TRIS"/>1198	<value value="0x3" name="TESS_CCW_TRIS"/>1199</enum>1200 1201<enum name="a7xx_cp_perfcounter_select">1202	<value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/>1203	<value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/>1204	<value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/>1205	<value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/>1206	<value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/>1207	<value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>1208	<value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>1209	<value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>1210	<value value="8" name="A7XX_PERF_CP_PREDICATED_DRAWS_KILLED"/>1211	<value value="9" name="A7XX_PERF_CP_MODE_SWITCH"/>1212	<value value="10" name="A7XX_PERF_CP_ZPASS_DONE"/>1213	<value value="11" name="A7XX_PERF_CP_CONTEXT_DONE"/>1214	<value value="12" name="A7XX_PERF_CP_CACHE_FLUSH"/>1215	<value value="13" name="A7XX_PERF_CP_LONG_PREEMPTIONS"/>1216	<value value="14" name="A7XX_PERF_CP_SQE_I_CACHE_STARVE"/>1217	<value value="15" name="A7XX_PERF_CP_SQE_IDLE"/>1218	<value value="16" name="A7XX_PERF_CP_SQE_PM4_STARVE_RB_IB"/>1219	<value value="17" name="A7XX_PERF_CP_SQE_PM4_STARVE_SDS"/>1220	<value value="18" name="A7XX_PERF_CP_SQE_MRB_STARVE"/>1221	<value value="19" name="A7XX_PERF_CP_SQE_RRB_STARVE"/>1222	<value value="20" name="A7XX_PERF_CP_SQE_VSD_STARVE"/>1223	<value value="21" name="A7XX_PERF_CP_VSD_DECODE_STARVE"/>1224	<value value="22" name="A7XX_PERF_CP_SQE_PIPE_OUT_STALL"/>1225	<value value="23" name="A7XX_PERF_CP_SQE_SYNC_STALL"/>1226	<value value="24" name="A7XX_PERF_CP_SQE_PM4_WFI_STALL"/>1227	<value value="25" name="A7XX_PERF_CP_SQE_SYS_WFI_STALL"/>1228	<value value="26" name="A7XX_PERF_CP_SQE_T4_EXEC"/>1229	<value value="27" name="A7XX_PERF_CP_SQE_LOAD_STATE_EXEC"/>1230	<value value="28" name="A7XX_PERF_CP_SQE_SAVE_SDS_STATE"/>1231	<value value="29" name="A7XX_PERF_CP_SQE_DRAW_EXEC"/>1232	<value value="30" name="A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>1233	<value value="31" name="A7XX_PERF_CP_SQE_EXEC_PROFILED"/>1234	<value value="32" name="A7XX_PERF_CP_MEMORY_POOL_EMPTY"/>1235	<value value="33" name="A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/>1236	<value value="34" name="A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>1237	<value value="35" name="A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>1238	<value value="36" name="A7XX_PERF_CP_AHB_STALL_SQE_GMU"/>1239	<value value="37" name="A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/>1240	<value value="38" name="A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/>1241	<value value="39" name="A7XX_PERF_CP_CLUSTER0_EMPTY"/>1242	<value value="40" name="A7XX_PERF_CP_CLUSTER1_EMPTY"/>1243	<value value="41" name="A7XX_PERF_CP_CLUSTER2_EMPTY"/>1244	<value value="42" name="A7XX_PERF_CP_CLUSTER3_EMPTY"/>1245	<value value="43" name="A7XX_PERF_CP_CLUSTER4_EMPTY"/>1246	<value value="44" name="A7XX_PERF_CP_CLUSTER5_EMPTY"/>1247	<value value="45" name="A7XX_PERF_CP_PM4_DATA"/>1248	<value value="46" name="A7XX_PERF_CP_PM4_HEADERS"/>1249	<value value="47" name="A7XX_PERF_CP_VBIF_READ_BEATS"/>1250	<value value="48" name="A7XX_PERF_CP_VBIF_WRITE_BEATS"/>1251	<value value="49" name="A7XX_PERF_CP_SQE_INSTR_COUNTER"/>1252	<value value="50" name="A7XX_PERF_CP_RESERVED_50"/>1253	<value value="51" name="A7XX_PERF_CP_RESERVED_51"/>1254	<value value="52" name="A7XX_PERF_CP_RESERVED_52"/>1255	<value value="53" name="A7XX_PERF_CP_RESERVED_53"/>1256	<value value="54" name="A7XX_PERF_CP_RESERVED_54"/>1257	<value value="55" name="A7XX_PERF_CP_RESERVED_55"/>1258	<value value="56" name="A7XX_PERF_CP_RESERVED_56"/>1259	<value value="57" name="A7XX_PERF_CP_RESERVED_57"/>1260	<value value="58" name="A7XX_PERF_CP_RESERVED_58"/>1261	<value value="59" name="A7XX_PERF_CP_RESERVED_59"/>1262	<value value="60" name="A7XX_PERF_CP_CLUSTER0_FULL"/>1263	<value value="61" name="A7XX_PERF_CP_CLUSTER1_FULL"/>1264	<value value="62" name="A7XX_PERF_CP_CLUSTER2_FULL"/>1265	<value value="63" name="A7XX_PERF_CP_CLUSTER3_FULL"/>1266	<value value="64" name="A7XX_PERF_CP_CLUSTER4_FULL"/>1267	<value value="65" name="A7XX_PERF_CP_CLUSTER5_FULL"/>1268	<value value="66" name="A7XX_PERF_CP_CLUSTER6_FULL"/>1269	<value value="67" name="A7XX_PERF_CP_CLUSTER6_EMPTY"/>1270	<value value="68" name="A7XX_PERF_CP_ICACHE_MISSES"/>1271	<value value="69" name="A7XX_PERF_CP_ICACHE_HITS"/>1272	<value value="70" name="A7XX_PERF_CP_ICACHE_STALL"/>1273	<value value="71" name="A7XX_PERF_CP_DCACHE_MISSES"/>1274	<value value="72" name="A7XX_PERF_CP_DCACHE_HITS"/>1275	<value value="73" name="A7XX_PERF_CP_DCACHE_STALLS"/>1276	<value value="74" name="A7XX_PERF_CP_AQE_SQE_STALL"/>1277	<value value="75" name="A7XX_PERF_CP_SQE_AQE_STARVE"/>1278	<value value="76" name="A7XX_PERF_CP_PREEMPT_LATENCY"/>1279	<value value="77" name="A7XX_PERF_CP_SQE_MD8_STALL_CYCLES"/>1280	<value value="78" name="A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/>1281	<value value="79" name="A7XX_PERF_CP_AQE_NUM_AS_CHUNKS"/>1282	<value value="80" name="A7XX_PERF_CP_AQE_NUM_MS_CHUNKS"/>1283</enum>1284 1285<enum name="a7xx_rbbm_perfcounter_select">1286	<value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/>1287	<value value="1" name="A7XX_PERF_RBBM_ALWAYS_ON"/>1288	<value value="2" name="A7XX_PERF_RBBM_TSE_BUSY"/>1289	<value value="3" name="A7XX_PERF_RBBM_RAS_BUSY"/>1290	<value value="4" name="A7XX_PERF_RBBM_PC_DCALL_BUSY"/>1291	<value value="5" name="A7XX_PERF_RBBM_PC_VSD_BUSY"/>1292	<value value="6" name="A7XX_PERF_RBBM_STATUS_MASKED"/>1293	<value value="7" name="A7XX_PERF_RBBM_COM_BUSY"/>1294	<value value="8" name="A7XX_PERF_RBBM_DCOM_BUSY"/>1295	<value value="9" name="A7XX_PERF_RBBM_VBIF_BUSY"/>1296	<value value="10" name="A7XX_PERF_RBBM_VSC_BUSY"/>1297	<value value="11" name="A7XX_PERF_RBBM_TESS_BUSY"/>1298	<value value="12" name="A7XX_PERF_RBBM_UCHE_BUSY"/>1299	<value value="13" name="A7XX_PERF_RBBM_HLSQ_BUSY"/>1300</enum>1301 1302<enum name="a7xx_pc_perfcounter_select">1303	<value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/>1304	<value value="1" name="A7XX_PERF_PC_WORKING_CYCLES"/>1305	<value value="2" name="A7XX_PERF_PC_STALL_CYCLES_VFD"/>1306	<value value="3" name="A7XX_PERF_PC_RESERVED"/>1307	<value value="4" name="A7XX_PERF_PC_STALL_CYCLES_VPC"/>1308	<value value="5" name="A7XX_PERF_PC_STALL_CYCLES_UCHE"/>1309	<value value="6" name="A7XX_PERF_PC_STALL_CYCLES_TESS"/>1310	<value value="7" name="A7XX_PERF_PC_STALL_CYCLES_VFD_ONLY"/>1311	<value value="8" name="A7XX_PERF_PC_STALL_CYCLES_VPC_ONLY"/>1312	<value value="9" name="A7XX_PERF_PC_PASS1_TF_STALL_CYCLES"/>1313	<value value="10" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_INDEX"/>1314	<value value="11" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>1315	<value value="12" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>1316	<value value="13" name="A7XX_PERF_PC_STARVE_CYCLES_DI"/>1317	<value value="14" name="A7XX_PERF_PC_VIS_STREAMS_LOADED"/>1318	<value value="15" name="A7XX_PERF_PC_INSTANCES"/>1319	<value value="16" name="A7XX_PERF_PC_VPC_PRIMITIVES"/>1320	<value value="17" name="A7XX_PERF_PC_DEAD_PRIM"/>1321	<value value="18" name="A7XX_PERF_PC_LIVE_PRIM"/>1322	<value value="19" name="A7XX_PERF_PC_VERTEX_HITS"/>1323	<value value="20" name="A7XX_PERF_PC_IA_VERTICES"/>1324	<value value="21" name="A7XX_PERF_PC_IA_PRIMITIVES"/>1325	<value value="22" name="A7XX_PERF_PC_RESERVED_22"/>1326	<value value="23" name="A7XX_PERF_PC_HS_INVOCATIONS"/>1327	<value value="24" name="A7XX_PERF_PC_DS_INVOCATIONS"/>1328	<value value="25" name="A7XX_PERF_PC_VS_INVOCATIONS"/>1329	<value value="26" name="A7XX_PERF_PC_GS_INVOCATIONS"/>1330	<value value="27" name="A7XX_PERF_PC_DS_PRIMITIVES"/>1331	<value value="28" name="A7XX_PERF_PC_3D_DRAWCALLS"/>1332	<value value="29" name="A7XX_PERF_PC_2D_DRAWCALLS"/>1333	<value value="30" name="A7XX_PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>1334	<value value="31" name="A7XX_PERF_PC_TESS_BUSY_CYCLES"/>1335	<value value="32" name="A7XX_PERF_PC_TESS_WORKING_CYCLES"/>1336	<value value="33" name="A7XX_PERF_PC_TESS_STALL_CYCLES_PC"/>1337	<value value="34" name="A7XX_PERF_PC_TESS_STARVE_CYCLES_PC"/>1338	<value value="35" name="A7XX_PERF_PC_TESS_SINGLE_PRIM_CYCLES"/>1339	<value value="36" name="A7XX_PERF_PC_TESS_PC_UV_TRANS"/>1340	<value value="37" name="A7XX_PERF_PC_TESS_PC_UV_PATCHES"/>1341	<value value="38" name="A7XX_PERF_PC_TESS_FACTOR_TRANS"/>1342	<value value="39" name="A7XX_PERF_PC_TAG_CHECKED_VERTICES"/>1343	<value value="40" name="A7XX_PERF_PC_MESH_VS_WAVES"/>1344	<value value="41" name="A7XX_PERF_PC_MESH_DRAWS"/>1345	<value value="42" name="A7XX_PERF_PC_MESH_DEAD_DRAWS"/>1346	<value value="43" name="A7XX_PERF_PC_MESH_MVIS_EN_DRAWS"/>1347	<value value="44" name="A7XX_PERF_PC_MESH_DEAD_PRIM"/>1348	<value value="45" name="A7XX_PERF_PC_MESH_LIVE_PRIM"/>1349	<value value="46" name="A7XX_PERF_PC_MESH_PA_EN_PRIM"/>1350	<value value="47" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM"/>1351	<value value="48" name="A7XX_PERF_PC_STARVE_CYCLES_PREDRAW"/>1352	<value value="49" name="A7XX_PERF_PC_STALL_CYCLES_COMPUTE_GFX"/>1353	<value value="50" name="A7XX_PERF_PC_STALL_CYCLES_GFX_COMPUTE"/>1354	<value value="51" name="A7XX_PERF_PC_TESS_PC_MULTI_PATCH_TRANS"/>1355</enum>1356 1357<enum name="a7xx_vfd_perfcounter_select">1358	<value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/>1359	<value value="1" name="A7XX_PERF_VFD_STALL_CYCLES_UCHE"/>1360	<value value="2" name="A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>1361	<value value="3" name="A7XX_PERF_VFD_STALL_CYCLES_SP_INFO"/>1362	<value value="4" name="A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/>1363	<value value="5" name="A7XX_PERF_VFD_STARVE_CYCLES_UCHE"/>1364	<value value="6" name="A7XX_PERF_VFD_RBUFFER_FULL"/>1365	<value value="7" name="A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/>1366	<value value="8" name="A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>1367	<value value="9" name="A7XX_PERF_VFD_NUM_ATTRIBUTES"/>1368	<value value="10" name="A7XX_PERF_VFD_UPPER_SHADER_FIBERS"/>1369	<value value="11" name="A7XX_PERF_VFD_LOWER_SHADER_FIBERS"/>1370	<value value="12" name="A7XX_PERF_VFD_MODE_0_FIBERS"/>1371	<value value="13" name="A7XX_PERF_VFD_MODE_1_FIBERS"/>1372	<value value="14" name="A7XX_PERF_VFD_MODE_2_FIBERS"/>1373	<value value="15" name="A7XX_PERF_VFD_MODE_3_FIBERS"/>1374	<value value="16" name="A7XX_PERF_VFD_MODE_4_FIBERS"/>1375	<value value="17" name="A7XX_PERF_VFD_TOTAL_VERTICES"/>1376	<value value="18" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD"/>1377	<value value="19" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>1378	<value value="20" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/>1379	<value value="21" name="A7XX_PERF_VFDP_STARVE_CYCLES_PC"/>1380	<value value="22" name="A7XX_PERF_VFDP_VS_STAGE_WAVES"/>1381	<value value="23" name="A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/>1382	<value value="24" name="A7XX_PERF_VFD_STALL_CYCLES_CBSYNC"/>1383</enum>1384 1385<enum name="a7xx_hlsq_perfcounter_select">1386	<value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/>1387	<value value="1" name="A7XX_PERF_HLSQ_STALL_CYCLES_UCHE"/>1388	<value value="2" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/>1389	<value value="3" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>1390	<value value="4" name="A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/>1391	<value value="5" name="A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/>1392	<value value="6" name="A7XX_PERF_HLSQ_RESERVED_6"/>1393	<value value="7" name="A7XX_PERF_HLSQ_RESERVED_7"/>1394	<value value="8" name="A7XX_PERF_HLSQ_RESERVED_8"/>1395	<value value="9" name="A7XX_PERF_HLSQ_RESERVED_9"/>1396	<value value="10" name="A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/>1397	<value value="11" name="A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>1398	<value value="12" name="A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>1399	<value value="13" name="A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>1400	<value value="14" name="A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>1401	<value value="15" name="A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>1402	<value value="16" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>1403	<value value="17" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>1404	<value value="18" name="A7XX_PERF_HLSQ_STALL_CYCLES_VPC"/>1405	<value value="19" name="A7XX_PERF_HLSQ_RESERVED_19"/>1406	<value value="20" name="A7XX_PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>1407	<value value="21" name="A7XX_PERF_HLSQ_VSBR_STALL_CYCLES"/>1408	<value value="22" name="A7XX_PERF_HLSQ_FS_STALL_CYCLES"/>1409	<value value="23" name="A7XX_PERF_HLSQ_LPAC_STALL_CYCLES"/>1410	<value value="24" name="A7XX_PERF_HLSQ_BV_STALL_CYCLES"/>1411	<value value="25" name="A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/>1412	<value value="26" name="A7XX_PERF_HLSQ_FS_DEREF_CYCLES"/>1413	<value value="27" name="A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/>1414	<value value="28" name="A7XX_PERF_HLSQ_BV_DEREF_CYCLES"/>1415	<value value="29" name="A7XX_PERF_HLSQ_VSBR_S2W_CYCLES"/>1416	<value value="30" name="A7XX_PERF_HLSQ_FS_S2W_CYCLES"/>1417	<value value="31" name="A7XX_PERF_HLSQ_LPAC_S2W_CYCLES"/>1418	<value value="32" name="A7XX_PERF_HLSQ_BV_S2W_CYCLES"/>1419	<value value="33" name="A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/>1420	<value value="34" name="A7XX_PERF_HLSQ_FS_WAIT_VS_S2W"/>1421	<value value="35" name="A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/>1422	<value value="36" name="A7XX_PERF_HLSQ_BV_WAIT_FS_S2W"/>1423	<value value="37" name="A7XX_PERF_HLSQ_VS_WAIT_CONST_RESOURCE"/>1424	<value value="38" name="A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/>1425	<value value="39" name="A7XX_PERF_HLSQ_FS_STARVING_SP"/>1426	<value value="40" name="A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/>1427	<value value="41" name="A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/>1428	<value value="42" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/>1429	<value value="43" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/>1430	<value value="44" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/>1431	<value value="45" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/>1432	<value value="46" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/>1433	<value value="47" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/>1434	<value value="48" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/>1435	<value value="49" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/>1436	<value value="50" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/>1437	<value value="51" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/>1438	<value value="52" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/>1439	<value value="53" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/>1440	<value value="54" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/>1441	<value value="55" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/>1442	<value value="56" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/>1443	<value value="57" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/>1444</enum>1445 1446<enum name="a7xx_vpc_perfcounter_select">1447	<value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/>1448	<value value="1" name="A7XX_PERF_VPC_WORKING_CYCLES"/>1449	<value value="2" name="A7XX_PERF_VPC_STALL_CYCLES_UCHE"/>1450	<value value="3" name="A7XX_PERF_VPC_STALL_CYCLES_VFD_WACK"/>1451	<value value="4" name="A7XX_PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>1452	<value value="5" name="A7XX_PERF_VPC_RESERVED_5"/>1453	<value value="6" name="A7XX_PERF_VPC_STALL_CYCLES_SP_LM"/>1454	<value value="7" name="A7XX_PERF_VPC_STARVE_CYCLES_SP"/>1455	<value value="8" name="A7XX_PERF_VPC_STARVE_CYCLES_LRZ"/>1456	<value value="9" name="A7XX_PERF_VPC_PC_PRIMITIVES"/>1457	<value value="10" name="A7XX_PERF_VPC_SP_COMPONENTS"/>1458	<value value="11" name="A7XX_PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>1459	<value value="12" name="A7XX_PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>1460	<value value="13" name="A7XX_PERF_VPC_RB_VISIBLE_PRIMITIVES"/>1461	<value value="14" name="A7XX_PERF_VPC_LM_TRANSACTION"/>1462	<value value="15" name="A7XX_PERF_VPC_STREAMOUT_TRANSACTION"/>1463	<value value="16" name="A7XX_PERF_VPC_VS_BUSY_CYCLES"/>1464	<value value="17" name="A7XX_PERF_VPC_PS_BUSY_CYCLES"/>1465	<value value="18" name="A7XX_PERF_VPC_VS_WORKING_CYCLES"/>1466	<value value="19" name="A7XX_PERF_VPC_PS_WORKING_CYCLES"/>1467	<value value="20" name="A7XX_PERF_VPC_STARVE_CYCLES_RB"/>1468	<value value="21" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_POS"/>1469	<value value="22" name="A7XX_PERF_VPC_WIT_FULL_CYCLES"/>1470	<value value="23" name="A7XX_PERF_VPC_VPCRAM_FULL_CYCLES"/>1471	<value value="24" name="A7XX_PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>1472	<value value="25" name="A7XX_PERF_VPC_NUM_VPCRAM_WRITE"/>1473	<value value="26" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_SO"/>1474	<value value="27" name="A7XX_PERF_VPC_NUM_ATTR_REQ_LM"/>1475	<value value="28" name="A7XX_PERF_VPC_STALL_CYCLE_TSE"/>1476	<value value="29" name="A7XX_PERF_VPC_TSE_PRIMITIVES"/>1477	<value value="30" name="A7XX_PERF_VPC_GS_PRIMITIVES"/>1478	<value value="31" name="A7XX_PERF_VPC_TSE_TRANSACTIONS"/>1479	<value value="32" name="A7XX_PERF_VPC_STALL_CYCLES_CCU"/>1480	<value value="33" name="A7XX_PERF_VPC_NUM_WM_HIT"/>1481	<value value="34" name="A7XX_PERF_VPC_STALL_DQ_WACK"/>1482	<value value="35" name="A7XX_PERF_VPC_STALL_CYCLES_CCHE"/>1483	<value value="36" name="A7XX_PERF_VPC_STARVE_CYCLES_CCHE"/>1484	<value value="37" name="A7XX_PERF_VPC_NUM_PA_REQ"/>1485	<value value="38" name="A7XX_PERF_VPC_NUM_LM_REQ_HIT"/>1486	<value value="39" name="A7XX_PERF_VPC_CCHE_REQBUF_FULL"/>1487	<value value="40" name="A7XX_PERF_VPC_STALL_CYCLES_LM_ACK"/>1488	<value value="41" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_FE"/>1489	<value value="42" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_PCVS"/>1490	<value value="43" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_VPCPS"/>1491</enum>1492 1493<enum name="a7xx_tse_perfcounter_select">1494	<value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/>1495	<value value="1" name="A7XX_PERF_TSE_CLIPPING_CYCLES"/>1496	<value value="2" name="A7XX_PERF_TSE_STALL_CYCLES_RAS"/>1497	<value value="3" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>1498	<value value="4" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>1499	<value value="5" name="A7XX_PERF_TSE_STARVE_CYCLES_PC"/>1500	<value value="6" name="A7XX_PERF_TSE_INPUT_PRIM"/>1501	<value value="7" name="A7XX_PERF_TSE_INPUT_NULL_PRIM"/>1502	<value value="8" name="A7XX_PERF_TSE_TRIVAL_REJ_PRIM"/>1503	<value value="9" name="A7XX_PERF_TSE_CLIPPED_PRIM"/>1504	<value value="10" name="A7XX_PERF_TSE_ZERO_AREA_PRIM"/>1505	<value value="11" name="A7XX_PERF_TSE_FACENESS_CULLED_PRIM"/>1506	<value value="12" name="A7XX_PERF_TSE_ZERO_PIXEL_PRIM"/>1507	<value value="13" name="A7XX_PERF_TSE_OUTPUT_NULL_PRIM"/>1508	<value value="14" name="A7XX_PERF_TSE_OUTPUT_VISIBLE_PRIM"/>1509	<value value="15" name="A7XX_PERF_TSE_CINVOCATION"/>1510	<value value="16" name="A7XX_PERF_TSE_CPRIMITIVES"/>1511	<value value="17" name="A7XX_PERF_TSE_2D_INPUT_PRIM"/>1512	<value value="18" name="A7XX_PERF_TSE_2D_ALIVE_CYCLES"/>1513	<value value="19" name="A7XX_PERF_TSE_CLIP_PLANES"/>1514</enum>1515 1516<enum name="a7xx_ras_perfcounter_select">1517	<value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/>1518	<value value="1" name="A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>1519	<value value="2" name="A7XX_PERF_RAS_STALL_CYCLES_LRZ"/>1520	<value value="3" name="A7XX_PERF_RAS_STARVE_CYCLES_TSE"/>1521	<value value="4" name="A7XX_PERF_RAS_SUPER_TILES"/>1522	<value value="5" name="A7XX_PERF_RAS_8X4_TILES"/>1523	<value value="6" name="A7XX_PERF_RAS_MASKGEN_ACTIVE"/>1524	<value value="7" name="A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/>1525	<value value="8" name="A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/>1526	<value value="9" name="A7XX_PERF_RAS_PRIM_KILLED_INVISILBE"/>1527	<value value="10" name="A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>1528	<value value="11" name="A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>1529	<value value="12" name="A7XX_PERF_RAS_BLOCKS"/>1530	<value value="13" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2"/>1531	<value value="14" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2"/>1532	<value value="15" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2"/>1533	<value value="16" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2"/>1534	<value value="17" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2"/>1535	<value value="18" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2"/>1536	<value value="19" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2"/>1537	<value value="20" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2"/>1538	<value value="21" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2"/>1539	<value value="22" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2"/>1540	<value value="23" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2"/>1541	<value value="24" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2"/>1542	<value value="25" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2"/>1543	<value value="26" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2"/>1544	<value value="27" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2"/>1545	<value value="28" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2"/>1546	<value value="29" name="A7XX_PERF_RAS_FALSE_PARTIAL_STILE"/>1547 1548</enum>1549 1550<enum name="a7xx_uche_perfcounter_select">1551	<value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/>1552	<value value="1" name="A7XX_PERF_UCHE_STALL_CYCLES_ARBITER"/>1553	<value value="2" name="A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/>1554	<value value="3" name="A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/>1555	<value value="4" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_TP"/>1556	<value value="5" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/>1557	<value value="6" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>1558	<value value="7" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/>1559	<value value="8" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_SP"/>1560	<value value="9" name="A7XX_PERF_UCHE_READ_REQUESTS_TP"/>1561	<value value="10" name="A7XX_PERF_UCHE_READ_REQUESTS_VFD"/>1562	<value value="11" name="A7XX_PERF_UCHE_READ_REQUESTS_HLSQ"/>1563	<value value="12" name="A7XX_PERF_UCHE_READ_REQUESTS_LRZ"/>1564	<value value="13" name="A7XX_PERF_UCHE_READ_REQUESTS_SP"/>1565	<value value="14" name="A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/>1566	<value value="15" name="A7XX_PERF_UCHE_WRITE_REQUESTS_SP"/>1567	<value value="16" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VPC"/>1568	<value value="17" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VSC"/>1569	<value value="18" name="A7XX_PERF_UCHE_EVICTS"/>1570	<value value="19" name="A7XX_PERF_UCHE_BANK_REQ0"/>1571	<value value="20" name="A7XX_PERF_UCHE_BANK_REQ1"/>1572	<value value="21" name="A7XX_PERF_UCHE_BANK_REQ2"/>1573	<value value="22" name="A7XX_PERF_UCHE_BANK_REQ3"/>1574	<value value="23" name="A7XX_PERF_UCHE_BANK_REQ4"/>1575	<value value="24" name="A7XX_PERF_UCHE_BANK_REQ5"/>1576	<value value="25" name="A7XX_PERF_UCHE_BANK_REQ6"/>1577	<value value="26" name="A7XX_PERF_UCHE_BANK_REQ7"/>1578	<value value="27" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/>1579	<value value="28" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/>1580	<value value="29" name="A7XX_PERF_UCHE_GMEM_READ_BEATS"/>1581	<value value="30" name="A7XX_PERF_UCHE_TPH_REF_FULL"/>1582	<value value="31" name="A7XX_PERF_UCHE_TPH_VICTIM_FULL"/>1583	<value value="32" name="A7XX_PERF_UCHE_TPH_EXT_FULL"/>1584	<value value="33" name="A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/>1585	<value value="34" name="A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/>1586	<value value="35" name="A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/>1587	<value value="36" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_PC"/>1588	<value value="37" name="A7XX_PERF_UCHE_READ_REQUESTS_PC"/>1589	<value value="38" name="A7XX_PERF_UCHE_RAM_READ_REQ"/>1590	<value value="39" name="A7XX_PERF_UCHE_RAM_WRITE_REQ"/>1591	<value value="40" name="A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/>1592	<value value="41" name="A7XX_PERF_UCHE_STALL_CYCLES_DECMP"/>1593	<value value="42" name="A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/>1594	<value value="43" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/>1595	<value value="44" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_NONUBWC"/>1596	<value value="45" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/>1597	<value value="46" name="A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA"/>1598	<value value="47" name="A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA"/>1599	<value value="48" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/>1600	<value value="49" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA"/>1601	<value value="50" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/>1602	<value value="51" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/>1603	<value value="52" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/>1604	<value value="53" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/>1605	<value value="54" name="A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/>1606	<value value="55" name="A7XX_PERF_UCHE_CCHE_DPH_QUEUE_FULL"/>1607	<value value="56" name="A7XX_PERF_UCHE_GMEM_WRITE_BEATS"/>1608	<value value="57" name="A7XX_PERF_UCHE_UBWC_READ_BEATS"/>1609	<value value="58" name="A7XX_PERF_UCHE_UBWC_WRITE_BEATS"/>1610</enum>1611 1612<enum name="a7xx_tp_perfcounter_select">1613	<value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/>1614	<value value="1" name="A7XX_PERF_TP_STALL_CYCLES_UCHE"/>1615	<value value="2" name="A7XX_PERF_TP_LATENCY_CYCLES"/>1616	<value value="3" name="A7XX_PERF_TP_LATENCY_TRANS"/>1617	<value value="4" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/>1618	<value value="5" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/>1619	<value value="6" name="A7XX_PERF_TP_L1_CACHELINE_REQUESTS"/>1620	<value value="7" name="A7XX_PERF_TP_L1_CACHELINE_MISSES"/>1621	<value value="8" name="A7XX_PERF_TP_SP_TP_TRANS"/>1622	<value value="9" name="A7XX_PERF_TP_TP_SP_TRANS"/>1623	<value value="10" name="A7XX_PERF_TP_OUTPUT_PIXELS"/>1624	<value value="11" name="A7XX_PERF_TP_FILTER_WORKLOAD_16BIT"/>1625	<value value="12" name="A7XX_PERF_TP_FILTER_WORKLOAD_32BIT"/>1626	<value value="13" name="A7XX_PERF_TP_QUADS_RECEIVED"/>1627	<value value="14" name="A7XX_PERF_TP_QUADS_OFFSET"/>1628	<value value="15" name="A7XX_PERF_TP_QUADS_SHADOW"/>1629	<value value="16" name="A7XX_PERF_TP_QUADS_ARRAY"/>1630	<value value="17" name="A7XX_PERF_TP_QUADS_GRADIENT"/>1631	<value value="18" name="A7XX_PERF_TP_QUADS_1D"/>1632	<value value="19" name="A7XX_PERF_TP_QUADS_2D"/>1633	<value value="20" name="A7XX_PERF_TP_QUADS_BUFFER"/>1634	<value value="21" name="A7XX_PERF_TP_QUADS_3D"/>1635	<value value="22" name="A7XX_PERF_TP_QUADS_CUBE"/>1636	<value value="23" name="A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/>1637	<value value="24" name="A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/>1638	<value value="25" name="A7XX_PERF_TP_OUTPUT_PIXELS_POINT"/>1639	<value value="26" name="A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/>1640	<value value="27" name="A7XX_PERF_TP_OUTPUT_PIXELS_MIP"/>1641	<value value="28" name="A7XX_PERF_TP_OUTPUT_PIXELS_ANISO"/>1642	<value value="29" name="A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>1643	<value value="30" name="A7XX_PERF_TP_FLAG_CACHE_REQUESTS"/>1644	<value value="31" name="A7XX_PERF_TP_FLAG_CACHE_MISSES"/>1645	<value value="32" name="A7XX_PERF_TP_L1_5_L2_REQUESTS"/>1646	<value value="33" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS"/>1647	<value value="34" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/>1648	<value value="35" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>1649	<value value="36" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>1650	<value value="37" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>1651	<value value="38" name="A7XX_PERF_TP_TPA2TPC_TRANS"/>1652	<value value="39" name="A7XX_PERF_TP_L1_MISSES_ASTC_1TILE"/>1653	<value value="40" name="A7XX_PERF_TP_L1_MISSES_ASTC_2TILE"/>1654	<value value="41" name="A7XX_PERF_TP_L1_MISSES_ASTC_4TILE"/>1655	<value value="42" name="A7XX_PERF_TP_L1_5_COMPRESS_REQS"/>1656	<value value="43" name="A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/>1657	<value value="44" name="A7XX_PERF_TP_L1_BANK_CONFLICT"/>1658	<value value="45" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>1659	<value value="46" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/>1660	<value value="47" name="A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>1661	<value value="48" name="A7XX_PERF_TP_FRONTEND_WORKING_CYCLES"/>1662	<value value="49" name="A7XX_PERF_TP_L1_TAG_WORKING_CYCLES"/>1663	<value value="50" name="A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>1664	<value value="51" name="A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>1665	<value value="52" name="A7XX_PERF_TP_BACKEND_WORKING_CYCLES"/>1666	<value value="53" name="A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>1667	<value value="54" name="A7XX_PERF_TP_STARVE_CYCLES_SP"/>1668	<value value="55" name="A7XX_PERF_TP_STARVE_CYCLES_UCHE"/>1669	<value value="56" name="A7XX_PERF_TP_STALL_CYCLES_UFC"/>1670	<value value="57" name="A7XX_PERF_TP_FORMAT_DECOMP"/>1671	<value value="58" name="A7XX_PERF_TP_FILTER_POINT_FP16"/>1672	<value value="59" name="A7XX_PERF_TP_FILTER_POINT_FP32"/>1673	<value value="60" name="A7XX_PERF_TP_LATENCY_FIFO_FULL"/>1674	<value value="61" name="A7XX_PERF_TP_RESERVED_61"/>1675	<value value="62" name="A7XX_PERF_TP_RESERVED_62"/>1676	<value value="63" name="A7XX_PERF_TP_RESERVED_63"/>1677	<value value="64" name="A7XX_PERF_TP_RESERVED_64"/>1678	<value value="65" name="A7XX_PERF_TP_RESERVED_65"/>1679	<value value="66" name="A7XX_PERF_TP_RESERVED_66"/>1680	<value value="67" name="A7XX_PERF_TP_RESERVED_67"/>1681	<value value="68" name="A7XX_PERF_TP_RESERVED_68"/>1682	<value value="69" name="A7XX_PERF_TP_RESERVED_69"/>1683	<value value="70" name="A7XX_PERF_TP_RESERVED_70"/>1684	<value value="71" name="A7XX_PERF_TP_RESERVED_71"/>1685	<value value="72" name="A7XX_PERF_TP_RESERVED_72"/>1686	<value value="73" name="A7XX_PERF_TP_RESERVED_73"/>1687	<value value="74" name="A7XX_PERF_TP_RESERVED_74"/>1688	<value value="75" name="A7XX_PERF_TP_RESERVED_75"/>1689	<value value="76" name="A7XX_PERF_TP_RESERVED_76"/>1690	<value value="77" name="A7XX_PERF_TP_RESERVED_77"/>1691	<value value="78" name="A7XX_PERF_TP_RESERVED_78"/>1692	<value value="79" name="A7XX_PERF_TP_RESERVED_79"/>1693	<value value="80" name="A7XX_PERF_TP_RESERVED_80"/>1694	<value value="81" name="A7XX_PERF_TP_RESERVED_81"/>1695	<value value="82" name="A7XX_PERF_TP_RESERVED_82"/>1696	<value value="83" name="A7XX_PERF_TP_RESERVED_83"/>1697	<value value="84" name="A7XX_PERF_TP_RESERVED_84"/>1698	<value value="85" name="A7XX_PERF_TP_RESERVED_85"/>1699	<value value="86" name="A7XX_PERF_TP_RESERVED_86"/>1700	<value value="87" name="A7XX_PERF_TP_RESERVED_87"/>1701	<value value="88" name="A7XX_PERF_TP_RESERVED_88"/>1702	<value value="89" name="A7XX_PERF_TP_RESERVED_89"/>1703	<value value="90" name="A7XX_PERF_TP_RESERVED_90"/>1704	<value value="91" name="A7XX_PERF_TP_RESERVED_91"/>1705	<value value="92" name="A7XX_PERF_TP_RESERVED_92"/>1706	<value value="93" name="A7XX_PERF_TP_RESERVED_93"/>1707	<value value="94" name="A7XX_PERF_TP_RESERVED_94"/>1708	<value value="95" name="A7XX_PERF_TP_RESERVED_95"/>1709	<value value="96" name="A7XX_PERF_TP_RESERVED_96"/>1710	<value value="97" name="A7XX_PERF_TP_RESERVED_97"/>1711	<value value="98" name="A7XX_PERF_TP_RESERVED_98"/>1712	<value value="99" name="A7XX_PERF_TP_RESERVED_99"/>1713	<value value="100" name="A7XX_PERF_TP_RESERVED_100"/>1714	<value value="101" name="A7XX_PERF_TP_RESERVED_101"/>1715	<value value="102" name="A7XX_PERF_TP_RESERVED_102"/>1716	<value value="103" name="A7XX_PERF_TP_RESERVED_103"/>1717	<value value="104" name="A7XX_PERF_TP_RESERVED_104"/>1718	<value value="105" name="A7XX_PERF_TP_RESERVED_105"/>1719	<value value="106" name="A7XX_PERF_TP_RESERVED_106"/>1720	<value value="107" name="A7XX_PERF_TP_RESERVED_107"/>1721	<value value="108" name="A7XX_PERF_TP_RESERVED_108"/>1722	<value value="109" name="A7XX_PERF_TP_RESERVED_109"/>1723	<value value="110" name="A7XX_PERF_TP_RESERVED_110"/>1724	<value value="111" name="A7XX_PERF_TP_RESERVED_111"/>1725	<value value="112" name="A7XX_PERF_TP_RESERVED_112"/>1726	<value value="113" name="A7XX_PERF_TP_RESERVED_113"/>1727	<value value="114" name="A7XX_PERF_TP_RESERVED_114"/>1728	<value value="115" name="A7XX_PERF_TP_RESERVED_115"/>1729	<value value="116" name="A7XX_PERF_TP_RESERVED_116"/>1730	<value value="117" name="A7XX_PERF_TP_RESERVED_117"/>1731	<value value="118" name="A7XX_PERF_TP_RESERVED_118"/>1732	<value value="119" name="A7XX_PERF_TP_RESERVED_119"/>1733	<value value="120" name="A7XX_PERF_TP_RESERVED_120"/>1734	<value value="121" name="A7XX_PERF_TP_RESERVED_121"/>1735	<value value="122" name="A7XX_PERF_TP_RESERVED_122"/>1736	<value value="123" name="A7XX_PERF_TP_RESERVED_123"/>1737	<value value="124" name="A7XX_PERF_TP_RESERVED_124"/>1738	<value value="125" name="A7XX_PERF_TP_RESERVED_125"/>1739	<value value="126" name="A7XX_PERF_TP_RESERVED_126"/>1740	<value value="127" name="A7XX_PERF_TP_RESERVED_127"/>1741	<value value="128" name="A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/>1742	<value value="129" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/>1743	<value value="130" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/>1744	<value value="131" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/>1745	<value value="132" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/>1746</enum>1747 1748<enum name="a7xx_sp_perfcounter_select">1749	<value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/>1750	<value value="1" name="A7XX_PERF_SP_ALU_WORKING_CYCLES"/>1751	<value value="2" name="A7XX_PERF_SP_EFU_WORKING_CYCLES"/>1752	<value value="3" name="A7XX_PERF_SP_STALL_CYCLES_VPC"/>1753	<value value="4" name="A7XX_PERF_SP_STALL_CYCLES_TP"/>1754	<value value="5" name="A7XX_PERF_SP_STALL_CYCLES_UCHE"/>1755	<value value="6" name="A7XX_PERF_SP_STALL_CYCLES_RB"/>1756	<value value="7" name="A7XX_PERF_SP_NON_EXECUTION_CYCLES"/>1757	<value value="8" name="A7XX_PERF_SP_WAVE_CONTEXTS"/>1758	<value value="9" name="A7XX_PERF_SP_WAVE_CONTEXT_CYCLES"/>1759	<value value="10" name="A7XX_PERF_SP_STAGE_WAVE_CYCLES"/>1760	<value value="11" name="A7XX_PERF_SP_STAGE_WAVE_SAMPLES"/>1761	<value value="12" name="A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/>1762	<value value="13" name="A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/>1763	<value value="14" name="A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/>1764	<value value="15" name="A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/>1765	<value value="16" name="A7XX_PERF_SP_WAVE_CTRL_CYCLES"/>1766	<value value="17" name="A7XX_PERF_SP_WAVE_LOAD_CYCLES"/>1767	<value value="18" name="A7XX_PERF_SP_WAVE_EMIT_CYCLES"/>1768	<value value="19" name="A7XX_PERF_SP_WAVE_NOP_CYCLES"/>1769	<value value="20" name="A7XX_PERF_SP_WAVE_WAIT_CYCLES"/>1770	<value value="21" name="A7XX_PERF_SP_WAVE_FETCH_CYCLES"/>1771	<value value="22" name="A7XX_PERF_SP_WAVE_IDLE_CYCLES"/>1772	<value value="23" name="A7XX_PERF_SP_WAVE_END_CYCLES"/>1773	<value value="24" name="A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/>1774	<value value="25" name="A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>1775	<value value="26" name="A7XX_PERF_SP_WAVE_JOIN_CYCLES"/>1776	<value value="27" name="A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/>1777	<value value="28" name="A7XX_PERF_SP_LM_STORE_INSTRUCTIONS"/>1778	<value value="29" name="A7XX_PERF_SP_LM_ATOMICS"/>1779	<value value="30" name="A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/>1780	<value value="31" name="A7XX_PERF_SP_GM_STORE_INSTRUCTIONS"/>1781	<value value="32" name="A7XX_PERF_SP_GM_ATOMICS"/>1782	<value value="33" name="A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>1783	<value value="34" name="A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>1784	<value value="35" name="A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>1785	<value value="36" name="A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>1786	<value value="37" name="A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>1787	<value value="38" name="A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>1788	<value value="39" name="A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>1789	<value value="40" name="A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>1790	<value value="41" name="A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>1791	<value value="42" name="A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>1792	<value value="43" name="A7XX_PERF_SP_VS_INSTRUCTIONS"/>1793	<value value="44" name="A7XX_PERF_SP_FS_INSTRUCTIONS"/>1794	<value value="45" name="A7XX_PERF_SP_ADDR_LOCK_COUNT"/>1795	<value value="46" name="A7XX_PERF_SP_UCHE_READ_TRANS"/>1796	<value value="47" name="A7XX_PERF_SP_UCHE_WRITE_TRANS"/>1797	<value value="48" name="A7XX_PERF_SP_EXPORT_VPC_TRANS"/>1798	<value value="49" name="A7XX_PERF_SP_EXPORT_RB_TRANS"/>1799	<value value="50" name="A7XX_PERF_SP_PIXELS_KILLED"/>1800	<value value="51" name="A7XX_PERF_SP_ICL1_REQUESTS"/>1801	<value value="52" name="A7XX_PERF_SP_ICL1_MISSES"/>1802	<value value="53" name="A7XX_PERF_SP_HS_INSTRUCTIONS"/>1803	<value value="54" name="A7XX_PERF_SP_DS_INSTRUCTIONS"/>1804	<value value="55" name="A7XX_PERF_SP_GS_INSTRUCTIONS"/>1805	<value value="56" name="A7XX_PERF_SP_CS_INSTRUCTIONS"/>1806	<value value="57" name="A7XX_PERF_SP_GPR_READ"/>1807	<value value="58" name="A7XX_PERF_SP_GPR_WRITE"/>1808	<value value="59" name="A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>1809	<value value="60" name="A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>1810	<value value="61" name="A7XX_PERF_SP_LM_BANK_CONFLICTS"/>1811	<value value="62" name="A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>1812	<value value="63" name="A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>1813	<value value="64" name="A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>1814	<value value="65" name="A7XX_PERF_SP_LM_WORKING_CYCLES"/>1815	<value value="66" name="A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/>1816	<value value="67" name="A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/>1817	<value value="68" name="A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>1818	<value value="69" name="A7XX_PERF_SP_STARVE_CYCLES_HLSQ"/>1819	<value value="70" name="A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/>1820	<value value="71" name="A7XX_PERF_SP_WORKING_EU"/>1821	<value value="72" name="A7XX_PERF_SP_ANY_EU_WORKING"/>1822	<value value="73" name="A7XX_PERF_SP_WORKING_EU_FS_STAGE"/>1823	<value value="74" name="A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/>1824	<value value="75" name="A7XX_PERF_SP_WORKING_EU_VS_STAGE"/>1825	<value value="76" name="A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/>1826	<value value="77" name="A7XX_PERF_SP_WORKING_EU_CS_STAGE"/>1827	<value value="78" name="A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/>1828	<value value="79" name="A7XX_PERF_SP_GPR_READ_PREFETCH"/>1829	<value value="80" name="A7XX_PERF_SP_GPR_READ_CONFLICT"/>1830	<value value="81" name="A7XX_PERF_SP_GPR_WRITE_CONFLICT"/>1831	<value value="82" name="A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/>1832	<value value="83" name="A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>1833	<value value="84" name="A7XX_PERF_SP_EXECUTABLE_WAVES"/>1834	<value value="85" name="A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/>1835	<value value="86" name="A7XX_PERF_SP_WORKING_EU_LPAC"/>1836	<value value="87" name="A7XX_PERF_SP_BYPASS_BUSY_CYCLES"/>1837	<value value="88" name="A7XX_PERF_SP_ANY_EU_WORKING_LPAC"/>1838	<value value="89" name="A7XX_PERF_SP_WAVE_ALU_CYCLES"/>1839	<value value="90" name="A7XX_PERF_SP_WAVE_EFU_CYCLES"/>1840	<value value="91" name="A7XX_PERF_SP_WAVE_INT_CYCLES"/>1841	<value value="92" name="A7XX_PERF_SP_WAVE_CSP_CYCLES"/>1842	<value value="93" name="A7XX_PERF_SP_EWAVE_CONTEXTS"/>1843	<value value="94" name="A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/>1844	<value value="95" name="A7XX_PERF_SP_LPAC_BUSY_CYCLES"/>1845	<value value="96" name="A7XX_PERF_SP_LPAC_INSTRUCTIONS"/>1846	<value value="97" name="A7XX_PERF_SP_FS_STAGE_1X_WAVES"/>1847	<value value="98" name="A7XX_PERF_SP_FS_STAGE_2X_WAVES"/>1848	<value value="99" name="A7XX_PERF_SP_QUADS"/>1849	<value value="100" name="A7XX_PERF_SP_CS_INVOCATIONS"/>1850	<value value="101" name="A7XX_PERF_SP_PIXELS"/>1851	<value value="102" name="A7XX_PERF_SP_LPAC_DRAWCALLS"/>1852	<value value="103" name="A7XX_PERF_SP_PI_WORKING_CYCLES"/>1853	<value value="104" name="A7XX_PERF_SP_WAVE_INPUT_CYCLES"/>1854	<value value="105" name="A7XX_PERF_SP_WAVE_OUTPUT_CYCLES"/>1855	<value value="106" name="A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/>1856	<value value="107" name="A7XX_PERF_SP_WAVE_HWAVE_SYNC"/>1857	<value value="108" name="A7XX_PERF_SP_OUTPUT_3D_PIXELS"/>1858	<value value="109" name="A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/>1859	<value value="110" name="A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/>1860	<value value="111" name="A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/>1861	<value value="112" name="A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/>1862	<value value="113" name="A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/>1863	<value value="114" name="A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/>1864	<value value="115" name="A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/>1865	<value value="116" name="A7XX_PERF_SP_ALU_GPR_READ_CYCLES"/>1866	<value value="117" name="A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/>1867	<value value="118" name="A7XX_PERF_SP_LM_FULL_CYCLES"/>1868	<value value="119" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/>1869	<value value="120" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/>1870	<value value="121" name="A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/>1871	<value value="122" name="A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/>1872	<value value="123" name="A7XX_PERF_SP_RBRT_KICKOFF_FIBERS"/>1873	<value value="124" name="A7XX_PERF_SP_RBRT_KICKOFF_DQUADS"/>1874	<value value="125" name="A7XX_PERF_SP_RTU_BUSY_CYCLES"/>1875	<value value="126" name="A7XX_PERF_SP_RTU_L0_HITS"/>1876	<value value="127" name="A7XX_PERF_SP_RTU_L0_MISSES"/>1877	<value value="128" name="A7XX_PERF_SP_RTU_L0_HIT_ON_MISS"/>1878	<value value="129" name="A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/>1879	<value value="130" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/>1880	<value value="131" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/>1881	<value value="132" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/>1882	<value value="133" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/>1883	<value value="134" name="A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/>1884	<value value="135" name="A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/>1885	<value value="136" name="A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/>1886	<value value="137" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/>1887	<value value="138" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/>1888	<value value="139" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/>1889	<value value="140" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/>1890	<value value="141" name="A7XX_PERF_SP_STCHE_MISS_INC_VS"/>1891	<value value="142" name="A7XX_PERF_SP_STCHE_MISS_INC_FS"/>1892	<value value="143" name="A7XX_PERF_SP_STCHE_MISS_INC_BV"/>1893	<value value="144" name="A7XX_PERF_SP_STCHE_MISS_INC_LPAC"/>1894	<value value="145" name="A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/>1895	<value value="146" name="A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/>1896	<value value="147" name="A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/>1897	<value value="148" name="A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/>1898	<value value="149" name="A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/>1899	<value value="150" name="A7XX_PERF_SP_SCH_STALL_CYCLES_RTU"/>1900</enum>1901 1902<enum name="a7xx_rb_perfcounter_select">1903	<value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/>1904	<value value="1" name="A7XX_PERF_RB_STALL_CYCLES_HLSQ"/>1905	<value value="2" name="A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/>1906	<value value="3" name="A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/>1907	<value value="4" name="A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/>1908	<value value="5" name="A7XX_PERF_RB_STARVE_CYCLES_SP"/>1909	<value value="6" name="A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/>1910	<value value="7" name="A7XX_PERF_RB_STARVE_CYCLES_CCU"/>1911	<value value="8" name="A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/>1912	<value value="9" name="A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/>1913	<value value="10" name="A7XX_PERF_RB_Z_WORKLOAD"/>1914	<value value="11" name="A7XX_PERF_RB_HLSQ_ACTIVE"/>1915	<value value="12" name="A7XX_PERF_RB_Z_READ"/>1916	<value value="13" name="A7XX_PERF_RB_Z_WRITE"/>1917	<value value="14" name="A7XX_PERF_RB_C_READ"/>1918	<value value="15" name="A7XX_PERF_RB_C_WRITE"/>1919	<value value="16" name="A7XX_PERF_RB_TOTAL_PASS"/>1920	<value value="17" name="A7XX_PERF_RB_Z_PASS"/>1921	<value value="18" name="A7XX_PERF_RB_Z_FAIL"/>1922	<value value="19" name="A7XX_PERF_RB_S_FAIL"/>1923	<value value="20" name="A7XX_PERF_RB_BLENDED_FXP_COMPONENTS"/>1924	<value value="21" name="A7XX_PERF_RB_BLENDED_FP16_COMPONENTS"/>1925	<value value="22" name="A7XX_PERF_RB_PS_INVOCATIONS"/>1926	<value value="23" name="A7XX_PERF_RB_2D_ALIVE_CYCLES"/>1927	<value value="24" name="A7XX_PERF_RB_2D_STALL_CYCLES_A2D"/>1928	<value value="25" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SRC"/>1929	<value value="26" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SP"/>1930	<value value="27" name="A7XX_PERF_RB_2D_STARVE_CYCLES_DST"/>1931	<value value="28" name="A7XX_PERF_RB_2D_VALID_PIXELS"/>1932	<value value="29" name="A7XX_PERF_RB_3D_PIXELS"/>1933	<value value="30" name="A7XX_PERF_RB_BLENDER_WORKING_CYCLES"/>1934	<value value="31" name="A7XX_PERF_RB_ZPROC_WORKING_CYCLES"/>1935	<value value="32" name="A7XX_PERF_RB_CPROC_WORKING_CYCLES"/>1936	<value value="33" name="A7XX_PERF_RB_SAMPLER_WORKING_CYCLES"/>1937	<value value="34" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>1938	<value value="35" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>1939	<value value="36" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>1940	<value value="37" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>1941	<value value="38" name="A7XX_PERF_RB_STALL_CYCLES_VPC"/>1942	<value value="39" name="A7XX_PERF_RB_2D_INPUT_TRANS"/>1943	<value value="40" name="A7XX_PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>1944	<value value="41" name="A7XX_PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>1945	<value value="42" name="A7XX_PERF_RB_BLENDED_FP32_COMPONENTS"/>1946	<value value="43" name="A7XX_PERF_RB_COLOR_PIX_TILES"/>1947	<value value="44" name="A7XX_PERF_RB_STALL_CYCLES_CCU"/>1948	<value value="45" name="A7XX_PERF_RB_EARLY_Z_ARB3_GRANT"/>1949	<value value="46" name="A7XX_PERF_RB_LATE_Z_ARB3_GRANT"/>1950	<value value="47" name="A7XX_PERF_RB_EARLY_Z_SKIP_GRANT"/>1951	<value value="48" name="A7XX_PERF_RB_VRS_1x1_QUADS"/>1952	<value value="49" name="A7XX_PERF_RB_VRS_2x1_QUADS"/>1953	<value value="50" name="A7XX_PERF_RB_VRS_1x2_QUADS"/>1954	<value value="51" name="A7XX_PERF_RB_VRS_2x2_QUADS"/>1955	<value value="52" name="A7XX_PERF_RB_VRS_4x2_QUADS"/>1956	<value value="53" name="A7XX_PERF_RB_VRS_4x4_QUADS"/>1957</enum>1958 1959<enum name="a7xx_vsc_perfcounter_select">1960	<value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/>1961	<value value="1" name="A7XX_PERF_VSC_WORKING_CYCLES"/>1962	<value value="2" name="A7XX_PERF_VSC_STALL_CYCLES_UCHE"/>1963	<value value="3" name="A7XX_PERF_VSC_EOT_NUM"/>1964	<value value="4" name="A7XX_PERF_VSC_INPUT_TILES"/>1965</enum>1966 1967<enum name="a7xx_ccu_perfcounter_select">1968	<value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/>1969	<value value="1" name="A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>1970	<value value="2" name="A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>1971	<value value="3" name="A7XX_PERF_CCU_DEPTH_BLOCKS"/>1972	<value value="4" name="A7XX_PERF_CCU_COLOR_BLOCKS"/>1973	<value value="5" name="A7XX_PERF_CCU_DEPTH_BLOCK_HIT"/>1974	<value value="6" name="A7XX_PERF_CCU_COLOR_BLOCK_HIT"/>1975	<value value="7" name="A7XX_PERF_CCU_PARTIAL_BLOCK_READ"/>1976	<value value="8" name="A7XX_PERF_CCU_GMEM_READ"/>1977	<value value="9" name="A7XX_PERF_CCU_GMEM_WRITE"/>1978	<value value="10" name="A7XX_PERF_CCU_2D_RD_REQ"/>1979	<value value="11" name="A7XX_PERF_CCU_2D_WR_REQ"/>1980	<value value="12" name="A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/>1981	<value value="13" name="A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/>1982	<value value="14" name="A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/>1983	<value value="15" name="A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/>1984	<value value="16" name="A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/>1985	<value value="17" name="A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/>1986	<value value="18" name="A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/>1987	<value value="19" name="A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/>1988	<value value="20" name="A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/>1989	<value value="21" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA"/>1990	<value value="22" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/>1991</enum>1992 1993<enum name="a7xx_lrz_perfcounter_select">1994	<value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/>1995	<value value="1" name="A7XX_PERF_LRZ_STARVE_CYCLES_RAS"/>1996	<value value="2" name="A7XX_PERF_LRZ_STALL_CYCLES_RB"/>1997	<value value="3" name="A7XX_PERF_LRZ_STALL_CYCLES_VSC"/>1998	<value value="4" name="A7XX_PERF_LRZ_STALL_CYCLES_VPC"/>1999	<value value="5" name="A7XX_PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>2000	<value value="6" name="A7XX_PERF_LRZ_STALL_CYCLES_UCHE"/>2001	<value value="7" name="A7XX_PERF_LRZ_LRZ_READ"/>2002	<value value="8" name="A7XX_PERF_LRZ_LRZ_WRITE"/>2003	<value value="9" name="A7XX_PERF_LRZ_READ_LATENCY"/>2004	<value value="10" name="A7XX_PERF_LRZ_MERGE_CACHE_UPDATING"/>2005	<value value="11" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>2006	<value value="12" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/>2007	<value value="13" name="A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>2008	<value value="14" name="A7XX_PERF_LRZ_FULL_8X8_TILES"/>2009	<value value="15" name="A7XX_PERF_LRZ_PARTIAL_8X8_TILES"/>2010	<value value="16" name="A7XX_PERF_LRZ_TILE_KILLED"/>2011	<value value="17" name="A7XX_PERF_LRZ_TOTAL_PIXEL"/>2012	<value value="18" name="A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>2013	<value value="19" name="A7XX_PERF_LRZ_FEEDBACK_ACCEPT"/>2014	<value value="20" name="A7XX_PERF_LRZ_FEEDBACK_DISCARD"/>2015	<value value="21" name="A7XX_PERF_LRZ_FEEDBACK_STALL"/>2016	<value value="22" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>2017	<value value="23" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>2018	<value value="24" name="A7XX_PERF_LRZ_RAS_MASK_TRANS"/>2019	<value value="25" name="A7XX_PERF_LRZ_STALL_CYCLES_MVC"/>2020	<value value="26" name="A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/>2021	<value value="27" name="A7XX_PERF_LRZ_TILE_KILLED_BY_Z"/>2022</enum>2023 2024<enum name="a7xx_cmp_perfcounter_select">2025	<value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/>2026	<value value="1" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>2027	<value value="2" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>2028	<value value="3" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>2029	<value value="4" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>2030	<value value="5" name="A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/>2031	<value value="6" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>2032	<value value="7" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA"/>2033	<value value="8" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/>2034	<value value="9" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>2035	<value value="10" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>2036	<value value="11" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>2037	<value value="12" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>2038	<value value="13" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>2039	<value value="14" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>2040	<value value="15" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>2041	<value value="16" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>2042	<value value="17" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>2043	<value value="18" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>2044	<value value="19" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>2045	<value value="20" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>2046	<value value="21" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>2047	<value value="22" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>2048	<value value="23" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>2049	<value value="24" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>2050	<value value="25" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>2051	<value value="26" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>2052	<value value="27" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>2053	<value value="28" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>2054	<value value="29" name="A7XX_PERF_CMPDECMP_RESOLVE_EVENTS"/>2055	<value value="30" name="A7XX_PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS"/>2056	<value value="31" name="A7XX_PERF_CMPDECMP_DROPPED_CLEAR_EVENTS"/>2057	<value value="32" name="A7XX_PERF_CMPDECMP_ST_BLOCKS_CONCURRENT"/>2058	<value value="33" name="A7XX_PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT"/>2059	<value value="34" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/>2060	<value value="35" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/>2061	<value value="36" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/>2062	<value value="37" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/>2063	<value value="38" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/>2064	<value value="39" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/>2065	<value value="40" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/>2066	<value value="41" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/>2067	<value value="42" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/>2068	<value value="43" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/>2069	<value value="44" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/>2070	<value value="45" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/>2071	<value value="46" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/>2072	<value value="47" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/>2073	<value value="48" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/>2074	<value value="49" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/>2075</enum>2076 2077<enum name="a7xx_gbif_perfcounter_select">2078	<value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/>2079	<value value="1" name="A7XX_PERF_GBIF_RESERVED_1"/>2080	<value value="2" name="A7XX_PERF_GBIF_RESERVED_2"/>2081	<value value="3" name="A7XX_PERF_GBIF_RESERVED_3"/>2082	<value value="4" name="A7XX_PERF_GBIF_RESERVED_4"/>2083	<value value="5" name="A7XX_PERF_GBIF_RESERVED_5"/>2084	<value value="6" name="A7XX_PERF_GBIF_RESERVED_6"/>2085	<value value="7" name="A7XX_PERF_GBIF_RESERVED_7"/>2086	<value value="8" name="A7XX_PERF_GBIF_RESERVED_8"/>2087	<value value="9" name="A7XX_PERF_GBIF_RESERVED_9"/>2088	<value value="10" name="A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/>2089	<value value="11" name="A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/>2090	<value value="12" name="A7XX_PERF_GBIF_RESERVED_12"/>2091	<value value="13" name="A7XX_PERF_GBIF_RESERVED_13"/>2092	<value value="14" name="A7XX_PERF_GBIF_RESERVED_14"/>2093	<value value="15" name="A7XX_PERF_GBIF_RESERVED_15"/>2094	<value value="16" name="A7XX_PERF_GBIF_RESERVED_16"/>2095	<value value="17" name="A7XX_PERF_GBIF_RESERVED_17"/>2096	<value value="18" name="A7XX_PERF_GBIF_RESERVED_18"/>2097	<value value="19" name="A7XX_PERF_GBIF_RESERVED_19"/>2098	<value value="20" name="A7XX_PERF_GBIF_RESERVED_20"/>2099	<value value="21" name="A7XX_PERF_GBIF_RESERVED_21"/>2100	<value value="22" name="A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/>2101	<value value="23" name="A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/>2102	<value value="24" name="A7XX_PERF_GBIF_RESERVED_24"/>2103	<value value="25" name="A7XX_PERF_GBIF_RESERVED_25"/>2104	<value value="26" name="A7XX_PERF_GBIF_RESERVED_26"/>2105	<value value="27" name="A7XX_PERF_GBIF_RESERVED_27"/>2106	<value value="28" name="A7XX_PERF_GBIF_RESERVED_28"/>2107	<value value="29" name="A7XX_PERF_GBIF_RESERVED_29"/>2108	<value value="30" name="A7XX_PERF_GBIF_RESERVED_30"/>2109	<value value="31" name="A7XX_PERF_GBIF_RESERVED_31"/>2110	<value value="32" name="A7XX_PERF_GBIF_RESERVED_32"/>2111	<value value="33" name="A7XX_PERF_GBIF_RESERVED_33"/>2112	<value value="34" name="A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/>2113	<value value="35" name="A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/>2114	<value value="36" name="A7XX_PERF_GBIF_RESERVED_36"/>2115	<value value="37" name="A7XX_PERF_GBIF_RESERVED_37"/>2116	<value value="38" name="A7XX_PERF_GBIF_RESERVED_38"/>2117	<value value="39" name="A7XX_PERF_GBIF_RESERVED_39"/>2118	<value value="40" name="A7XX_PERF_GBIF_RESERVED_40"/>2119	<value value="41" name="A7XX_PERF_GBIF_RESERVED_41"/>2120	<value value="42" name="A7XX_PERF_GBIF_RESERVED_42"/>2121	<value value="43" name="A7XX_PERF_GBIF_RESERVED_43"/>2122	<value value="44" name="A7XX_PERF_GBIF_RESERVED_44"/>2123	<value value="45" name="A7XX_PERF_GBIF_RESERVED_45"/>2124	<value value="46" name="A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/>2125	<value value="47" name="A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/>2126	<value value="48" name="A7XX_PERF_GBIF_RESERVED_48"/>2127	<value value="49" name="A7XX_PERF_GBIF_RESERVED_49"/>2128	<value value="50" name="A7XX_PERF_GBIF_RESERVED_50"/>2129	<value value="51" name="A7XX_PERF_GBIF_RESERVED_51"/>2130	<value value="52" name="A7XX_PERF_GBIF_RESERVED_52"/>2131	<value value="53" name="A7XX_PERF_GBIF_RESERVED_53"/>2132	<value value="54" name="A7XX_PERF_GBIF_RESERVED_54"/>2133	<value value="55" name="A7XX_PERF_GBIF_RESERVED_55"/>2134	<value value="56" name="A7XX_PERF_GBIF_RESERVED_56"/>2135	<value value="57" name="A7XX_PERF_GBIF_RESERVED_57"/>2136	<value value="58" name="A7XX_PERF_GBIF_RESERVED_58"/>2137	<value value="59" name="A7XX_PERF_GBIF_RESERVED_59"/>2138	<value value="60" name="A7XX_PERF_GBIF_RESERVED_60"/>2139	<value value="61" name="A7XX_PERF_GBIF_RESERVED_61"/>2140	<value value="62" name="A7XX_PERF_GBIF_RESERVED_62"/>2141	<value value="63" name="A7XX_PERF_GBIF_RESERVED_63"/>2142	<value value="64" name="A7XX_PERF_GBIF_RESERVED_64"/>2143	<value value="65" name="A7XX_PERF_GBIF_RESERVED_65"/>2144	<value value="66" name="A7XX_PERF_GBIF_RESERVED_66"/>2145	<value value="67" name="A7XX_PERF_GBIF_RESERVED_67"/>2146	<value value="68" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/>2147	<value value="69" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/>2148	<value value="70" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/>2149	<value value="71" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/>2150	<value value="72" name="A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/>2151	<value value="73" name="A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/>2152	<value value="74" name="A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/>2153	<value value="75" name="A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/>2154	<value value="76" name="A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/>2155	<value value="77" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/>2156	<value value="78" name="A7XX_PERF_GBIF_AXI_ALL_READ_BEATS"/>2157	<value value="79" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_BEATS"/>2158	<value value="80" name="A7XX_PERF_GBIF_AXI_ALL_BEATS"/>2159</enum>2160 2161<enum name="a7xx_ufc_perfcounter_select">2162	<value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/>2163	<value value="1" name="A7XX_PERF_UFC_READ_DATA_VBIF"/>2164	<value value="2" name="A7XX_PERF_UFC_WRITE_DATA_VBIF"/>2165	<value value="3" name="A7XX_PERF_UFC_READ_REQUEST_VBIF"/>2166	<value value="4" name="A7XX_PERF_UFC_WRITE_REQUEST_VBIF"/>2167	<value value="5" name="A7XX_PERF_UFC_LRZ_FILTER_HIT"/>2168	<value value="6" name="A7XX_PERF_UFC_LRZ_FILTER_MISS"/>2169	<value value="7" name="A7XX_PERF_UFC_CRE_FILTER_HIT"/>2170	<value value="8" name="A7XX_PERF_UFC_CRE_FILTER_MISS"/>2171	<value value="9" name="A7XX_PERF_UFC_SP_FILTER_HIT"/>2172	<value value="10" name="A7XX_PERF_UFC_SP_FILTER_MISS"/>2173	<value value="11" name="A7XX_PERF_UFC_SP_REQUESTS"/>2174	<value value="12" name="A7XX_PERF_UFC_TP_FILTER_HIT"/>2175	<value value="13" name="A7XX_PERF_UFC_TP_FILTER_MISS"/>2176	<value value="14" name="A7XX_PERF_UFC_TP_REQUESTS"/>2177	<value value="15" name="A7XX_PERF_UFC_MAIN_HIT_LRZ_PREFETCH"/>2178	<value value="16" name="A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/>2179	<value value="17" name="A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/>2180	<value value="18" name="A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/>2181	<value value="19" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_READ"/>2182	<value value="20" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/>2183	<value value="21" name="A7XX_PERF_UFC_MAIN_MISS_LRZ_PREFETCH"/>2184	<value value="22" name="A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/>2185	<value value="23" name="A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/>2186	<value value="24" name="A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/>2187	<value value="25" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_READ"/>2188	<value value="26" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/>2189	<value value="27" name="A7XX_PERF_UFC_UBWC_READ_UFC_TRANS"/>2190	<value value="28" name="A7XX_PERF_UFC_UBWC_WRITE_UFC_TRANS"/>2191	<value value="29" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/>2192	<value value="30" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/>2193	<value value="31" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/>2194	<value value="32" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/>2195	<value value="33" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/>2196	<value value="34" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/>2197	<value value="35" name="A7XX_PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES"/>2198	<value value="36" name="A7XX_PERF_UFC_CRE_PREFETCH_STALLED_CYCLES"/>2199	<value value="37" name="A7XX_PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES"/>2200	<value value="38" name="A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/>2201	<value value="39" name="A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/>2202	<value value="40" name="A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/>2203	<value value="41" name="A7XX_PERF_UFC_EVICTION_STALLED_CYCLES"/>2204	<value value="42" name="A7XX_PERF_UFC_LOCK_STALLED_CYCLES"/>2205	<value value="43" name="A7XX_PERF_UFC_MISS_LATENCY_CYCLES"/>2206	<value value="44" name="A7XX_PERF_UFC_MISS_LATENCY_SAMPLES"/>2207	<value value="45" name="A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/>2208	<value value="46" name="A7XX_PERF_UFC_TP_HINT_TAG_MISS"/>2209	<value value="47" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_RDY"/>2210	<value value="48" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_NRDY"/>2211	<value value="49" name="A7XX_PERF_UFC_TP_HINT_IS_FCLEAR"/>2212	<value value="50" name="A7XX_PERF_UFC_TP_HINT_IS_ALPHA0"/>2213	<value value="51" name="A7XX_PERF_UFC_SP_L1_FILTER_HIT"/>2214	<value value="52" name="A7XX_PERF_UFC_SP_L1_FILTER_MISS"/>2215	<value value="53" name="A7XX_PERF_UFC_SP_L1_FILTER_REQUESTS"/>2216	<value value="54" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_RDY"/>2217	<value value="55" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_NRDY"/>2218	<value value="56" name="A7XX_PERF_UFC_TP_L1_TAG_MISS"/>2219	<value value="57" name="A7XX_PERF_UFC_TP_L1_FILTER_REQUESTS"/>2220</enum>2221 2222<domain name="A6XX" width="32" prefix="variant" varset="chip">2223	<bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">2224		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>2225		<bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>2226		<bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>2227		<bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>2228		<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>2229		<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>2230		<bitfield name="CP_SW" pos="8" type="boolean"/>2231		<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>2232		<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>2233		<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>2234		<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>2235		<bitfield name="CP_IB2" pos="13" type="boolean"/>2236		<bitfield name="CP_IB1" pos="14" type="boolean"/>2237		<bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>2238		<!-- Same as above but different name??: -->2239		<bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>2240		<bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>2241		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>2242		<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>2243		<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>2244		<bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>2245		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>2246		<bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>2247		<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>2248		<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>2249		<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>2250		<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>2251		<bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>2252		<bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>2253		<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>2254		<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>2255	</bitset>2256 2257	<!--2258		Note the _LPAC bits probably *actually* first appeared in a660, but the2259		_BV bits are new in a7xx2260	 -->2261	<bitset name="A6XX_CP_INT" varset="chip">2262		<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>2263		<bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>2264		<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>2265		<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>2266		<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>2267		<bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>2268		<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>2269		<bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>2270		<bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>2271		<bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>2272		<bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>2273		<bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>2274		<bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>2275		<bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>2276		<bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>2277		<bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>2278		<bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>2279	</bitset>2280 2281	<reg64 offset="0x0800" name="CP_RB_BASE"/>2282	<reg32 offset="0x0802" name="CP_RB_CNTL"/>2283	<reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>2284	<reg32 offset="0x0806" name="CP_RB_RPTR"/>2285	<reg32 offset="0x0807" name="CP_RB_WPTR"/>2286	<reg32 offset="0x0808" name="CP_SQE_CNTL"/>2287	<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">2288		<bitfield name="IFPC" pos="0" type="boolean"/>2289	</reg32>2290	<reg32 offset="0x0821" name="CP_HW_FAULT"/>2291	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>2292	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>2293	<reg32 offset="0x0825" name="CP_STATUS_1"/>2294	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>2295	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>2296	<reg32 offset="0x0844" name="CP_APRIV_CNTL">2297		<!-- Crashdumper writes -->2298		<bitfield pos="6" name="CDWRITE" type="boolean"/>2299		<!-- Crashdumper reads -->2300		<bitfield pos="5" name="CDREAD" type="boolean"/>2301 2302		<!-- 4 is unknown -->2303 2304		<!-- RPTR shadow writes -->2305		<bitfield pos="3" name="RBRPWB" type="boolean"/>2306		<!-- Memory accesses from PM4 packets in the ringbuffer -->2307		<bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>2308		<!-- Ringbuffer reads -->2309		<bitfield pos="1" name="RBFETCH" type="boolean"/>2310		<!-- Instruction cache fetches -->2311		<bitfield pos="0" name="ICACHE" type="boolean"/>2312	</reg32>2313	<!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->2314	<reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>2315	<!-- all the threshold values seem to be in units of quad-dwords: -->2316	<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">2317		<doc>2318			b0..7 identifies where MRB data starts (and RB data ends)2319			b8.15 identifies where VSD data starts (and MRB data ends)2320			b16..23 identifies where IB1 data starts (and RB data ends)2321			b24..31 identifies where IB2 data starts (and IB1 data ends)2322		</doc>2323		<bitfield name="MRB_START" low="0" high="7" shr="2"/>2324		<bitfield name="VSD_START" low="8" high="15" shr="2"/>2325		<bitfield name="IB1_START" low="16" high="23" shr="2"/>2326		<bitfield name="IB2_START" low="24" high="31" shr="2"/>2327	</reg32>2328	<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">2329		<doc>2330			low bits identify where CP_SET_DRAW_STATE stateobj2331			processing starts (and IB2 data ends). I'm guessing2332			b8 is part of this since (from downstream kgsl):2333 2334				/* ROQ sizes are twice as big on a640/a680 than on a630 */2335				if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {2336					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);2337					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);2338				} ...2339		</doc>2340		<bitfield name="SDS_START" low="0" high="8" shr="2"/>2341		<!-- total ROQ size: -->2342		<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>2343	</reg32>2344	<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>2345	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>2346	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>2347	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>2348	<reg32 offset="0x084F" name="CP_PROTECT_CNTL">2349		<bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>2350		<bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>2351		<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>2352	</reg32>2353 2354	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">2355		<reg32 offset="0x0" name="REG" type="uint"/>2356	</array>2357	<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">2358		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>2359	</array>2360 2361	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>2362	<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>2363	<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>2364	<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>2365	<reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>2366	<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>2367	<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>2368	<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>2369	<reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>2370	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>2371	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>2372	<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>2373	<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>2374	<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>2375	<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>2376	<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>2377	<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>2378	<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>2379	<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>2380	<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>2381	<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>2382	<reg64 offset="0x0928" name="CP_IB1_BASE"/>2383	<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>2384	<reg64 offset="0x092B" name="CP_IB2_BASE"/>2385	<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>2386	<!-- SDS == CP_SET_DRAW_STATE: -->2387	<reg64 offset="0x092e" name="CP_SDS_BASE"/>2388	<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>2389	<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->2390	<reg64 offset="0x0931" name="CP_MRB_BASE"/>2391	<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>2392	<!--2393	VSD == Visibility Stream Decode2394	This is used by CP to read the draw stream and skip empty draws2395	-->2396	<reg64 offset="0x0934" name="CP_VSD_BASE"/>2397 2398	<bitset name="a6xx_roq_stat" inline="yes">2399		<bitfield name="RPTR" low="0" high="9"/>2400		<bitfield name="WPTR" low="16" high="25"/>2401	</bitset>2402	<reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/>2403	<reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/>2404	<reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/>2405	<reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/>2406	<reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/>2407	<reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/>2408 2409	<reg32 offset="0x0943" name="CP_IB1_DWORDS"/>2410	<reg32 offset="0x0944" name="CP_IB2_DWORDS"/>2411	<reg32 offset="0x0945" name="CP_SDS_DWORDS"/>2412	<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>2413	<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>2414 2415	<reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">2416		<doc>number of remaining dwords incl current dword being consumed?</doc>2417		<bitfield name="REM" low="16" high="31"/>2418	</reg32>2419	<reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">2420		<doc>number of remaining dwords incl current dword being consumed?</doc>2421		<bitfield name="REM" low="16" high="31"/>2422	</reg32>2423	<reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">2424		<doc>number of remaining dwords incl current dword being consumed?</doc>2425		<bitfield name="REM" low="16" high="31"/>2426	</reg32>2427	<reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">2428		<doc>number of remaining dwords incl current dword being consumed?</doc>2429		<bitfield name="REM" low="16" high="31"/>2430	</reg32>2431	<reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">2432		<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>2433		<bitfield name="REM" low="16" high="31"/>2434	</reg32>2435	<reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">2436		<doc>number of remaining dwords incl current dword being consumed?</doc>2437		<bitfield name="REM" low="16" high="31"/>2438	</reg32>2439 2440	<bitset name="a7xx_aperture_cntl" inline="yes">2441		<bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>2442		<bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>2443		<bitfield name="CONTEXT" low="4" high="5"/>2444	</bitset>2445	<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>2446	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>2447	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>2448	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>2449	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>2450	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>2451 2452	<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>2453	<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>2454	<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>2455	<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>2456	<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>2457	<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>2458	<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>2459	<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>2460	<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>2461	<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>2462	<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>2463	<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>2464	<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>2465 2466	<reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>2467	<reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>2468	<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>2469	<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>2470 2471	<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>2472	<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>2473	<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>2474	<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>2475	<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>2476	<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>2477	<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>2478 2479	<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>2480	<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>2481	<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>2482	<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>2483	<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>2484	<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>2485	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>2486 2487	<reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>2488	<reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>2489	<reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>2490 2491	<reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>2492	<reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>2493	<reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>2494	<reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>2495	<reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>2496	<reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>2497	<reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>2498	<reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>2499	<reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>2500	<reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>2501	<reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>2502	<reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>2503 2504	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>2505	<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>2506	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>2507	<reg32 offset="0x0210" name="RBBM_STATUS">2508		<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>2509		<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>2510		<bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>2511		<bitfield pos="20" name="VSC_BUSY" type="boolean"/>2512		<bitfield pos="19" name="TPL1_BUSY" type="boolean"/>2513		<bitfield pos="18" name="SP_BUSY" type="boolean"/>2514		<bitfield pos="17" name="UCHE_BUSY" type="boolean"/>2515		<bitfield pos="16" name="VPC_BUSY" type="boolean"/>2516		<bitfield pos="15" name="VFD_BUSY" type="boolean"/>2517		<bitfield pos="14" name="TESS_BUSY" type="boolean"/>2518		<bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>2519		<bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>2520		<bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>2521		<bitfield pos="10" name="LRZ_BUSY" type="boolean"/>2522		<bitfield pos="9"  name="A2D_BUSY" type="boolean"/>2523		<bitfield pos="8"  name="CCU_BUSY" type="boolean"/>2524		<bitfield pos="7"  name="RB_BUSY" type="boolean"/>2525		<bitfield pos="6"  name="RAS_BUSY" type="boolean"/>2526		<bitfield pos="5"  name="TSE_BUSY" type="boolean"/>2527		<bitfield pos="4"  name="VBIF_BUSY" type="boolean"/>2528		<bitfield pos="3"  name="GFX_DBGC_BUSY" type="boolean"/>2529		<bitfield pos="2"  name="CP_BUSY" type="boolean"/>2530		<bitfield pos="1"  name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>2531		<bitfield pos="0"  name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>2532	</reg32>2533	<reg32 offset="0x0211" name="RBBM_STATUS1"/>2534	<reg32 offset="0x0212" name="RBBM_STATUS2"/>2535	<reg32 offset="0x0213" name="RBBM_STATUS3">2536		<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>2537	</reg32>2538	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>2539 2540	<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>2541	<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>2542	<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>2543	<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>2544	<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>2545	<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>2546 2547	<reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>2548	<reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>2549 2550	<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>2551	<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>2552	<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>2553	<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>2554	<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>2555	<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>2556	<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>2557	<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>2558	<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>2559	<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>2560	<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>2561	<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>2562	<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>2563	<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>2564	<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>2565	<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>2566 2567	<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>2568	<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>2569	<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>2570	<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>2571	<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>2572	<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>2573	<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>2574	<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>2575	<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>2576	<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>2577	<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>2578	<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>2579	<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>2580	<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>2581	<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>2582	<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>2583	<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>2584	<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>2585	<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>2586	<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>2587	<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>2588	<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>2589	<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>2590	<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>2591	<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>2592	<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>2593	<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>2594	<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>2595 2596	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>2597	<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>2598	<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>2599	<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>2600	<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>2601	<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>2602	<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>2603	<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>2604	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>2605	<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>2606	<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>2607	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>2608	<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>2609	<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>2610 2611	<!---2612	    This block of registers aren't tied to perf counters. They2613	    count various geometry stats, for example number of2614	    vertices in, number of primnitives assembled etc.2615	-->2616 2617	<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->2618	<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>2619	<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->2620	<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>2621	<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->2622	<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>2623	<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->2624	<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>2625	<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->2626	<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>2627	<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->2628	<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>2629	<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->2630	<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>2631	<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->2632	<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>2633	<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->2634	<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>2635	<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->2636	<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>2637	<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>2638	<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>2639 2640	<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>2641	<reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>2642	<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>2643	<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>2644	<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>2645	<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>2646	<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>2647	<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>2648	<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>2649	<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>2650	<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">2651		<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>2652	</reg32>2653 2654	<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>2655	<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>2656	<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>2657	<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>2658	<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>2659	<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>2660	<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>2661	<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>2662	<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>2663	<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>2664	<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>2665	<reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>2666	<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>2667	<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>2668	<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>2669	<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>2670	<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>2671	<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>2672	<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>2673	<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>2674	<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>2675	<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>2676	<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>2677	<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>2678	<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>2679	<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>2680	<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>2681	<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>2682	<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>2683	<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>2684	<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>2685	<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>2686	<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>2687	<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>2688	<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>2689	<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>2690	<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>2691	<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>2692	<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>2693	<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>2694	<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>2695	<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>2696	<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>2697	<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>2698	<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>2699	<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>2700	<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>2701	<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>2702	<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>2703	<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>2704	<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>2705	<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>2706	<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>2707	<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>2708	<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>2709	<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>2710	<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>2711	<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>2712	<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>2713	<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>2714	<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>2715	<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>2716	<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>2717	<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>2718	<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>2719	<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>2720	<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>2721	<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>2722	<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>2723	<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>2724	<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>2725	<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>2726	<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>2727	<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>2728	<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>2729	<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>2730	<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>2731	<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>2732	<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>2733	<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>2734	<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>2735	<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>2736	<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>2737	<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>2738	<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>2739	<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>2740	<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>2741	<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>2742	<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>2743	<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>2744	<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>2745	<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>2746	<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>2747	<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>2748	<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>2749	<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>2750	<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>2751	<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>2752	<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>2753	<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>2754	<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>2755	<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>2756	<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>2757	<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>2758	<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>2759	<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>2760	<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>2761	<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>2762	<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>2763	<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>2764	<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>2765	<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>2766	<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>2767	<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>2768	<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>2769	<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>2770	<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>2771	<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>2772	<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>2773	<reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>2774	<reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>2775	<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>2776	<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>2777	<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>2778	<reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">2779		<bitfield name="TXDONE" pos="0" type="boolean"/>2780	</reg32>2781	<reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>2782	<reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>2783	<reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>2784	<reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>2785	<reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>2786	<reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>2787	<reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>2788	<reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>2789	<reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>2790	<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>2791	<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>2792 2793	<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>2794	<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>2795	<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>2796	<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">2797		<bitfield high="7" low="0" name="PING_INDEX"/>2798		<bitfield high="15" low="8" name="PING_BLK_SEL"/>2799	</reg32>2800	<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">2801		<bitfield high="5" low="0" name="TRACEEN"/>2802		<bitfield high="14" low="12" name="GRANU"/>2803		<bitfield high="31" low="28" name="SEGT"/>2804	</reg32>2805	<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">2806		<bitfield high="27" low="24" name="ENABLE"/>2807	</reg32>2808	<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>2809	<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>2810	<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>2811	<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>2812	<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>2813	<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>2814	<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>2815	<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>2816	<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">2817		<bitfield high="3" low="0" name="BYTEL0"/>2818		<bitfield high="7" low="4" name="BYTEL1"/>2819		<bitfield high="11" low="8" name="BYTEL2"/>2820		<bitfield high="15" low="12" name="BYTEL3"/>2821		<bitfield high="19" low="16" name="BYTEL4"/>2822		<bitfield high="23" low="20" name="BYTEL5"/>2823		<bitfield high="27" low="24" name="BYTEL6"/>2824		<bitfield high="31" low="28" name="BYTEL7"/>2825	</reg32>2826	<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">2827		<bitfield high="3" low="0" name="BYTEL8"/>2828		<bitfield high="7" low="4" name="BYTEL9"/>2829		<bitfield high="11" low="8" name="BYTEL10"/>2830		<bitfield high="15" low="12" name="BYTEL11"/>2831		<bitfield high="19" low="16" name="BYTEL12"/>2832		<bitfield high="23" low="20" name="BYTEL13"/>2833		<bitfield high="27" low="24" name="BYTEL14"/>2834		<bitfield high="31" low="28" name="BYTEL15"/>2835	</reg32>2836	<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>2837	<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>2838	<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>2839	<reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">2840		<doc>2841			Set to true when binning, isn't changed afterwards2842		</doc>2843		<bitfield name="BINNING" pos="0" type="boolean"/>2844	</reg32>2845	<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>2846	<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>2847	<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>2848	<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>2849	<reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>2850	<reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>2851	<reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>2852	<reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>2853	<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>2854	<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>2855	<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>2856	<reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">2857		<bitfield high="7" low="0" name="PERFSEL"/>2858	</reg32>2859	<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>2860	<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>2861	<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>2862 2863	<reg32 offset="0x3000" name="VBIF_VERSION"/>2864	<reg32 offset="0x3001" name="VBIF_CLKON">2865		<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>2866	</reg32>2867	<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>2868	<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>2869	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>2870	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>2871	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>2872	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">2873		<bitfield low="0" high="3" name="DATA_SEL"/>2874	</reg32>2875	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>2876	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">2877		<bitfield low="0" high="8" name="DATA_SEL"/>2878	</reg32>2879	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>2880	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>2881	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>2882	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>2883	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>2884	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>2885	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>2886	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>2887	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>2888	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>2889	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>2890	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>2891	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>2892	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>2893	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>2894	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>2895	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>2896	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>2897	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>2898	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>2899	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>2900	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>2901 2902	<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>2903	<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>2904	<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>2905	<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>2906	<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>2907	<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>2908	<reg32 offset="0x3c45" name="GBIF_HALT"/>2909	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>2910	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>2911	<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>2912	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>2913	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>2914	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>2915	<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>2916	<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>2917	<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>2918	<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>2919	<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>2920	<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>2921	<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>2922	<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>2923	<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>2924	<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>2925	<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>2926	<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>2927	<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>2928 2929	<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>2930	<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">2931		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>2932		<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>2933	</reg32>2934	<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/>2935	<reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit">2936		<bitfield name="NX" low="1" high="10" type="uint"/>2937		<bitfield name="NY" low="11" high="20" type="uint"/>2938	</reg32>2939	<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">2940		<reg32 offset="0x0" name="REG">2941			<doc>2942				Configures the mapping between VSC_PIPE buffer and2943				bin, X/Y specify the bin index in the horiz/vert2944				direction (0,0 is upper left, 0,1 is leftmost bin2945				on second row, and so on).  W/H specify the number2946				of bins assigned to this VSC_PIPE in the horiz/vert2947				dimension.2948			</doc>2949			<bitfield name="X" low="0" high="9" type="uint"/>2950			<bitfield name="Y" low="10" high="19" type="uint"/>2951			<bitfield name="W" low="20" high="25" type="uint"/>2952			<bitfield name="H" low="26" high="31" type="uint"/>2953		</reg32>2954	</array>2955	<!--2956	HW binning primitive & draw streams, which enable draws and primitives2957	within a draw to be skipped in the main tile pass.  See:2958	https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format2959 2960	Compared to a5xx and earlier, we just program the address of the first2961	stream and hw adds (pipe_num * VSC_*_STRM_PITCH)2962 2963	LIMIT is set to PITCH - 64, to make room for a bit of overflow2964	 -->2965	<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/>2966	<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/>2967	<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/>2968	<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/>2969	<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/>2970	<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/>2971 2972	<array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit">2973		<doc>2974			Seems to be a bitmap of which tiles mapped to the VSC2975			pipe contain geometry.2976 2977			I suppose we can connect a maximum of 32 tiles to a2978			single VSC pipe.2979		</doc>2980		<reg32 offset="0x0" name="REG"/>2981	</array>2982 2983	<array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">2984		<doc>2985			Has the size of data written to corresponding VSC_PRIM_STRM2986			buffer.2987		</doc>2988		<reg32 offset="0x0" name="REG"/>2989	</array>2990 2991	<array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">2992		<doc>2993			Has the size of data written to corresponding VSC pipe, ie.2994			same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI2995		</doc>2996		<reg32 offset="0x0" name="REG"/>2997	</array>2998 2999	<reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>3000 3001	<reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>3002	<reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>3003	<!-- always 0x03200000 ? -->3004	<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"  usage="cmd"/>3005 3006	<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->3007	<bitset name="a6xx_reg_xy" inline="yes">3008		<bitfield name="X" low="0" high="13" type="uint"/>3009		<bitfield name="Y" low="16" high="29" type="uint"/>3010	</bitset>3011 3012	<reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">3013		<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>3014		<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>3015		<bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>3016		<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>3017		<!-- controls near z clip behavior (set for vulkan) -->3018		<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>3019		<!-- guess based on a3xx and meaning of bits 8 and 93020		     if the guess is right then this is related to point sprite clipping -->3021		<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>3022		<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>3023		<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>3024	</reg32>3025 3026	<bitset name="a6xx_gras_xs_cl_cntl" inline="yes">3027		<bitfield name="CLIP_MASK" low="0" high="7"/>3028		<bitfield name="CULL_MASK" low="8" high="15"/>3029	</bitset>3030	<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>3031	<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>3032	<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>3033	<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>3034 3035	<reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit">3036		<!-- see also RB_RENDER_CONTROL0 -->3037		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>3038		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>3039		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>3040		<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>3041		<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>3042		<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>3043		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>3044		<bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>3045		<bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>3046	</reg32>3047	<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">3048		<bitfield name="HORZ" low="0" high="8" type="uint"/>3049		<bitfield name="VERT" low="10" high="18" type="uint"/>3050	</reg32>3051 3052	<!-- Something connected to depth-stencil attachment size -->3053	<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>3054 3055	<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>3056 3057	<reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>3058	<reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>3059	<reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>3060	<reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>3061 3062	<!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->3063 3064	<!-- 0x8006-0x800f invalid -->3065	<array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit">3066		<reg32 offset="0" name="XOFFSET" type="float"/>3067		<reg32 offset="1" name="XSCALE" type="float"/>3068		<reg32 offset="2" name="YOFFSET" type="float"/>3069		<reg32 offset="3" name="YSCALE" type="float"/>3070		<reg32 offset="4" name="ZOFFSET" type="float"/>3071		<reg32 offset="5" name="ZSCALE" type="float"/>3072	</array>3073	<array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit">3074		<reg32 offset="0" name="MIN" type="float"/>3075		<reg32 offset="1" name="MAX" type="float"/>3076	</array>3077 3078	<reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">3079		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>3080		<bitfield name="CULL_BACK" pos="1" type="boolean"/>3081		<bitfield name="FRONT_CW" pos="2" type="boolean"/>3082		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>3083		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>3084		<bitfield name="UNK12" pos="12"/>3085		<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>3086		<bitfield name="UNK15" low="15" high="16"/>3087		<!--3088                        On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have3089                        the ability to add the view index to either the RT array3090                        index or the viewport index, and it seems that3091                        MULTIVIEW_ENABLE doesn't do anything, instead we need to3092                        set at least one of RENDERTARGETINDEXINCR or3093                        VIEWPORTINDEXINCR to enable multiview. The blob still3094                        sets MULTIVIEW_ENABLE regardless.3095                        TODO: what about gen2 (a640)?3096		-->3097		<bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>3098		<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>3099		<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>3100		<bitfield name="UNK20" low="20" high="22"/>3101	</reg32>3102	<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">3103		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>3104		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>3105	</reg32>3106	<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/>3107	<!-- 0x8093 invalid -->3108	<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">3109		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>3110	</reg32>3111	<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>3112	<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>3113	<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>3114	<!-- duplicates RB_DEPTH_BUFFER_INFO: -->3115	<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">3116		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>3117		<bitfield name="UNK3" pos="3"/>3118	</reg32>3119 3120	<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">3121		<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>3122		<bitfield name="SHIFTAMOUNT" low="1" high="2"/>3123		<bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>3124		<bitfield name="UNK4" low="4" high="5"/>3125	</reg32>3126	<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">3127		<bitfield name="UNK0" pos="0" type="boolean"/>3128		<bitfield name="LINELENGTHEN" pos="1" type="boolean"/>3129	</reg32>3130 3131	<bitset name="a6xx_gras_layer_cntl" inline="yes">3132		<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>3133		<bitfield name="WRITES_VIEW" pos="1" type="boolean"/>3134	</bitset>3135	<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>3136	<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>3137	<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>3138	<!-- 0x809e/0x809f invalid -->3139 3140	<enum name="a6xx_sequenced_thread_dist">3141		<value value="0x0" name="DIST_SCREEN_COORD"/>3142		<value value="0x1" name="DIST_ALL_TO_RB0"/>3143	</enum>3144 3145	<enum name="a6xx_single_prim_mode">3146		<value value="0x0" name="NO_FLUSH"/>3147		<doc>3148			In addition to FLUSH_PER_OVERLAP, guarantee that UCHE3149			and CCU don't get out of sync when fetching the previous3150			value for the current pixel. With NO_FLUSH, there's the3151			possibility that the flags for the current pixel are3152			flushed before the data or vice-versa, leading to3153			texture fetches via UCHE getting out of sync values.3154			This mode should eliminate that. It's used in bypass3155			mode for coherent blending3156			(GL_KHR_blend_equation_advanced_coherent) as well as3157			non-coherent blending.3158		</doc>3159		<value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>3160		<doc>3161			Invalidate UCHE and wait for any pending work to finish3162			if there was possibly an overlapping primitive prior to3163			the current one. This is similar to a combination of3164			GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and3165			WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for3166			coherent blending3167			(GL_KHR_blend_equation_advanced_coherent).3168		</doc>3169		<value value="0x3" name="FLUSH_PER_OVERLAP"/>3170	</enum>3171 3172	<!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->3173	<enum name="a6xx_raster_mode">3174		<value value="0x0" name="TYPE_TILED"/>3175		<value value="0x1" name="TYPE_WRITER"/>3176	</enum>3177 3178	<!-- I'm guessing this is the same as a3xx -->3179	<enum name="a6xx_raster_direction">3180		<value value="0x0" name="LR_TB"/>3181		<value value="0x1" name="RL_TB"/>3182		<value value="0x2" name="LR_BT"/>3183		<value value="0x3" name="RB_BT"/>3184	</enum>3185 3186	<reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">3187		<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>3188		<bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>3189		<bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>3190		<bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>3191		<bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>3192		<!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->3193		<bitfield name="UNK9" pos="9" type="boolean"/>3194		<bitfield name="ROTATION" low="10" high="11" type="uint"/>3195		<bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>3196	</reg32>3197 3198	<enum name="a6xx_render_mode">3199		<value value="0x0" name="RENDERING_PASS"/>3200		<value value="0x1" name="BINNING_PASS"/>3201	</enum>3202 3203	<enum name="a6xx_buffers_location">3204		<value value="0" name="BUFFERS_IN_GMEM"/>3205		<value value="3" name="BUFFERS_IN_SYSMEM"/>3206	</enum>3207 3208	<enum name="a6xx_lrz_feedback_mask">3209		<value value="0x0" name="LRZ_FEEDBACK_NONE"/>3210		<value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/>3211		<value value="0x2" name="LRZ_FEEDBACK_EARLY_LRZ_LATE_Z"/>3212		<!-- We don't have a flag type and this flags combination is often used -->3213		<value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z"/>3214		<value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/>3215	</enum>3216 3217	<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit">3218		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>3219		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>3220		<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>3221		<doc>Disable LRZ feedback writes</doc>3222		<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>3223		<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>3224		<doc>3225			Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have3226			GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass.3227			In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered.3228		</doc>3229		<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>3230		<bitfield name="UNK27" pos="27"/>3231	</reg32>3232 3233	<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit">3234		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>3235		<bitfield name="UNK2" pos="2"/>3236		<bitfield name="UNK3" pos="3"/>3237	</reg32>3238	<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit">3239		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>3240		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>3241	</reg32>3242 3243	<bitset name="a6xx_sample_config" inline="yes">3244		<bitfield name="UNK0" pos="0"/>3245		<bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>3246	</bitset>3247 3248	<bitset name="a6xx_sample_locations" inline="yes">3249		<bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>3250		<bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>3251		<bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>3252		<bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>3253		<bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>3254		<bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>3255		<bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>3256		<bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>3257	</bitset>3258 3259	<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>3260	<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>3261	<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>3262 3263	<reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>3264 3265	<!-- 0x80a7-0x80ae invalid -->3266	<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>3267 3268	<bitset name="a6xx_scissor_xy" inline="yes">3269		<bitfield name="X" low="0" high="15" type="uint"/>3270		<bitfield name="Y" low="16" high="31" type="uint"/>3271	</bitset>3272	<array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">3273		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>3274		<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>3275	</array>3276	<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">3277		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>3278		<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>3279	</array>3280 3281	<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>3282	<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>3283 3284	<!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->3285	<reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>3286	<reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>3287	<reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>3288	<reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>3289	<reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>3290	<reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>3291 3292	<enum name="a6xx_lrz_dir_status">3293		<value value="0x1" name="LRZ_DIR_LE"/>3294		<value value="0x2" name="LRZ_DIR_GE"/>3295		<value value="0x3" name="LRZ_DIR_INVALID"/>3296	</enum>3297 3298	<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">3299		<bitfield name="ENABLE" pos="0" type="boolean"/>3300		<doc>LRZ write also disabled for blend/etc.</doc>3301		<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>3302		<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>3303		<bitfield name="GREATER" pos="2" type="boolean"/>3304		<doc>3305			Clears the LRZ block being touched to:3306			- 0.0 if GREATER3307			- 1.0 if LESS3308		</doc>3309		<bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>3310		<!-- set when depth-test + depth-write enabled -->3311		<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>3312		<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>3313		<bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>3314		<doc>3315			If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into3316			buffer, in case of mismatched direction writes 0 (disables LRZ).3317		</doc>3318		<bitfield name="DIR_WRITE" pos="8" type="boolean"/>3319		<doc>3320			Disable LRZ based on previous direction and the current one.3321			If DIR_WRITE is not enabled - there is no write to direction buffer.3322		</doc>3323		<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>3324		<bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>3325	</reg32>3326 3327	<enum name="a6xx_fragcoord_sample_mode">3328		<value value="0" name="FRAGCOORD_CENTER"/>3329		<value value="3" name="FRAGCOORD_SAMPLE"/>3330	</enum>3331 3332	<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">3333		<bitfield name="SAMPLEID" pos="0" type="boolean"/>3334		<bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>3335	</reg32>3336 3337	<reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit">3338		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>3339	</reg32>3340	<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>3341	<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">3342		<!-- TODO: fix the shr fields -->3343		<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>3344		<bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>3345	</reg32>3346 3347	<!--3348	The LRZ "fast clear" buffer is initialized to zero's by blob, and3349	read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears3350	to store 1b/block.  It appears that '0' means block has original3351	depth clear value, and '1' means that the corresponding block in3352	LRZ has been modified.  Ignoring alignment/padding, the size is3353	given by the formula:3354 3355		// calculate LRZ size from depth size:3356		if (nr_samples == 4) {3357			width *= 2;3358			height *= 2;3359		} else if (nr_samples == 2) {3360			height *= 2;3361		}3362 3363		lrz_width = div_round_up(width, 8);3364		lrz_heigh = div_round_up(height, 8);3365 3366		// calculate # of blocks:3367		nblocksx = div_round_up(lrz_width, 16);3368		nblocksy = div_round_up(lrz_height, 4);3369 3370		// fast-clear buffer is 1bit/block:3371		fc_sz = div_round_up(nblocksx * nblocksy, 8);3372 3373	In practice the blob seems to switch off FC_ENABLE once the size3374	increases beyond 1 page.  Not sure if that is an actual limit or3375	not.3376	 -->3377	<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/>3378	<!-- 0x8108 invalid -->3379	<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit">3380		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>3381	</reg32>3382	<!--3383	LRZ buffer represents a single array layer + mip level, and there is3384	a single buffer per depth image. Thus to reuse LRZ between renderpasses3385	it is necessary to track the depth view used in the past renderpass, which3386	GRAS_LRZ_DEPTH_VIEW is for.3387	GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to3388	the value stored in the LRZ buffer, if not - LRZ is disabled.3389	-->3390	<reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd">3391		<bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>3392		<bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>3393		<bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>3394	</reg32>3395 3396	<reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">3397		<bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/>3398		<bitfield name="FC_ENABLE" pos="1" type="boolean"/>3399	</reg32>3400 3401	<!-- 0x810c-0x810f invalid -->3402 3403	<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>3404 3405	<!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->3406	<reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>3407 3408	<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">3409		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>3410		<bitfield name="UNK3" pos="3"/>3411	</reg32>3412 3413	<!-- Always written together and always equal 09510840 00000a62 -->3414	<reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>3415	<reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>3416 3417	<!-- 0x8112-0x83ff invalid -->3418 3419	<enum name="a6xx_rotation">3420		<value value="0x0" name="ROTATE_0"/>3421		<value value="0x1" name="ROTATE_90"/>3422		<value value="0x2" name="ROTATE_180"/>3423		<value value="0x3" name="ROTATE_270"/>3424		<value value="0x4" name="ROTATE_HFLIP"/>3425		<value value="0x5" name="ROTATE_VFLIP"/>3426	</enum>3427 3428	<bitset name="a6xx_2d_blit_cntl" inline="yes">3429		<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>3430		<bitfield name="OVERWRITEEN" pos="3" type="boolean"/>3431		<bitfield name="UNK4" low="4" high="6"/>3432		<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>3433		<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>3434		<bitfield name="SCISSOR" pos="16" type="boolean"/>3435		<bitfield name="UNK17" low="17" high="18"/>3436		<!-- required when blitting D24S8/D24X8 -->3437		<bitfield name="D24S8" pos="19" type="boolean"/>3438		<!-- some sort of channel mask, disabled channels are set to zero ? -->3439		<bitfield name="MASK" low="20" high="23"/>3440		<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>3441		<bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>3442		<bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>3443	</bitset>3444 3445	<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>3446	<!-- note: the low 8 bits for src coords are valid, probably fixed point3447	     it would be a bit weird though, since we subtract 1 from BR coords3448	     apparently signed, gallium driver uses negative coords and it works?3449	 -->3450	<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>3451	<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>3452	<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>3453	<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>3454	<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/>3455	<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/>3456	<reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>3457	<reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>3458	<reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>3459	<reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/>3460	<reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/>3461	<!-- 0x840c-0x85ff invalid -->3462 3463	<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->3464	<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">3465		<bitfield name="UNK7" pos="7" type="boolean"/>3466		<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>3467	</reg32>3468	<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>3469	<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>3470	<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>3471	<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>3472	<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>3473 3474	<!-- note 0x8620-0x87ff are not all invalid3475	(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)3476	-->3477 3478	<!-- same as GRAS_BIN_CONTROL, but without bit 27: -->3479	<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit">3480		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>3481		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>3482		<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>3483		<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>3484		<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>3485		<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>3486	</reg32>3487 3488	<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">3489		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>3490		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>3491		<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>3492		<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>3493		<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>3494	</reg32>3495 3496	<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">3497		<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>3498		<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>3499		<!-- set during binning pass: -->3500		<bitfield name="BINNING" pos="7" type="boolean"/>3501		<bitfield name="UNK8" low="8" high="10"/>3502		<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>3503		<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>3504		<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>3505		<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>3506		<!-- bit seems to be set whenever depth buffer enabled: -->3507		<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>3508		<!-- bitmask of MRTs using UBWC flag buffer: -->3509		<bitfield name="FLAG_MRTS" low="16" high="23"/>3510	</reg32>3511	<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">3512		<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>3513		<!-- set during binning pass: -->3514		<bitfield name="BINNING" pos="7" type="boolean"/>3515		<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>3516		<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>3517		<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>3518		<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>3519	</reg32>3520	<reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">3521		<bitfield name="BINNING" pos="7" type="boolean"/>3522	</reg32>3523 3524	<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">3525		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>3526		<bitfield name="UNK2" pos="2"/>3527		<bitfield name="UNK3" pos="3"/>3528	</reg32>3529	<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit">3530		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>3531		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>3532	</reg32>3533 3534	<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>3535	<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>3536	<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>3537	<!-- 0x8807-0x8808 invalid -->3538	<!--3539	note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL3540	name comes from kernel and is probably right)3541	 -->3542	<reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit">3543		<!-- see also GRAS_CNTL -->3544		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>3545		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>3546		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>3547		<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>3548		<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>3549		<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>3550		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>3551		<bitfield name="UNK10" pos="10" type="boolean"/>3552	</reg32>3553	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit">3554		<!-- enable bits for various FS sysvalue regs: -->3555		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>3556		<bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>3557		<bitfield name="FACENESS" pos="2" type="boolean"/>3558		<bitfield name="SAMPLEID" pos="3" type="boolean"/>3559		<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>3560		<bitfield name="CENTERRHW" pos="6" type="boolean"/>3561		<bitfield name="LINELENGTHEN" pos="7" type="boolean"/>3562		<bitfield name="FOVEATION" pos="8" type="boolean"/>3563	</reg32>3564 3565	<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit">3566		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>3567		<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>3568		<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>3569		<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>3570	</reg32>3571	<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit">3572		<bitfield name="MRT" low="0" high="3" type="uint"/>3573	</reg32>3574	<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit">3575		<bitfield name="RT0" low="0" high="3"/>3576		<bitfield name="RT1" low="4" high="7"/>3577		<bitfield name="RT2" low="8" high="11"/>3578		<bitfield name="RT3" low="12" high="15"/>3579		<bitfield name="RT4" low="16" high="19"/>3580		<bitfield name="RT5" low="20" high="23"/>3581		<bitfield name="RT6" low="24" high="27"/>3582		<bitfield name="RT7" low="28" high="31"/>3583	</reg32>3584	<reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd">3585		<bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>3586		<bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>3587		<bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>3588		<bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>3589		<bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>3590		<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>3591		<bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>3592		<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>3593	</reg32>3594	<reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit">3595		<!-- Same as SP_SRGB_CNTL -->3596		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>3597		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>3598		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>3599		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>3600		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>3601		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>3602		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>3603		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>3604	</reg32>3605 3606	<reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit">3607		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>3608	</reg32>3609	<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>3610	<reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>3611	<!-- 0x8813-0x8817 invalid -->3612	<!-- always 0x0 ? -->3613	<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>3614	<!-- 0x8819-0x881e all 32 bits -->3615	<reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/>3616	<reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/>3617	<reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/>3618	<reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>3619	<reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>3620	<reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>3621	<!-- 0x881f invalid -->3622	<array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">3623		<reg32 offset="0x0" name="CONTROL">3624			<bitfield name="BLEND" pos="0" type="boolean"/>3625			<bitfield name="BLEND2" pos="1" type="boolean"/>3626			<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>3627			<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>3628			<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>3629		</reg32>3630		<reg32 offset="0x1" name="BLEND_CONTROL">3631			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>3632			<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>3633			<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>3634			<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>3635			<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>3636			<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>3637		</reg32>3638		<reg32 offset="0x2" name="BUF_INFO" variants="A6XX">3639			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>3640			<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>3641			<bitfield name="UNK10" pos="10"/>3642			<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>3643		</reg32>3644		<reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">3645			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>3646			<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>3647			<bitfield name="UNK10" pos="10"/>3648			<bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/>3649			<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>3650			<bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>3651		</reg32>3652		<!--3653		at least in gmem, things seem to be aligned to pitch of 64..3654		maybe an artifact of tiled format used in gmem?3655		 -->3656		<reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>3657		<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>3658		<!--3659		Compared to a5xx and before, we configure both a GMEM base and3660		external base.  Not sure if this is to facilitate GMEM save/3661		restore for context switch, or just to simplify state setup to3662		not have to care about GMEM vs BYPASS mode.3663		 -->3664		<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->3665		<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>3666 3667		<reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>3668	</array>3669 3670	<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/>3671	<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/>3672	<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/>3673	<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/>3674	<reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd">3675		<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>3676		<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>3677		<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>3678	</reg32>3679	<reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit">3680		<!-- per-mrt enable bit -->3681		<bitfield name="ENABLE_BLEND" low="0" high="7"/>3682		<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>3683		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>3684		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>3685		<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>3686		<bitfield name="SAMPLE_MASK" low="16" high="31"/>3687	</reg32>3688	<!-- 0x8866-0x886f invalid -->3689	<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit">3690		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>3691	</reg32>3692 3693	<reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">3694		<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>3695		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>3696		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>3697		<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>3698		<doc>3699		Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER3700		also set when Z_BOUNDS_ENABLE is set3701		</doc>3702		<bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>3703		<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>3704	</reg32>3705	<reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit">3706		<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>3707	</reg32>3708	<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->3709	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit">3710		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>3711		<bitfield name="UNK3" low="3" high="4"/>3712	</reg32>3713	<!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->3714	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">3715		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>3716		<bitfield name="UNK3" low="3" high="4"/>3717		<bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>3718		<bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>3719	</reg32>3720 3721	<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/>3722	<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/>3723	<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>3724	<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>3725 3726	<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/>3727	<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/>3728	<!-- 0x887a-0x887f invalid -->3729	<reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit">3730		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>3731		<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>3732		<!--3733			set for stencil operations that require read from stencil3734			buffer, but not for example for stencil clear (which does3735			not require read).. so guessing this is analogous to3736			READ_DEST_ENABLE for color buffer..3737		 -->3738		<bitfield name="STENCIL_READ" pos="2" type="boolean"/>3739		<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>3740		<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>3741		<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>3742		<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>3743		<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>3744		<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>3745		<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>3746		<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>3747	</reg32>3748	<reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit">3749		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>3750	</reg32>3751	<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit">3752		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>3753		<bitfield name="UNK1" pos="1" type="boolean"/>3754	</reg32>3755	<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">3756		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>3757		<bitfield name="UNK1" pos="1" type="boolean"/>3758		<bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>3759	</reg32>3760	<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/>3761	<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/>3762	<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>3763	<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>3764	<reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit">3765		<bitfield name="REF" low="0" high="7"/>3766		<bitfield name="BFREF" low="8" high="15"/>3767	</reg32>3768	<reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit">3769		<bitfield name="MASK" low="0" high="7"/>3770		<bitfield name="BFMASK" low="8" high="15"/>3771	</reg32>3772	<reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit">3773		<bitfield name="WRMASK" low="0" high="7"/>3774		<bitfield name="BFWRMASK" low="8" high="15"/>3775	</reg32>3776	<!-- 0x888a-0x888f invalid -->3777	<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>3778	<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd">3779		<bitfield name="DISABLE" pos="0" type="boolean"/>3780		<bitfield name="COPY" pos="1" type="boolean"/>3781	</reg32>3782	<!-- 0x8892-0x8897 invalid -->3783	<reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">3784		<bitfield name="ENABLE" pos="0" type="boolean"/>3785	</reg32>3786	<reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>3787	<!-- 0x8899-0x88bf invalid -->3788	<!-- clamps depth value for depth test/write -->3789	<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/>3790	<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/>3791	<!-- 0x88c2-0x88cf invalid-->3792	<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit">3793		<bitfield name="UNK0" low="0" high="12"/>3794		<bitfield name="UNK16" low="16" high="26"/>3795	</reg32>3796	<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>3797	<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>3798	<!-- weird to duplicate other regs from same block?? -->3799	<reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit">3800		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>3801		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>3802	</reg32>3803	<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/>3804	<reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit">3805		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>3806	</reg32>3807	<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>3808	<!-- s/DST_FORMAT/DST_INFO/ probably: -->3809	<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit">3810		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>3811		<bitfield name="FLAGS" pos="2" type="boolean"/>3812		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>3813		<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>3814		<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>3815		<bitfield name="UNK15" pos="15" type="boolean"/>3816		<bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>3817	</reg32>3818	<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/>3819	<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>3820	<!-- array-pitch is size of layer -->3821	<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/>3822	<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/>3823	<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit">3824		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>3825		<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>3826	</reg32>3827 3828	<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/>3829	<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/>3830	<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>3831	<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>3832 3833	<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->3834	<reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">3835		<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->3836		<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->3837		<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->3838		<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->3839		<doc>3840			For clearing depth/stencil3841				1 - depth3842				2 - stencil3843				3 - depth+stencil3844			For clearing color buffer:3845				then probably a component mask, I always see 0xf3846		</doc>3847		<bitfield name="CLEAR_MASK" low="4" high="7"/>3848		<!-- set when this is the last resolve on a650+ -->3849		<bitfield name="LAST" low="8" high="9"/>3850		<!--3851			a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.3852			a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.3853 3854			We believe this is related to concurrent resolves3855		 -->3856		<bitfield name="BUFFER_ID" low="12" high="15"/>3857	</reg32>3858	<reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">3859		<!-- Value conditioned based on predicate, changed before blits -->3860		<bitfield name="UNK0" pos="0" type="boolean"/>3861	</reg32>3862 3863	<enum name="a6xx_ccu_cache_size">3864		<value value="0x0" name="CCU_CACHE_SIZE_FULL"/>3865		<value value="0x1" name="CCU_CACHE_SIZE_HALF"/>3866		<value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>3867		<value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>3868	</enum>3869	<reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">3870		<bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>3871		<bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>3872		<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>3873		<!-- GMEM offset of CCU depth cache -->3874		<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>3875		<bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>3876		<!-- GMEM offset of CCU color cache3877			for GMEM rendering, we set it to GMEM size minus the minimum3878			CCU color cache size. CCU color cache will be needed in some3879			resolve cases, and in those cases we need to reserve the end3880			of GMEM for color cache.3881		-->3882		<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>3883	</reg32>3884	<!-- 0x88e6-0x88ef invalid -->3885	<!-- always 0x0 ? -->3886	<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>3887	<!-- could be for separate stencil? (or may not be a flag buffer at all) -->3888	<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>3889	<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">3890		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>3891		<bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>3892	</reg32>3893	<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>3894	<!-- Connected to VK_EXT_fragment_density_map? -->3895	<reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>3896	<!-- 0x88f6-0x88ff invalid -->3897	<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>3898	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">3899		<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>3900		<!-- TODO: actually part of array pitch -->3901		<bitfield name="UNK8" low="8" high="10"/>3902		<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>3903	</reg32>3904	<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit">3905		<reg64 offset="0" name="ADDR" type="waddress" align="64"/>3906		<reg32 offset="2" name="PITCH">3907			<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>3908			<bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>3909		</reg32>3910	</array>3911	<!-- 0x891b-0x8926 invalid -->3912	<doc>3913		RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that3914		the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT.3915	</doc>3916	<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/>3917	<!-- 0x8929-0x89ff invalid -->3918 3919	<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->3920 3921	<!--3922		These show up in a6xx gen3+ but so far haven't found an example of3923		blob writing non-zero:3924	 -->3925	<reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/>3926	<reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/>3927	<reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>3928	<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>3929 3930	<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>3931	<reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>3932 3933	<bitset name="a6xx_2d_src_surf_info" inline="yes">3934		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>3935		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>3936		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>3937		<bitfield name="FLAGS" pos="12" type="boolean"/>3938		<bitfield name="SRGB" pos="13" type="boolean"/>3939		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>3940		<bitfield name="FILTER" pos="16" type="boolean"/>3941		<bitfield name="UNK17" pos="17" type="boolean"/>3942		<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>3943		<bitfield name="UNK19" pos="19" type="boolean"/>3944		<bitfield name="UNK20" pos="20" type="boolean"/>3945		<bitfield name="UNK21" pos="21" type="boolean"/>3946		<bitfield name="UNK22" pos="22" type="boolean"/>3947		<bitfield name="UNK23" low="23" high="26"/>3948		<bitfield name="UNK28" pos="28" type="boolean"/>3949		<bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/>3950	</bitset>3951 3952	<bitset name="a6xx_2d_dst_surf_info" inline="yes">3953		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>3954		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>3955		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>3956		<bitfield name="FLAGS" pos="12" type="boolean"/>3957		<bitfield name="SRGB" pos="13" type="boolean"/>3958		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>3959		<bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/>3960	</bitset>3961 3962	<!-- 0x8c02-0x8c16 invalid -->3963	<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_dst_surf_info" usage="rp_blit"/>3964	<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/>3965	<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>3966	<!-- this is a guess but seems likely (for NV12/IYUV): -->3967	<reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/>3968	<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>3969	<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/>3970 3971	<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/>3972	<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>3973	<!-- this is a guess but seems likely (for NV12 with UBWC): -->3974	<reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/>3975	<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>3976 3977	<!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->3978	<!-- unlike a5xx, these are per channel values rather than packed -->3979	<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/>3980	<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>3981	<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>3982	<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>3983 3984	<reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>3985 3986	<!-- 0x8c35-0x8dff invalid -->3987 3988	<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->3989	<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>3990	<!-- 0x8e00-0x8e03 invalid -->3991	<reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->3992	<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>3993	<!-- 0x02080000 in GMEM, zero otherwise?  -->3994	<reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>3995 3996	<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX">3997		<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>3998		<!-- concurrent resolves are apparently a 2-bit enum on a650+ -->3999		<bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>4000		<bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/>4001		<bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/>4002		<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>4003		<!-- GMEM offset of CCU depth cache -->4004		<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>4005		<bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>4006		<!-- GMEM offset of CCU color cache4007			for GMEM rendering, we set it to GMEM size minus the minimum4008			CCU color cache size. CCU color cache will be needed in some4009			resolve cases, and in those cases we need to reserve the end4010			of GMEM for color cache.4011		-->4012		<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>4013		<!--TODO: valid mask 0xfffffc1f -->4014	</reg32>4015	<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">4016		<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>4017		<bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>4018		<!-- rest of the bits were moved to RB_CCU_CNTL2 -->4019	</reg32>4020	<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">4021		<bitfield name="MODE" pos="0" type="boolean"/>4022		<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>4023		<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->4024		<bitfield name="AMSBC" pos="4" type="boolean"/>4025		<bitfield name="UPPER_BIT" pos="10" type="uint"/>4026		<bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>4027		<bitfield name="UNK12" low="12" high="13"/>4028	</reg32>4029	<reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>4030	<!-- 0x8e09-0x8e0f invalid -->4031	<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>4032	<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>4033	<!-- 0x8e1d-0x8e1f invalid -->4034	<!-- 0x8e20-0x8e25 more perfcntr sel? -->4035	<!-- 0x8e26-0x8e27 invalid -->4036	<reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/>4037	<!-- 0x8e29-0x8e2b invalid -->4038	<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>4039	<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>4040	<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>4041	<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>4042	<!-- 0x8e3e-0x8e4f invalid -->4043	<!-- GMEM save/restore for preemption: -->4044	<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>4045	<!-- address for GMEM save/restore? -->4046	<reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>4047	<!-- 0x8e53-0x8e7f invalid -->4048	<reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>4049	<!-- 0x8e80-0x8e83 are valid -->4050	<!-- 0x8e84-0x90ff invalid -->4051 4052	<!-- 0x9000-0x90ff invalid -->4053 4054	<reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit">4055		<bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>4056	</reg32>4057 4058	<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">4059		<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>4060		<!-- there can be up to 8 total clip/cull distance outputs,4061		     but apparenly VPC can only deal with vec4, so when there are4062		     more than 4 outputs a second location needs to be programmed4063		-->4064		<bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>4065		<bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>4066	</bitset>4067	<reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4068	<reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4069	<reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4070 4071	<reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4072	<reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4073	<reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>4074 4075	<bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">4076		<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>4077		<bitfield name="VIEWLOC" low="8" high="15" type="uint"/>4078		<bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>4079	</bitset>4080 4081	<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4082	<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4083	<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4084 4085	<reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4086	<reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4087	<reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>4088 4089	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">4090		<!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->4091		<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>4092		<bitfield name="UNK2" pos="2" type="boolean"/>4093	</reg32>4094	<reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit">4095		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>4096	</reg32>4097 4098	<bitset name="a6xx_primitive_cntl_0" inline="yes">4099		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>4100		<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>4101		<bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean">4102			<doc>4103				Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes4104				triangle fans and triangle strips use the D3D4105				order instead of the OpenGL order.4106			</doc>4107		</bitfield>4108		<bitfield name="UNK3" pos="3" type="boolean"/>4109	</bitset>4110 4111	<bitset name="a6xx_primitive_cntl_5" inline="yes">4112		<doc>4113		  geometry shader4114		</doc>4115		<!-- TODO: first 16 bits are valid so something is wrong or missing here -->4116		<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>4117		<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>4118		<bitfield name="LINELENGTHEN" pos="15" type="boolean"/>4119		<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>4120		<bitfield name="UNK18" pos="18"/>4121	</bitset>4122 4123	<bitset name="a6xx_multiview_cntl" inline="yes">4124		<bitfield name="ENABLE" pos="0" type="boolean"/>4125		<bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">4126			<doc>4127				Multi-position output lets the last geometry4128				stage shader write multiple copies of4129				gl_Position. If disabled then the VS is run once4130				for each view, and ViewID is passed as a4131				register to the VS.4132			</doc>4133		</bitfield>4134		<bitfield name="VIEWS" low="2" high="6" type="uint"/>4135	</bitset>4136 4137	<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/>4138	<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/>4139	<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/>4140	<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/>4141 4142	<enum name="a6xx_varying_interp_mode">4143		<value value="0" name="INTERP_SMOOTH"/>4144		<value value="1" name="INTERP_FLAT"/>4145		<value value="2" name="INTERP_ZERO"/>4146		<value value="3" name="INTERP_ONE"/>4147	</enum>4148 4149	<enum name="a6xx_varying_ps_repl_mode">4150		<value value="0" name="PS_REPL_NONE"/>4151		<value value="1" name="PS_REPL_S"/>4152		<value value="2" name="PS_REPL_T"/>4153		<value value="3" name="PS_REPL_ONE_MINUS_T"/>4154	</enum>4155 4156	<!-- 0x9109-0x91ff invalid -->4157	<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">4158		<doc>Packed array of a6xx_varying_interp_mode</doc>4159		<reg32 offset="0x0" name="MODE"/>4160	</array>4161	<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">4162		<doc>Packed array of a6xx_varying_ps_repl_mode</doc>4163		<reg32 offset="0x0" name="MODE"/>4164	</array>4165 4166	<!-- always 0x0 -->4167	<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>4168	<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>4169 4170	<array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit">4171		<!-- one bit per varying component: -->4172		<reg32 offset="0" name="DISABLE"/>4173	</array>4174 4175	<reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit">4176		<!--4177			Choose which DWORD to write to. There is an array of4178			(4 * 64) DWORD's, dumped in the devcoredump at4179			HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a4180			(VPC location, stream) pair like so:4181 4182			location 0, stream 04183			location 2, stream 04184			...4185			location 126, stream 04186			location 0, stream 14187			location 2, stream 14188			...4189			location 126, stream 14190			location 0, stream 24191			...4192 4193			When EmitStreamVertex(N) happens, the HW goes to DWORD4194			64 * N and then "executes" the next 64 DWORD's.4195 4196			This field is auto-incremented when VPC_SO_PROG is4197			written to.4198		-->4199		<bitfield name="ADDR" low="0" high="7" type="hex"/>4200		<!-- clear all A_EN and B_EN bits for all DWORD's -->4201		<bitfield name="RESET" pos="16" type="boolean"/>4202	</reg32>4203	<!-- special register, write multiple times to load SO program (not readable) -->4204	<reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit">4205		<bitfield name="A_BUF" low="0" high="1" type="uint"/>4206		<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>4207		<bitfield name="A_EN" pos="11" type="boolean"/>4208		<bitfield name="B_BUF" low="12" high="13" type="uint"/>4209		<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>4210		<bitfield name="B_EN" pos="23" type="boolean"/>4211	</reg32>4212 4213	<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/>4214 4215	<array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd">4216		<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>4217		<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>4218		<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>4219		<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>4220		<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>4221	</array>4222 4223	<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd">4224		<bitfield name="INVERT" pos="0" type="boolean"/>4225	</reg32>4226	<!-- 0x9237-0x92ff invalid -->4227	<!-- always 0x0 ? -->4228	<reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>4229 4230	<bitset name="a6xx_vpc_xs_pack" inline="yes">4231		<doc>4232			num of varyings plus four for gl_Position (plus one if gl_PointSize)4233			plus # of transform-feedback (streamout) varyings if using the4234			hw streamout (rather than stg instructions in shader)4235		</doc>4236		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>4237		<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>4238		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>4239		<bitfield name="EXTRAPOS" low="24" high="27" type="uint">4240			<doc>4241				The number of extra copies of POSITION, i.e.4242				number of views minus one when multi-position4243				output is enabled, otherwise 0.4244			</doc>4245		</bitfield>4246	</bitset>4247	<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>4248	<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>4249	<reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>4250 4251	<reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit">4252		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>4253		<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->4254		<bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>4255		<bitfield name="VARYING" pos="16" type="boolean"/>4256		<bitfield name="VIEWIDLOC" low="24" high="31" type="uint">4257			<doc>4258				This VPC location will be overwritten with4259				ViewID when multiview is enabled. It's used when4260				fragment shaders read ViewID. It's only4261				strictly required for multi-position output,4262				where the same VS invocation is used for all the4263				views at once, but it can be used when multi-pos4264				output is disabled too, to avoid having to pass4265				ViewID through the VS.4266			</doc>4267		</bitfield>4268	</reg32>4269 4270	<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit">4271		<!--4272		It's offset by 1, and 0 means "disabled"4273		-->4274		<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>4275		<bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>4276		<bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>4277		<bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>4278		<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>4279	</reg32>4280	<reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit">4281		<bitfield name="DISABLE" pos="0" type="boolean"/>4282	</reg32>4283	<reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">4284		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>4285	</reg32>4286	<reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">4287		<bitfield name="SIZE_GMEM" low="0" high="31"/>4288	</reg32>4289	<reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">4290		<bitfield name="BASE_GMEM" low="0" high="31"/>4291	</reg32>4292	<reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">4293		<bitfield name="SIZE_GMEM" low="0" high="31"/>4294	</reg32>4295 4296	<!-- 0x9307-0x95ff invalid -->4297 4298	<!-- TODO: 0x9600-0x97ff range -->4299	<reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->4300	<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>4301	<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->4302	<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>4303	<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>4304	<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>4305	<!-- 0x960a-0x9623 invalid -->4306	<!-- TODO: regs from 0x9624-0x963a -->4307	<!-- 0x963b-0x97ff invalid -->4308 4309	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>4310 4311	<!-- always 0x0 ? -->4312	<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit">4313		<bitfield name="SIZE" low="0" high="10" type="uint"/>4314		<bitfield name="UNK13" pos="13"/>4315	</reg32>4316 4317	<reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit">4318		<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>4319		<bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>4320	</reg32>4321 4322	<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>4323	<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>4324 4325	<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>4326 4327	<reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">4328		<bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>4329	</reg32>4330 4331	<!-- New in a6xx gen3+ -->4332	<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">4333		<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>4334	</reg32>4335 4336	<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">4337		<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>4338	</reg32>4339	<!-- 0x980b-0x983f invalid -->4340 4341	<!-- 0x9840 - 0x9842 are not readable -->4342	<reg32 offset="0x9840" name="PC_DRAW_CMD">4343		<bitfield name="STATE_ID" low="0" high="7"/>4344	</reg32>4345 4346	<reg32 offset="0x9841" name="PC_DISPATCH_CMD">4347		<bitfield name="STATE_ID" low="0" high="7"/>4348	</reg32>4349 4350	<reg32 offset="0x9842" name="PC_EVENT_CMD">4351		<!-- I think only the low bit is actually used? -->4352		<bitfield name="STATE_ID" low="16" high="23"/>4353		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>4354	</reg32>4355 4356	<!--4357		0x9880 written in a lot of places by SQE, same value gets written4358		to control reg 0x12a.  Set by CP_SET_MARKER, so lets name it after4359		that4360	 -->4361	<reg32 offset="0x9880" name="PC_MARKER"/>4362 4363	<!-- 0x9843-0x997f invalid -->4364 4365	<reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit">4366		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>4367	</reg32>4368	<reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">4369		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>4370	</reg32>4371 4372	<reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit">4373		<!-- which stream to send to GRAS -->4374		<bitfield name="STREAM" low="0" high="1" type="uint"/>4375		<!-- discard primitives before rasterization -->4376		<bitfield name="DISCARD" pos="2" type="boolean"/>4377	</reg32>4378	<!-- VPC_RASTER_CNTL -->4379	<reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">4380		<!-- which stream to send to GRAS -->4381		<bitfield name="STREAM" low="0" high="1" type="uint"/>4382		<!-- discard primitives before rasterization -->4383		<bitfield name="DISCARD" pos="2" type="boolean"/>4384	</reg32>4385	<reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">4386		<!-- which stream to send to GRAS -->4387		<bitfield name="STREAM" low="0" high="1" type="uint"/>4388		<!-- discard primitives before rasterization -->4389		<bitfield name="DISCARD" pos="2" type="boolean"/>4390	</reg32>4391 4392	<!-- Both are a750+.4393	     Probably needed to correctly overlap execution of several draws.4394	-->4395	<reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>4396	<!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of4397	     this additional space is not known.4398	-->4399	<reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>4400 4401	<!-- 0x9982-0x9aff invalid -->4402 4403	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>4404 4405	<bitset name="a6xx_xs_out_cntl" inline="yes">4406		<doc>4407			num of varyings plus four for gl_Position (plus one if gl_PointSize)4408			plus # of transform-feedback (streamout) varyings if using the4409			hw streamout (rather than stg instructions in shader)4410		</doc>4411		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>4412		<bitfield name="PSIZE" pos="8" type="boolean"/>4413		<bitfield name="LAYER" pos="9" type="boolean"/>4414		<bitfield name="VIEW" pos="10" type="boolean"/>4415		<!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->4416		<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>4417		<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>4418		<bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>4419	</bitset>4420 4421	<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>4422	<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>4423	<!-- since HS can't output anything, only PRIMITIVE_ID is valid -->4424	<reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>4425	<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>4426 4427	<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/>4428 4429	<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">4430		<doc>4431		  size in vec4s of per-primitive storage for gs. TODO: not actually in VPC4432		</doc>4433		<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>4434	</reg32>4435 4436	<reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>4437	<!-- mask of enabled views, doesn't exist on A630 -->4438	<reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>4439	<!-- 0x9b09-0x9bff invalid -->4440	<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">4441		<!-- special register (but note first 8 bits can be written/read) -->4442		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>4443		<bitfield name="STATE_ID" low="8" high="15"/>4444	</reg32>4445	<!-- 0x9c01-0x9dff invalid -->4446	<!-- TODO: 0x9e00-0xa000 range incomplete -->4447	<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>4448	<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>4449	<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>4450	<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>4451	<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>4452	<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/>4453	<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/>4454 4455	<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">4456		<doc>4457			Possibly not really "initiating" the draw but the layout is similar4458			to VGT_DRAW_INITIATOR on older gens4459		</doc>4460	</reg32>4461	<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>4462	<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>4463 4464	<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->4465	<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">4466		<bitfield name="UNK0" low="0" high="15"/>4467		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>4468		<bitfield name="VSC_N" low="22" high="26" type="uint"/>4469	</reg32>4470	<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>4471	<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>4472 4473	<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">4474		<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>4475		<bitfield name="OVERRIDE" pos="0" type="boolean"/>4476	</reg32>4477 4478	<reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>4479 4480	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>4481	<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>4482 4483	<!-- always 0x0 -->4484	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>4485 4486	<reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit">4487		<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>4488		<bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>4489	</reg32>4490	<reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit">4491		<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>4492		<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>4493		<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>4494		<!-- only used for VS in non-multi-position-output case -->4495		<bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>4496	</reg32>4497	<reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit">4498		<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">4499			<doc>4500				This is the ID of the current patch within the4501				subdraw, used to calculate the offset of the4502				patch within the HS->DS buffers. When a draw is4503				split into multiple subdraws then this differs4504				from gl_PrimitiveID on the second, third, etc.4505				subdraws.4506			</doc>4507		</bitfield>4508		<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>4509	</reg32>4510	<reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit">4511		<bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>4512		<bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>4513		<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>4514		<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>4515	</reg32>4516	<reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit">4517		<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>4518	</reg32>4519	<reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit">4520		<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>4521		<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>4522	</reg32>4523	<reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">4524		<!--4525			True if gl_PrimitiveID is read via the FS4526		-->4527		<bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>4528	</reg32>4529 4530	<reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">4531		<bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>4532	</reg32>4533 4534	<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>4535	<reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd">4536		<!-- add VFD_INDEX_OFFSET to REGID4VTX -->4537		<bitfield name="VERTEX" pos="0" type="boolean"/>4538		<!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->4539		<bitfield name="INSTANCE" pos="1" type="boolean"/>4540	</reg32>4541 4542	<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/>4543	<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/>4544	<array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit">4545		<reg64 offset="0x0" name="BASE" type="address" align="1"/>4546		<reg32 offset="0x2" name="SIZE" type="uint"/>4547		<reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>4548	</array>4549	<array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit">4550		<reg32 offset="0x0" name="INSTR">4551			<!-- IDX and byte OFFSET into VFD_FETCH -->4552			<bitfield name="IDX" low="0" high="4" type="uint"/>4553			<bitfield name="OFFSET" low="5" high="16"/>4554			<bitfield name="INSTANCED" pos="17" type="boolean"/>4555			<bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>4556			<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>4557			<bitfield name="UNK30" pos="30" type="boolean"/>4558			<bitfield name="FLOAT" pos="31" type="boolean"/>4559		</reg32>4560		<reg32 offset="0x1" name="STEP_RATE" type="uint"/>4561	</array>4562	<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit">4563		<reg32 offset="0x0" name="INSTR">4564			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>4565			<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>4566		</reg32>4567	</array>4568 4569	<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>4570 4571	<reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>4572 4573	<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>4574	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>4575	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>4576 4577	<!--4578	Note: this seems to always be paired with another bit in another4579	block.4580	-->4581	<enum name="a6xx_threadsize">4582		<value value="0" name="THREAD64"/>4583		<value value="1" name="THREAD128"/>4584	</enum>4585 4586	<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">4587		<!-- if set to SINGLE, only use 1 concurrent wave on each SP -->4588		<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>4589		<!--4590		When b31 set we just see FULLREGFOOTPRINT set.  The pattern of4591		used registers is a bit odd too:4592			- used (half): 0-15 68-179 (cnt=128, max=179)4593			- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>4594		whereas we usually see a (mostly) contiguous range of regs used.  But if4595		I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),4596		then:4597			- used (merged): 0-191 (cnt=192, max=191)4598		So I think if b31 is set, then the half precision registers overlap4599		the full precision registers.  (Which seems like a pretty sensible4600		feature, actually I'm not sure when you *wouldn't* want to use that,4601		since it gives register allocation more flexibility)4602		 -->4603		<bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>4604		<bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>4605		<!-- could it be a low bit of branchstack? -->4606		<bitfield name="UNK13" pos="13" type="boolean"/>4607		<!-- seems to be nesting level for flow control:.. -->4608		<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>4609	</bitset>4610 4611	<bitset name="a6xx_sp_xs_config" inline="yes">4612		<!--4613		Each of these are set if the given resource type is used4614		with the Vulkan/bindless binding model.4615		-->4616		<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>4617		<bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>4618		<bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>4619		<bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>4620 4621		<bitfield name="ENABLED" pos="8" type="boolean"/>4622		<!--4623		number of textures and samplers.. these might be swapped, with GL I4624		always see the same value for both.4625		 -->4626		<bitfield name="NTEX" low="9" high="16" type="uint"/>4627		<bitfield name="NSAMP" low="17" high="21" type="uint"/>4628		<bitfield name="NIBO" low="22" high="28" type="uint"/>4629	</bitset>4630 4631	<bitset name="a6xx_sp_xs_prim_cntl" inline="yes">4632		<!-- # of VS outputs including pos/psize -->4633		<bitfield name="OUT" low="0" high="5" type="uint"/>4634		<!-- FLAGS_REGID only for GS -->4635		<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>4636	</bitset>4637 4638	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">4639		<!--4640		This field actually controls all geometry stages. TCS, TES, and4641		GS must have the same mergedregs setting as VS.4642		-->4643		<bitfield name="MERGEDREGS" pos="20" type="boolean"/>4644		<!--4645		Creates a separate preamble-only thread?4646 4647		Early preamble has the following limitations:4648		- Only shared, a1, and consts regs could be used4649		  (accessing other regs would result in GPU fault);4650		- No cat5/cat6, only stc/ldc variants are working;4651		- Values writen to shared regs are not accessible by the rest4652		  of the shader;4653		- Instructions before shps are also considered to be a part of4654		  early preamble;4655 4656		Note, for all shaders from d3d11 games blob produced preambles4657		compatible with early preamble mode.4658		-->4659		<bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/>4660	</reg32>4661	<!-- bitmask of true/false conditions for VS brac.N instructions,4662	     bit N corresponds to brac.N -->4663	<reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>4664	<!-- # of VS outputs including pos/psize -->4665	<reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>4666	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit">4667		<reg32 offset="0x0" name="REG">4668			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>4669			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>4670			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>4671			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>4672		</reg32>4673	</array>4674	<!--4675	Starting with a5xx, position/psize outputs from shader end up in the4676	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are4677	the last entries too, except when gl_PointCoord is used, blob inserts4678	an extra varying after, but with a lower OUTLOC position.  If present,4679	psize is last, preceded by position.4680	 -->4681	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit">4682		<reg32 offset="0x0" name="REG">4683			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>4684			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>4685			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>4686			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>4687		</reg32>4688	</array>4689 4690	<bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">4691		<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">4692			<doc>The size of memory that ldp/stp can address.</doc>4693		</bitfield>4694		<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">4695                        <doc>4696				Seems to be the same as a3xx. The maximum stack4697				size in units of 4 calls, so a call depth of 74698				would result in a value of 2.4699				TODO: What's the actual size per call, i.e. the4700				size of the PC? a3xx docs say it's 16 bits4701				there, but the length register now takes 28 bits4702				so it's probably been bumped to 32 bits.4703                        </doc>4704		</bitfield>4705	</bitset>4706 4707	<bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">4708		<bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>4709		<bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">4710			<doc>4711				There are four indices used to compute the4712				private memory location for an access:4713 4714				- stp/ldp offset4715				- fiber id4716				- wavefront id (a swizzled version of what "getwid" returns)4717				- SP ID (the same as what "getspid" returns)4718 4719				The stride for the SP ID is always set by4720				TOTALPVTMEMSIZE. In the per-wave layout, the4721				indices are used in this order:4722 4723				- offset % 4 (offset within dword)4724				- fiber id4725				- offset / 44726				- wavefront id4727				- SP ID4728 4729				and the stride for the wavefront ID is4730				MEMSIZEPERITEM, multiplied by 128 (fibers per4731				wavefront). In the per-fiber layout, the indices4732				are used in this order:4733 4734				- offset4735				- fiber id % 44736				- wavefront id4737				- fiber id / 44738				- SP ID4739 4740				and the stride for the fiber id/wavefront id4741				combo is MEMSIZEPERITEM.4742 4743				Note: Accesses of more than 1 dword do not work4744				with per-fiber layout. The blob will fall back4745				to per-wave instead.4746			</doc>4747		</bitfield>4748	</bitset>4749 4750	<bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">4751		<doc>4752			This seems to be be the equivalent of HWSTACKOFFSET in4753			a3xx. The ldp/stp offset formula above isn't affected by4754			HWSTACKSIZEPERTHREAD at all, so the HW return address4755			stack seems to be after all the normal per-SP private4756			memory.4757		</doc>4758		<bitfield name="OFFSET" low="0" high="18" shr="11"/>4759	</bitset>4760 4761	<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>4762	<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/>4763	<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>4764	<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>4765	<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>4766	<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>4767	<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>4768	<reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>4769	<reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>4770	<reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>4771 4772	<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">4773		<!-- There is no mergedregs bit, that comes from the VS. -->4774		<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>4775	</reg32>4776	<!--4777	Total size of local storage in dwords divided by the wave size.4778	The maximum value is 64. With the wave size being always 64 for HS,4779	the maximum size of local storage should be:4780	 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k4781	-->4782	<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>4783	<reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/>4784 4785	<!-- TODO: exact same layout as 0xa81b-0xa825 -->4786	<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>4787	<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/>4788	<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>4789	<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>4790	<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>4791	<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>4792	<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>4793	<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>4794	<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>4795	<reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>4796 4797	<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">4798		<!-- There is no mergedregs bit, that comes from the VS. -->4799		<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>4800	</reg32>4801	<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>4802 4803	<!-- TODO: exact same layout as 0xa802-0xa81a -->4804	<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>4805	<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit">4806		<reg32 offset="0x0" name="REG">4807			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>4808			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>4809			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>4810			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>4811		</reg32>4812	</array>4813	<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit">4814		<reg32 offset="0x0" name="REG">4815			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>4816			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>4817			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>4818			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>4819		</reg32>4820	</array>4821 4822	<!-- TODO: exact same layout as 0xa81b-0xa825 -->4823	<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>4824	<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/>4825	<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>4826	<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>4827	<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>4828	<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>4829	<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>4830	<reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>4831	<reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>4832	<reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>4833 4834	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">4835		<!-- There is no mergedregs bit, that comes from the VS. -->4836		<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>4837	</reg32>4838	<reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">4839		<doc>4840			Normally the size of the output of the last stage in4841			dwords. It should be programmed as follows:4842 4843			size less than 63    - size4844			size of 63 (?) or 64 - 634845			size greater than 64 - 644846 4847			What to program when the size is 61-63 is a guess, but4848			both the blob and ir3 align the size to 4 dword's so it4849			doesn't matter in practice.4850		</doc>4851	</reg32>4852	<reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/>4853 4854	<!-- TODO: exact same layout as 0xa802-0xa81a -->4855	<reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>4856	<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit">4857		<reg32 offset="0x0" name="REG">4858			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>4859			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>4860			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>4861			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>4862		</reg32>4863	</array>4864 4865	<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit">4866		<reg32 offset="0x0" name="REG">4867			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>4868			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>4869			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>4870			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>4871		</reg32>4872	</array>4873 4874	<!-- TODO: exact same layout as 0xa81b-0xa825 -->4875	<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>4876	<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/>4877	<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>4878	<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>4879	<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>4880	<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>4881	<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>4882	<reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>4883	<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>4884	<reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>4885 4886	<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/>4887	<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/>4888	<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/>4889	<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/>4890	<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/>4891	<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/>4892	<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/>4893	<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/>4894 4895	<!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->4896 4897	<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">4898		<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>4899		<bitfield name="UNK21" pos="21" type="boolean"/>4900		<bitfield name="VARYING" pos="22" type="boolean"/>4901		<bitfield name="LODPIXMASK" pos="23" type="boolean">4902			<doc>4903				Enable ALL helper invocations in a quad. Necessary for4904				fine derivatives and quad subgroup ops.4905			</doc>4906		</bitfield>4907		<!-- note: vk blob uses bit24 -->4908		<bitfield name="UNK24" pos="24" type="boolean"/>4909		<bitfield name="UNK25" pos="25" type="boolean"/>4910		<bitfield name="PIXLODENABLE" pos="26" type="boolean">4911			<doc>4912				Enable helper invocations. Enables 3 out of 4 fragments,4913				because the coarse derivatives only use half of the quad4914				and so one pixel's value is always unused.4915			</doc>4916		</bitfield>4917		<bitfield name="UNK27" pos="27" type="boolean"/>4918		<bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/>4919		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>4920	</reg32>4921	<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>4922	<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>4923	<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/>4924	<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>4925	<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>4926	<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>4927 4928	<reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">4929		<!-- per-mrt enable bit -->4930		<bitfield name="ENABLE_BLEND" low="0" high="7"/>4931		<bitfield name="UNK8" pos="8" type="boolean"/>4932		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>4933		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>4934	</reg32>4935	<reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">4936		<!-- Same as RB_SRGB_CNTL -->4937		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>4938		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>4939		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>4940		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>4941		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>4942		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>4943		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>4944		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>4945	</reg32>4946	<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit">4947		<bitfield name="RT0" low="0" high="3"/>4948		<bitfield name="RT1" low="4" high="7"/>4949		<bitfield name="RT2" low="8" high="11"/>4950		<bitfield name="RT3" low="12" high="15"/>4951		<bitfield name="RT4" low="16" high="19"/>4952		<bitfield name="RT5" low="20" high="23"/>4953		<bitfield name="RT6" low="24" high="27"/>4954		<bitfield name="RT7" low="28" high="31"/>4955	</reg32>4956	<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit">4957		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>4958		<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>4959		<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>4960		<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>4961	</reg32>4962	<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit">4963		<bitfield name="MRT" low="0" high="3" type="uint"/>4964	</reg32>4965 4966	<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit">4967		<doc>per MRT</doc>4968		<reg32 offset="0x0" name="REG">4969			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>4970			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>4971		</reg32>4972	</array>4973 4974	<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit">4975		<reg32 offset="0" name="REG">4976			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>4977			<bitfield name="COLOR_SINT" pos="8" type="boolean"/>4978			<bitfield name="COLOR_UINT" pos="9" type="boolean"/>4979			<bitfield name="UNK10" pos="10" type="boolean"/>4980		</reg32>4981	</array>4982 4983	<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit">4984		<bitfield name="COUNT" low="0" high="2" type="uint"/>4985		<bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>4986		<doc>4987			Similar to "(eq)" flag but disables helper invocations4988			after the texture prefetch.4989		</doc>4990		<bitfield name="ENDOFQUAD" pos="4" type="boolean" />4991		<doc>4992			Bypass writing to regs and overwrite output with color from4993			CONSTSLOTID const regs.4994		</doc>4995		<bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>4996		<bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>4997		<!-- Blob never uses it -->4998		<bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>4999	</reg32>5000	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">5001		<reg32 offset="0" name="CMD" variants="A6XX">5002			<bitfield name="SRC" low="0" high="6" type="uint"/>5003			<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>5004			<bitfield name="TEX_ID" low="11" high="15" type="uint"/>5005			<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>5006			<bitfield name="WRMASK" low="22" high="25" type="hex"/>5007			<bitfield name="HALF" pos="26" type="boolean"/>5008			<doc>Results in color being zero</doc>5009			<bitfield name="UNK27" pos="27" type="boolean"/>5010			<bitfield name="BINDLESS" pos="28" type="boolean"/>5011			<bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>5012		</reg32>5013	</array>5014	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit">5015		<reg32 offset="0" name="CMD" variants="A7XX-">5016			<bitfield name="SRC" low="0" high="6" type="uint"/>5017			<bitfield name="SAMP_ID" low="7" high="9" type="uint"/>5018			<bitfield name="TEX_ID" low="10" high="12" type="uint"/>5019			<bitfield name="DST" low="13" high="18" type="a3xx_regid"/>5020			<bitfield name="WRMASK" low="19" high="22" type="hex"/>5021			<bitfield name="HALF" pos="23" type="boolean"/>5022			<bitfield name="BINDLESS" pos="25" type="boolean"/>5023			<bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>5024		</reg32>5025	</array>5026	<array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit">5027		<reg32 offset="0" name="CMD">5028			<bitfield name="SAMP_ID" low="0" high="15" type="uint"/>5029			<bitfield name="TEX_ID" low="16" high="31" type="uint"/>5030		</reg32>5031	</array>5032	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>5033	<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->5034	<reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>5035 5036	<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->5037 5038 5039 5040 5041	<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd">5042		<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>5043		<!-- seems to make SP use less concurrent threads when possible? -->5044		<bitfield name="UNK21" pos="21" type="boolean"/>5045		<!-- has a small impact on performance, not clear what it does -->5046		<bitfield name="UNK22" pos="22" type="boolean"/>5047		<bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/>5048		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>5049	</reg32>5050 5051	<!-- set for compute shaders -->5052	<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd">5053		<bitfield name="SHARED_SIZE" low="0" high="4" type="uint">5054			<doc>5055				If 0 - all 32k of shared storage is enabled, otherwise5056				(SHARED_SIZE + 1) * 1k is enabled.5057				The ldl/stl offset seems to be rewritten to 0 when it is beyond5058				this limit. This is different from ldlw/stlw, which wraps at5059				64k (and has 36k of storage on A640 - reads between 36k-64k5060				always return 0)5061			</doc>5062		</bitfield>5063		<bitfield name="UNK5" pos="5" type="boolean"/>5064		<!-- always 1 ? -->5065		<bitfield name="UNK6" pos="6" type="boolean"/>5066	</reg32>5067	<reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/>5068	<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/>5069	<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/>5070	<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/>5071	<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/>5072	<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/>5073	<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>5074	<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>5075	<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>5076	<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/>5077	<reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>5078	<reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>5079 5080	<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->5081	<reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd">5082		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>5083		<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>5084		<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>5085		<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>5086	</reg32>5087	<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->5088	<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd">5089		<!-- gl_LocalInvocationIndex -->5090		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>5091		<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only5092		     one of those 6 "SP cores" -->5093		<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>5094		<!-- Must match SP_CS_CTRL -->5095		<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>5096		<!-- 1 thread per wave (ignored if bit9 set) -->5097		<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>5098	</reg32>5099 5100	<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">5101		<!-- gl_LocalInvocationIndex -->5102		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>5103		<!-- Must match SP_CS_CTRL -->5104		<bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/>5105		<!-- 1 thread per wave (would hang if THREAD128 is also set) -->5106		<bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/>5107 5108		<!-- Affects getone. If enabled, getone sometimes executed 1? less times5109		     than there are subgroups.5110		 -->5111		<bitfield name="UNK15" pos="15" type="boolean"/>5112	</reg32>5113 5114	<!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->5115 5116	<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/>5117	<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/>5118	<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/>5119	<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/>5120 5121	<enum name="a6xx_bindless_descriptor_size">5122		<doc>5123			This can alternatively be interpreted as a pitch shift, ie, the5124			descriptor size is 2 &lt;&lt; N dwords5125		</doc>5126		<value value="1" name="BINDLESS_DESCRIPTOR_16B"/>5127		<value value="3" name="BINDLESS_DESCRIPTOR_64B"/>5128	</enum>5129 5130	<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">5131		<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">5132			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5133			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5134		</reg64>5135	</array>5136	<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd">5137		<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">5138			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5139			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5140		</reg64>5141	</array>5142 5143	<!--5144	IBO state for compute shader:5145	 -->5146	<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>5147	<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>5148 5149	<!-- Correlated with avgs/uvgs usage in FS -->5150	<reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>5151 5152	<reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">5153		<bitfield name="ENABLED" pos="0" type="boolean"/>5154	</reg32>5155	<reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">5156		<doc>5157			Specify for which components the output color should be read5158			from alias, e.g. for:5159 5160				alias.1.b32.0 r3.x, c8.x5161				alias.1.b32.0 r2.x, c4.x5162				alias.1.b32.0 r1.x, c4.x5163				alias.1.b32.0 r0.x, c0.x5164 5165			the SP_PS_ALIASED_COMPONENTS would be 0x000011115166		</doc>5167 5168		<bitfield name="RT0" low="0" high="3"/>5169		<bitfield name="RT1" low="4" high="7"/>5170		<bitfield name="RT2" low="8" high="11"/>5171		<bitfield name="RT3" low="12" high="15"/>5172		<bitfield name="RT4" low="16" high="19"/>5173		<bitfield name="RT5" low="20" high="23"/>5174		<bitfield name="RT6" low="24" high="27"/>5175		<bitfield name="RT7" low="28" high="31"/>5176	</reg32>5177 5178	<reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>5179 5180	<!--5181                This enum is probably similar in purpose to SNORMMODE on a3xx,5182                minus the snorm stuff, i.e. it controls what happens with an5183                out-of-bounds isam/isamm. GL and Vulkan robustness require us to5184                return 0 on out-of-bound textureFetch().5185	-->5186	<enum name="a6xx_isam_mode">5187		<value value="0x1" name="ISAMMODE_CL"/>5188		<value value="0x2" name="ISAMMODE_GL"/>5189	</enum>5190 5191	<reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit">5192	  <!--5193	  When set, half register loads from the constant file will5194	  load a 32-bit value (so hc0.y loads the same value as c0.y)5195	  and implicitly convert it to 16b (f2f16, or u2u16, based on5196	  operand type).  When unset, half register loads from the5197	  constant file will load 16 bits from the packed constant5198	  file (so hc0.y loads the top 16 bits of the value of c0.x)5199	  -->5200		<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>5201		<bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>5202		<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->5203	</reg32>5204 5205	<reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>5206	<reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>5207 5208	<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>5209	<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>5210 5211	<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">5212		<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">5213			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5214			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5215		</reg64>5216	</array>5217	<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit">5218		<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">5219			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5220			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5221		</reg64>5222	</array>5223 5224	<!--5225	Combined IBO state for 3d pipe, used for Image and SSBO write/atomic5226	instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.5227	 -->5228	<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>5229	<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>5230 5231	<reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>5232 5233	<bitset name="a6xx_sp_2d_dst_format" inline="yes">5234		<bitfield name="NORM" pos="0" type="boolean"/>5235		<bitfield name="SINT" pos="1" type="boolean"/>5236		<bitfield name="UINT" pos="2" type="boolean"/>5237		<!-- looks like HW only cares about the base type of this format,5238		     which matches the ifmt? -->5239		<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>5240		<!-- set when ifmt is R2D_UNORM8_SRGB -->5241		<bitfield name="SRGB" pos="11" type="boolean"/>5242		<!-- some sort of channel mask, not sure what it is for -->5243		<bitfield name="MASK" low="12" high="15"/>5244	</bitset>5245 5246	<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/>5247	<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/>5248 5249	<reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>5250	<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>5251	<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">5252		<!-- TODO: valid bits 0x3c3f, see kernel -->5253	</reg32>5254	<reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>5255	<reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd">5256		<bitfield name="F16_NO_INF" pos="3" type="boolean"/>5257	</reg32>5258 5259	<reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>5260	<reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>5261	<reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>5262	<reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>5263 5264	<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd">5265		<!-- some perfcntrs are affected by a per-stage enable bit5266		     (PERF_SP_ALU_WORKING_CYCLES for example)5267		     TODO: verify position of HS/DS/GS bits -->5268		<bitfield name="VS" pos="0" type="boolean"/>5269		<bitfield name="HS" pos="1" type="boolean"/>5270		<bitfield name="DS" pos="2" type="boolean"/>5271		<bitfield name="GS" pos="3" type="boolean"/>5272		<bitfield name="FS" pos="4" type="boolean"/>5273		<bitfield name="CS" pos="5" type="boolean"/>5274	</reg32>5275	<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>5276	<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>5277	<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>5278	<reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>5279	<reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>5280	<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">5281		<bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>5282		<bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>5283		<bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>5284		<bitfield name="USPTP" low="4" high="7"/>5285		<bitfield name="SPTP" low="0" high="3"/>5286	</reg32>5287	<reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>5288	<reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>5289	<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>5290	<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->5291	<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->5292	<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>5293 5294	<!--5295	The downstream kernel calls the debug cluster of registers5296	"a6xx_sp_ps_tp_cluster" but this actually specifies the border5297	color base for compute shaders.5298	-->5299	<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>5300	<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>5301	<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>5302 5303	<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>5304	<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>5305 5306	<!-- could be all the stuff below here is actually TPL1?? -->5307 5308	<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit">5309		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>5310		<bitfield name="UNK2" low="2" high="3"/>5311	</reg32>5312	<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit">5313		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>5314		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>5315	</reg32>5316 5317	<!-- looks to work in the same way as a5xx: -->5318	<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>5319	<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>5320	<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>5321	<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>5322	<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>5323	<reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd">5324		<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>5325		<bitfield name="UNK3" low="2" high="7"/>5326	</reg32>5327	<reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>5328 5329	<!--5330	Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either5331	badly named or the functionality moved in a6xx.  But downstream kernel5332	calls this "a6xx_sp_ps_tp_2d_cluster"5333	 -->5334	<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A6XX" usage="rp_blit"/>5335	<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit">5336		<bitfield name="WIDTH" low="0" high="14" type="uint"/>5337		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>5338	</reg32>5339	<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/>5340	<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit">5341		<bitfield name="UNK0" low="0" high="8"/>5342		<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>5343	</reg32>5344 5345	<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usage="rp_blit"/>5346	<reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX">5347		<bitfield name="WIDTH" low="0" high="14" type="uint"/>5348		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>5349	</reg32>5350	<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/>5351	<reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX">5352		<bitfield name="UNK0" low="0" high="8"/>5353		<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>5354	</reg32>5355 5356	<!-- planes for NV12, etc. (TODO: not tested) -->5357	<reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/>5358	<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/>5359	<reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/>5360 5361	<reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>5362	<reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>5363	<reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>5364 5365	<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/>5366	<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/>5367 5368	<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/>5369	<reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>5370 5371	<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>5372	<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>5373	<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>5374	<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>5375	<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/>5376 5377	<reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>5378	<reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>5379	<reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>5380	<reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>5381	<reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/>5382	<reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>5383	<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/>5384 5385	<!-- always 0x100000 or 0x1000000? -->5386	<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>5387	<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>5388	<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd">5389		<!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set5390		     and if other blit is done without it - UBWC image may be copied incorrectly.5391		 -->5392		<bitfield name="TP_UBWC_FLAG_HINT" pos="18" type="boolean"/>5393	</reg32>5394	<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">5395		<bitfield name="MODE" pos="0" type="boolean"/>5396		<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>5397		<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->5398		<bitfield name="UPPER_BIT" pos="4" type="uint"/>5399		<bitfield name="UNK6" low="6" high="7"/>5400	</reg32>5401	<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->5402 5403	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>5404	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>5405	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>5406	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>5407	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>5408 5409	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/>5410	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/>5411	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/>5412	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/>5413	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/>5414 5415	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/>5416	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/>5417 5418	<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->5419 5420	<bitset name="a6xx_hlsq_xs_cntl" inline="yes">5421		<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>5422		<bitfield name="ENABLED" pos="8" type="boolean"/>5423		<bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>5424	</bitset>5425 5426	<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>5427	<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>5428	<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>5429	<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>5430 5431	<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>5432	<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>5433	<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>5434	<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>5435 5436	<reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">5437		<!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->5438		<bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>5439	</reg32>5440 5441	<!-- Always 0 -->5442	<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>5443 5444	<!-- Used in VK_KHR_fragment_shading_rate -->5445	<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>5446 5447	<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">5448		<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>5449		<!-- UNK8 is set on a730/a740 -->5450		<bitfield name="UNK8" pos="8" type="boolean"/>5451		<!-- UNK9 is set on a750 -->5452		<bitfield name="UNK9" pos="9" type="boolean"/>5453	</reg32>5454 5455	<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>5456	<reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>5457	<reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>5458 5459 5460	<bitset name="a6xx_hlsq_fs_cntl_0" inline="yes">5461		<!-- must match SP_FS_CTRL -->5462		<bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>5463		<bitfield name="VARYINGS" pos="1" type="boolean"/>5464		<bitfield name="UNK2" low="2" high="11"/>5465	</bitset>5466	<bitset name="a6xx_hlsq_control_3_reg" inline="yes">5467		<!-- register loaded with position (bary.f) -->5468		<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>5469		<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>5470		<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>5471		<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>5472	</bitset>5473	<bitset name="a6xx_hlsq_control_4_reg" inline="yes">5474		<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>5475		<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>5476		<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>5477		<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>5478	</bitset>5479	<bitset name="a6xx_hlsq_control_5_reg" inline="yes">5480		<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>5481		<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>5482	</bitset>5483 5484	<reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/>5485	<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->5486	<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">5487		<!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the5488				 A3xx field, except that it's not necessary to set it to anything but the maximum, since5489				 the hardware will simply emit smaller waves when it runs out of space.	-->5490		<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>5491	</reg32>5492	<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit">5493		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>5494		<!-- SAMPLEID is loaded into a half-precision register: -->5495		<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>5496		<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>5497		<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>5498	</reg32>5499	<reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/>5500	<reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/>5501	<reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/>5502	<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/>5503	<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/>5504	<reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">5505			<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>5506	</reg32>5507	<reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">5508		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>5509		<!-- SAMPLEID is loaded into a half-precision register: -->5510		<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>5511		<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>5512		<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>5513	</reg32>5514	<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/>5515	<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/>5516	<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/>5517	<reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>5518 5519	<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->5520	<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit">5521		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>5522		<!-- localsize is value minus one: -->5523		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>5524		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>5525		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>5526	</reg32>5527	<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit">5528		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>5529	</reg32>5530	<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit">5531		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>5532	</reg32>5533	<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit">5534		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>5535	</reg32>5536	<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit">5537		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>5538	</reg32>5539	<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit">5540		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>5541	</reg32>5542	<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit">5543		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>5544	</reg32>5545	<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit">5546		<!-- these are all vec3. first 3 need to be high regs5547		     WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)5548		     WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID5549		-->5550		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>5551		<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>5552		<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>5553		<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>5554	</reg32>5555	<reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit">5556		<!-- gl_LocalInvocationIndex -->5557		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>5558		<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only5559		     one of those 6 "SP cores" -->5560		<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>5561		<!-- Must match SP_CS_CTRL -->5562		<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>5563		<!-- 1 thread per wave (ignored if bit9 set) -->5564		<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>5565	</reg32>5566	<!--note: vulkan blob doesn't use these -->5567	<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/>5568	<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/>5569	<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/>5570 5571	<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->5572	<reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">5573		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>5574		<!-- localsize is value minus one: -->5575		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>5576		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>5577		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>5578	</reg32>5579	<reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">5580		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>5581	</reg32>5582	<reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">5583		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>5584	</reg32>5585	<reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">5586		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>5587	</reg32>5588	<reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">5589		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>5590	</reg32>5591	<reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">5592		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>5593	</reg32>5594	<reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">5595		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>5596	</reg32>5597	<!--note: vulkan blob doesn't use these -->5598	<reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>5599	<reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>5600	<reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>5601 5602	<enum name="a7xx_cs_yalign">5603		<value name="CS_YALIGN_1" value="8"/>5604		<value name="CS_YALIGN_2" value="4"/>5605		<value name="CS_YALIGN_4" value="2"/>5606		<value name="CS_YALIGN_8" value="1"/>5607	</enum>5608 5609	<reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">5610		<!-- gl_LocalInvocationIndex -->5611		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>5612		<!-- Must match SP_CS_CTRL -->5613		<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>5614		<bitfield name="UNK11" pos="11" type="boolean"/>5615		<bitfield name="UNK22" pos="22" type="boolean"/>5616		<bitfield name="UNK26" pos="26" type="boolean"/>5617		<bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>5618	</reg32>5619 5620	<reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">5621		<!-- localsize is value minus one: -->5622		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>5623		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>5624		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>5625	</reg32>5626 5627	<reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>5628	<reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>5629	<reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>5630 5631	<!-- mirror of SP_CS_BINDLESS_BASE -->5632	<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">5633		<reg64 offset="0" name="DESCRIPTOR">5634			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5635			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5636		</reg64>5637	</array>5638 5639	<!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->5640	<reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd">5641		<bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>5642		<bitfield name="UNK5" pos="5" type="boolean"/>5643		<!-- always 1 ? -->5644		<bitfield name="UNK6" pos="6" type="boolean"/>5645	</reg32>5646 5647	<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD" variants="A6XX">5648		<bitfield name="STATE_ID" low="0" high="7"/>5649	</reg32>5650 5651	<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD" variants="A6XX">5652		<bitfield name="STATE_ID" low="0" high="7"/>5653	</reg32>5654 5655	<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD" variants="A6XX">5656		<!-- I think only the low bit is actually used? -->5657		<bitfield name="STATE_ID" low="16" high="23"/>5658		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>5659	</reg32>5660 5661	<reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd">5662		<doc>5663			This register clears pending loads queued up by5664			CP_LOAD_STATE6. Each bit resets a particular kind(s) of5665			CP_LOAD_STATE6.5666		</doc>5667 5668		<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->5669		<bitfield name="VS_STATE" pos="0" type="boolean"/>5670		<bitfield name="HS_STATE" pos="1" type="boolean"/>5671		<bitfield name="DS_STATE" pos="2" type="boolean"/>5672		<bitfield name="GS_STATE" pos="3" type="boolean"/>5673		<bitfield name="FS_STATE" pos="4" type="boolean"/>5674		<bitfield name="CS_STATE" pos="5" type="boolean"/>5675 5676		<bitfield name="CS_IBO" pos="6" type="boolean"/>5677		<bitfield name="GFX_IBO" pos="7" type="boolean"/>5678 5679		<!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->5680		<bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>5681		<bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>5682 5683		<!-- SS6_BINDLESS: one bit per bindless base -->5684		<bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>5685		<bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>5686	</reg32>5687 5688	<reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">5689		<bitfield name="STATE_ID" low="0" high="7"/>5690	</reg32>5691 5692	<reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">5693		<bitfield name="STATE_ID" low="0" high="7"/>5694	</reg32>5695 5696	<reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">5697		<bitfield name="STATE_ID" low="16" high="23"/>5698		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>5699	</reg32>5700 5701	<reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">5702		<doc>5703			This register clears pending loads queued up by5704			CP_LOAD_STATE6. Each bit resets a particular kind(s) of5705			CP_LOAD_STATE6.5706		</doc>5707 5708		<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->5709		<bitfield name="VS_STATE" pos="0" type="boolean"/>5710		<bitfield name="HS_STATE" pos="1" type="boolean"/>5711		<bitfield name="DS_STATE" pos="2" type="boolean"/>5712		<bitfield name="GS_STATE" pos="3" type="boolean"/>5713		<bitfield name="FS_STATE" pos="4" type="boolean"/>5714		<bitfield name="CS_STATE" pos="5" type="boolean"/>5715 5716		<bitfield name="CS_IBO" pos="6" type="boolean"/>5717		<bitfield name="GFX_IBO" pos="7" type="boolean"/>5718 5719		<!-- SS6_BINDLESS: one bit per bindless base -->5720		<bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>5721		<bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>5722	</reg32>5723 5724	<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>5725	<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>5726 5727	<array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>5728 5729	<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">5730		<doc>5731			Shared constants are intended to be used for Vulkan push5732			constants. When enabled, 8 vec4's are reserved in the FS5733			const pool and 16 in the geometry const pool although5734			only 8 are actually used (why?) and they are mapped to5735			c504-c511 in each stage. Both VS and FS shared consts5736			are written using ST6_CONSTANTS/SB6_IBO, so that both5737			the geometry and FS shared consts can be written at once5738			by using CP_LOAD_STATE6 rather than5739			CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition5740			DST_OFF and NUM_UNIT are in units of dwords instead of5741			vec4's.5742 5743			There is also a separate shared constant pool for CS,5744			which is loaded through CP_LOAD_STATE6_FRAG with5745			ST6_UBO/ST6_IBO. However the only real difference for CS5746			is the dword units.5747		</doc>5748		<bitfield name="ENABLE" pos="0" type="boolean"/>5749	</reg32>5750 5751	<!-- mirror of SP_BINDLESS_BASE -->5752	<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">5753		<reg64 offset="0" name="DESCRIPTOR">5754			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>5755			<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>5756		</reg64>5757	</array>5758 5759	<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">5760		<bitfield name="STATE_ID" low="8" high="15"/>5761		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>5762	</reg32>5763 5764	<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->5765	<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>5766	<reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>5767	<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>5768	<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>5769	<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>5770 5771	<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->5772	<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>5773 5774	<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>5775 5776	<!-- Don't know if these are SP, always 0 -->5777	<reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>5778	<reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>5779	<reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>5780 5781	<!--5782		These special registers signal the beginning/end of an event5783		sequence. The sequence used internally for an event looks like:5784		- write EVENT_CMD pipe register5785		- write CP_EVENT_START5786		- write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD5787		- write PC_EVENT_CMD with event or PC_DRAW_CMD5788		- write HLSQ_EVENT_CMD(CONTEXT_DONE)5789		- write PC_EVENT_CMD(CONTEXT_DONE)5790		- write CP_EVENT_END5791		Writing to CP_EVENT_END seems to actually trigger the context roll5792	-->5793	<reg32 offset="0xd600" name="CP_EVENT_START">5794		<bitfield name="STATE_ID" low="0" high="7"/>5795	</reg32>5796	<reg32 offset="0xd601" name="CP_EVENT_END">5797		<bitfield name="STATE_ID" low="0" high="7"/>5798	</reg32>5799	<reg32 offset="0xd700" name="CP_2D_EVENT_START">5800		<bitfield name="STATE_ID" low="0" high="7"/>5801	</reg32>5802	<reg32 offset="0xd701" name="CP_2D_EVENT_END">5803		<bitfield name="STATE_ID" low="0" high="7"/>5804	</reg32>5805</domain>5806 5807<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->5808<domain name="A6XX_TEX_SAMP" width="32">5809	<doc>Texture sampler dwords</doc>5810	<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->5811		<value name="A6XX_TEX_NEAREST" value="0"/>5812		<value name="A6XX_TEX_LINEAR" value="1"/>5813		<value name="A6XX_TEX_ANISO" value="2"/>5814		<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->5815	</enum>5816	<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->5817		<value name="A6XX_TEX_REPEAT" value="0"/>5818		<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>5819		<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>5820		<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>5821		<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>5822	</enum>5823	<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->5824		<value name="A6XX_TEX_ANISO_1" value="0"/>5825		<value name="A6XX_TEX_ANISO_2" value="1"/>5826		<value name="A6XX_TEX_ANISO_4" value="2"/>5827		<value name="A6XX_TEX_ANISO_8" value="3"/>5828		<value name="A6XX_TEX_ANISO_16" value="4"/>5829	</enum>5830	<enum name="a6xx_reduction_mode">5831		<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>5832		<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>5833		<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>5834	</enum>5835 5836	<reg32 offset="0" name="0">5837		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>5838		<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>5839		<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>5840		<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>5841		<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>5842		<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>5843		<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>5844		<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->5845	</reg32>5846	<reg32 offset="1" name="1">5847		<bitfield name="CLAMPENABLE" pos="0" type="boolean">5848			<doc>5849				clamp result to [0, 1] if the format is unorm or5850				[-1, 1] if the format is snorm, *after*5851				filtering. Has no effect for other formats.5852			</doc>5853		</bitfield>5854		<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>5855		<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>5856		<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>5857		<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>5858		<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>5859		<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>5860	</reg32>5861	<reg32 offset="2" name="2">5862		<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>5863		<bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>5864		<bitfield name="BCOLOR" low="7" high="31"/>5865	</reg32>5866	<reg32 offset="3" name="3"/>5867</domain>5868 5869<domain name="A6XX_TEX_CONST" width="32" varset="chip">5870	<doc>Texture constant dwords</doc>5871	<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->5872		<value name="A6XX_TEX_X" value="0"/>5873		<value name="A6XX_TEX_Y" value="1"/>5874		<value name="A6XX_TEX_Z" value="2"/>5875		<value name="A6XX_TEX_W" value="3"/>5876		<value name="A6XX_TEX_ZERO" value="4"/>5877		<value name="A6XX_TEX_ONE" value="5"/>5878	</enum>5879	<enum name="a6xx_tex_type"> <!-- same as a4xx? -->5880		<value name="A6XX_TEX_1D" value="0"/>5881		<value name="A6XX_TEX_2D" value="1"/>5882		<value name="A6XX_TEX_CUBE" value="2"/>5883		<value name="A6XX_TEX_3D" value="3"/>5884		<value name="A6XX_TEX_BUFFER" value="4"/>5885	</enum>5886	<reg32 offset="0" name="0">5887		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>5888		<bitfield name="SRGB" pos="2" type="boolean"/>5889		<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>5890		<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>5891		<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>5892		<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>5893		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>5894		<!-- overlaps with MIPLVLS -->5895		<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>5896		<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>5897		<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>5898		<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>5899		<!--5900			Why is the swap needed in addition to SWIZ_*? The swap5901			is performed before border color replacement, while the5902			swizzle is applied after after it.5903		-->5904		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>5905	</reg32>5906	<reg32 offset="1" name="1">5907		<bitfield name="WIDTH" low="0" high="14" type="uint"/>5908		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>5909		<bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>5910	</reg32>5911	<reg32 offset="2" name="2">5912		<!--5913			These fields overlap PITCH, and are used instead of5914			PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.5915		 -->5916		<doc> probably for D3D structured UAVs, normally set to 1 </doc>5917		<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>5918		<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>5919 5920		<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->5921		<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>5922		<doc>Pitch in bytes (so actually stride)</doc>5923		<bitfield name="PITCH" low="7" high="28" type="uint"/>5924		<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>5925	</reg32>5926	<reg32 offset="3" name="3">5927		<!--5928		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and5929		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the5930		layer size at the point that it stops being reduced moving to5931		higher (smaller) mipmap levels5932		 -->5933		<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>5934		<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>5935		<!--5936		by default levels with w < 16 are linear5937		TILE_ALL makes all levels have tiling5938		seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)5939		 -->5940		<bitfield name="TILE_ALL" pos="27" type="boolean"/>5941		<bitfield name="FLAG" pos="28" type="boolean"/>5942	</reg32>5943	<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)5944	     the address of the non-flag base buffer is determined automatically,5945	     and must follow the flag buffer5946	 -->5947	<reg32 offset="4" name="4">5948		<bitfield name="BASE_LO" low="5" high="31" shr="5"/>5949	</reg32>5950	<reg32 offset="5" name="5">5951		<bitfield name="BASE_HI" low="0" high="16"/>5952		<bitfield name="DEPTH" low="17" high="29" type="uint"/>5953	</reg32>5954	<reg32 offset="6" name="6">5955		<!-- overlaps with PLANE_PITCH -->5956		<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>5957		<!-- pitch for plane 2 / plane 3 -->5958		<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>5959	</reg32>5960	<!-- 7/8 is plane 2 address for planar formats -->5961	<reg32 offset="7" name="7">5962		<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>5963	</reg32>5964	<reg32 offset="8" name="8">5965		<bitfield name="FLAG_HI" low="0" high="16"/>5966	</reg32>5967	<!-- 9/10 is plane 3 address for planar formats -->5968	<reg32 offset="9" name="9">5969		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>5970	</reg32>5971	<reg32 offset="10" name="10">5972		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>5973		<!-- log2 size of the first level, required for mipmapping -->5974		<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>5975		<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>5976	</reg32>5977	<reg32 offset="11" name="11"/>5978	<reg32 offset="12" name="12"/>5979	<reg32 offset="13" name="13"/>5980	<reg32 offset="14" name="14"/>5981	<reg32 offset="15" name="15"/>5982</domain>5983 5984<domain name="A6XX_UBO" width="32">5985	<reg32 offset="0" name="0">5986		<bitfield name="BASE_LO" low="0" high="31"/>5987	</reg32>5988	<reg32 offset="1" name="1">5989		<bitfield name="BASE_HI" low="0" high="16"/>5990		<bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->5991	</reg32>5992</domain>5993 5994<domain name="A6XX_PDC" width="32">5995	<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>5996	<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>5997	<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>5998	<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>5999	<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>6000	<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>6001	<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>6002	<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>6003	<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>6004	<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>6005	<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>6006	<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>6007	<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>6008	<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>6009	<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>6010	<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>6011	<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>6012	<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>6013	<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>6014	<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>6015	<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>6016	<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>6017	<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>6018	<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>6019	<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>6020	<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>6021</domain>6022 6023<domain name="A6XX_PDC_GPU_SEQ" width="32">6024	<reg32 offset="0x0" name="MEM_0"/>6025</domain>6026 6027<domain name="A6XX_CX_DBGC" width="32">6028	<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">6029		<bitfield high="7" low="0" name="PING_INDEX"/>6030		<bitfield high="15" low="8" name="PING_BLK_SEL"/>6031	</reg32>6032	<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>6033	<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>6034	<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>6035	<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">6036		<bitfield high="5" low="0" name="TRACEEN"/>6037		<bitfield high="14" low="12" name="GRANU"/>6038		<bitfield high="31" low="28" name="SEGT"/>6039	</reg32>6040	<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">6041		<bitfield high="27" low="24" name="ENABLE"/>6042	</reg32>6043	<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>6044	<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>6045	<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>6046	<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>6047	<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>6048	<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>6049	<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>6050	<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>6051	<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">6052		<bitfield high="3" low="0" name="BYTEL0"/>6053		<bitfield high="7" low="4" name="BYTEL1"/>6054		<bitfield high="11" low="8" name="BYTEL2"/>6055		<bitfield high="15" low="12" name="BYTEL3"/>6056		<bitfield high="19" low="16" name="BYTEL4"/>6057		<bitfield high="23" low="20" name="BYTEL5"/>6058		<bitfield high="27" low="24" name="BYTEL6"/>6059		<bitfield high="31" low="28" name="BYTEL7"/>6060	</reg32>6061	<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">6062		<bitfield high="3" low="0" name="BYTEL8"/>6063		<bitfield high="7" low="4" name="BYTEL9"/>6064		<bitfield high="11" low="8" name="BYTEL10"/>6065		<bitfield high="15" low="12" name="BYTEL11"/>6066		<bitfield high="19" low="16" name="BYTEL12"/>6067		<bitfield high="23" low="20" name="BYTEL13"/>6068		<bitfield high="27" low="24" name="BYTEL14"/>6069		<bitfield high="31" low="28" name="BYTEL15"/>6070	</reg32>6071 6072	<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>6073	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>6074</domain>6075 6076<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">6077	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>6078	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>6079	<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>6080	<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">6081		<bitfield pos="0" name="FASTBLEND" type="boolean"/>6082		<bitfield pos="1" name="LPAC" type="boolean"/>6083		<bitfield pos="2" name="RAYTRACING" type="boolean"/>6084	</reg32>6085</domain>6086 6087</database>6088