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1<?xml version="1.0" encoding="UTF-8"?>2<database xmlns="http://nouveau.freedesktop.org/"3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">5<import file="freedreno_copyright.xml"/>6 7<domain name="EDP" width="32">8 <enum name="edp_color_depth">9 <value name="EDP_6BIT" value="0"/>10 <value name="EDP_8BIT" value="1"/>11 <value name="EDP_10BIT" value="2"/>12 <value name="EDP_12BIT" value="3"/>13 <value name="EDP_16BIT" value="4"/>14 </enum>15 16 <enum name="edp_component_format">17 <value name="EDP_RGB" value="0"/>18 <value name="EDP_YUV422" value="1"/>19 <value name="EDP_YUV444" value="2"/>20 </enum>21 22 <reg32 offset="0x0004" name="MAINLINK_CTRL">23 <bitfield name="ENABLE" pos="0" type="boolean"/>24 <bitfield name="RESET" pos="1" type="boolean"/>25 </reg32>26 27 <reg32 offset="0x0008" name="STATE_CTRL">28 <bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>29 <bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>30 <bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>31 <bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>32 <bitfield name="PRBS7" pos="4" type="boolean"/>33 <bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>34 <bitfield name="SEND_VIDEO" pos="6" type="boolean"/>35 <bitfield name="PUSH_IDLE" pos="7" type="boolean"/>36 </reg32>37 38 <reg32 offset="0x000c" name="CONFIGURATION_CTRL">39 <!-- next two may be swapped? -->40 <bitfield name="SYNC_CLK" pos="0" type="boolean"/>41 <bitfield name="STATIC_MVID" pos="1" type="boolean"/>42 <bitfield name="PROGRESSIVE" pos="2" type="boolean"/>43 <!-- # of lanes minus one: -->44 <bitfield name="LANES" low="4" high="5" type="uint"/>45 <bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>46 <!--47 NOTE: only 6bit and 8bit valid48 -->49 <bitfield name="COLOR" pos="8" type="edp_color_depth"/>50 </reg32>51 52 <reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>53 <reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>54 55 <reg32 offset="0x001c" name="TOTAL_HOR_VER">56 <bitfield name="HORIZ" low="0" high="15" type="uint"/>57 <bitfield name="VERT" low="16" high="31" type="uint"/>58 </reg32>59 60 <reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">61 <bitfield name="HORIZ" low="0" high="15" type="uint"/>62 <bitfield name="VERT" low="16" high="31" type="uint"/>63 </reg32>64 65 <reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">66 <bitfield name="HORIZ" low="0" high="14" type="uint"/>67 <bitfield name="NHSYNC" pos="15" type="boolean"/>68 <bitfield name="VERT" low="16" high="30" type="uint"/>69 <bitfield name="NVSYNC" pos="31" type="boolean"/>70 </reg32>71 72 <reg32 offset="0x0028" name="ACTIVE_HOR_VER">73 <bitfield name="HORIZ" low="0" high="15" type="uint"/>74 <bitfield name="VERT" low="16" high="31" type="uint"/>75 </reg32>76 77 <reg32 offset="0x002c" name="MISC1_MISC0">78 <!-- MISC0 from DisplayPort v1.2 spec: -->79 <bitfield name="MISC0" low="0" high="7"/>80 <!-- aliased MISC0 bitfields: -->81 <bitfield name="SYNC" pos="0" type="boolean"/>82 <bitfield name="COMPONENT_FORMAT" low="1" high="2" type="edp_component_format"/>83 <!-- CEA (vs VESA) color range: -->84 <bitfield name="CEA" pos="3" type="boolean"/>85 <!-- YCbCr Colorimetry ITU-R BT709-5 (vs ITU-R BT601-5): -->86 <bitfield name="BT709_5" pos="4" type="boolean"/>87 <bitfield name="COLOR" low="5" high="7" type="edp_color_depth"/>88 89 <!-- MISC1 from DisplayPort v1.2 spec: -->90 <bitfield name="MISC1" low="8" high="15"/>91 <!-- aliased MISC1 bitfields: -->92 <bitfield name="INTERLACED_ODD" pos="8" type="boolean"/>93 <bitfield name="STEREO" low="9" high="10" type="uint"/>94 </reg32>95 96 <reg32 offset="0x0074" name="PHY_CTRL">97 <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>98 <bitfield name="SW_RESET" pos="2" type="boolean"/>99 </reg32>100 <reg32 offset="0x0084" name="MAINLINK_READY">101 <bitfield name="TRAIN_PATTERN_1_READY" pos="3" type="boolean"/>102 <bitfield name="TRAIN_PATTERN_2_READY" pos="4" type="boolean"/>103 <bitfield name="TRAIN_PATTERN_3_READY" pos="5" type="boolean"/>104 </reg32>105 106 <reg32 offset="0x0300" name="AUX_CTRL">107 <bitfield name="ENABLE" pos="0" type="boolean"/>108 <bitfield name="RESET" pos="1" type="boolean"/>109 </reg32>110 111 <!-- interrupt registers come in sets of 3 bits, status/ack/en -->112 <reg32 offset="0x0308" name="INTERRUPT_REG_1">113 <bitfield name="HPD" pos="0" type="boolean"/>114 <bitfield name="HPD_ACK" pos="1" type="boolean"/>115 <bitfield name="HPD_EN" pos="2" type="boolean"/>116 <bitfield name="AUX_I2C_DONE" pos="3" type="boolean"/>117 <bitfield name="AUX_I2C_DONE_ACK" pos="4" type="boolean"/>118 <bitfield name="AUX_I2C_DONE_EN" pos="5" type="boolean"/>119 <bitfield name="WRONG_ADDR" pos="6" type="boolean"/>120 <bitfield name="WRONG_ADDR_ACK" pos="7" type="boolean"/>121 <bitfield name="WRONG_ADDR_EN" pos="8" type="boolean"/>122 <bitfield name="TIMEOUT" pos="9" type="boolean"/>123 <bitfield name="TIMEOUT_ACK" pos="10" type="boolean"/>124 <bitfield name="TIMEOUT_EN" pos="11" type="boolean"/>125 <bitfield name="NACK_DEFER" pos="12" type="boolean"/>126 <bitfield name="NACK_DEFER_ACK" pos="13" type="boolean"/>127 <bitfield name="NACK_DEFER_EN" pos="14" type="boolean"/>128 <bitfield name="WRONG_DATA_CNT" pos="15" type="boolean"/>129 <bitfield name="WRONG_DATA_CNT_ACK" pos="16" type="boolean"/>130 <bitfield name="WRONG_DATA_CNT_EN" pos="17" type="boolean"/>131 <bitfield name="I2C_NACK" pos="18" type="boolean"/>132 <bitfield name="I2C_NACK_ACK" pos="19" type="boolean"/>133 <bitfield name="I2C_NACK_EN" pos="20" type="boolean"/>134 <bitfield name="I2C_DEFER" pos="21" type="boolean"/>135 <bitfield name="I2C_DEFER_ACK" pos="22" type="boolean"/>136 <bitfield name="I2C_DEFER_EN" pos="23" type="boolean"/>137 <bitfield name="PLL_UNLOCK" pos="24" type="boolean"/>138 <bitfield name="PLL_UNLOCK_ACK" pos="25" type="boolean"/>139 <bitfield name="PLL_UNLOCK_EN" pos="26" type="boolean"/>140 <bitfield name="AUX_ERROR" pos="27" type="boolean"/>141 <bitfield name="AUX_ERROR_ACK" pos="28" type="boolean"/>142 <bitfield name="AUX_ERROR_EN" pos="29" type="boolean"/>143 </reg32>144 145 <reg32 offset="0x030c" name="INTERRUPT_REG_2">146 <bitfield name="READY_FOR_VIDEO" pos="0" type="boolean"/>147 <bitfield name="READY_FOR_VIDEO_ACK" pos="1" type="boolean"/>148 <bitfield name="READY_FOR_VIDEO_EN" pos="2" type="boolean"/>149 <bitfield name="IDLE_PATTERNs_SENT" pos="3" type="boolean"/>150 <bitfield name="IDLE_PATTERNs_SENT_ACK" pos="4" type="boolean"/>151 <bitfield name="IDLE_PATTERNs_SENT_EN" pos="5" type="boolean"/>152 <bitfield name="FRAME_END" pos="9" type="boolean"/>153 <bitfield name="FRAME_END_ACK" pos="7" type="boolean"/>154 <bitfield name="FRAME_END_EN" pos="8" type="boolean"/>155 <bitfield name="CRC_UPDATED" pos="9" type="boolean"/>156 <bitfield name="CRC_UPDATED_ACK" pos="10" type="boolean"/>157 <bitfield name="CRC_UPDATED_EN" pos="11" type="boolean"/>158 </reg32>159 160 <reg32 offset="0x0310" name="INTERRUPT_TRANS_NUM"/>161 <reg32 offset="0x0314" name="AUX_DATA">162 <bitfield name="READ" pos="0" type="boolean"/>163 <bitfield name="DATA" low="8" high="15"/>164 <bitfield name="INDEX" low="16" high="23"/>165 <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>166 </reg32>167 168 <reg32 offset="0x0318" name="AUX_TRANS_CTRL">169 <bitfield name="I2C" pos="8" type="boolean"/>170 <bitfield name="GO" pos="9" type="boolean"/>171 </reg32>172 173 <reg32 offset="0x0324" name="AUX_STATUS"/>174</domain>175 176<domain name="EDP_PHY" width="32">177 <array offset="0x0400" name="LN" length="4" stride="0x40">178 <reg32 offset="0x04" name="PD_CTL"/>179 </array>180 <reg32 offset="0x0510" name="GLB_VM_CFG0"/>181 <reg32 offset="0x0514" name="GLB_VM_CFG1"/>182 <reg32 offset="0x0518" name="GLB_MISC9"/>183 <reg32 offset="0x0528" name="GLB_CFG"/>184 <reg32 offset="0x052c" name="GLB_PD_CTL"/>185 <reg32 offset="0x0598" name="GLB_PHY_STATUS"/>186</domain>187 188<domain name="EDP_28nm_PHY_PLL" width="32">189 <reg32 offset="0x00000" name="REFCLK_CFG"/>190 <reg32 offset="0x00004" name="POSTDIV1_CFG"/>191 <reg32 offset="0x00008" name="CHGPUMP_CFG"/>192 <reg32 offset="0x0000C" name="VCOLPF_CFG"/>193 <reg32 offset="0x00010" name="VREG_CFG"/>194 <reg32 offset="0x00014" name="PWRGEN_CFG"/>195 <reg32 offset="0x00018" name="DMUX_CFG"/>196 <reg32 offset="0x0001C" name="AMUX_CFG"/>197 <reg32 offset="0x00020" name="GLB_CFG">198 <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>199 <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>200 <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>201 <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>202 </reg32>203 <reg32 offset="0x00024" name="POSTDIV2_CFG"/>204 <reg32 offset="0x00028" name="POSTDIV3_CFG"/>205 <reg32 offset="0x0002C" name="LPFR_CFG"/>206 <reg32 offset="0x00030" name="LPFC1_CFG"/>207 <reg32 offset="0x00034" name="LPFC2_CFG"/>208 <reg32 offset="0x00038" name="SDM_CFG0"/>209 <reg32 offset="0x0003C" name="SDM_CFG1"/>210 <reg32 offset="0x00040" name="SDM_CFG2"/>211 <reg32 offset="0x00044" name="SDM_CFG3"/>212 <reg32 offset="0x00048" name="SDM_CFG4"/>213 <reg32 offset="0x0004C" name="SSC_CFG0"/>214 <reg32 offset="0x00050" name="SSC_CFG1"/>215 <reg32 offset="0x00054" name="SSC_CFG2"/>216 <reg32 offset="0x00058" name="SSC_CFG3"/>217 <reg32 offset="0x0005C" name="LKDET_CFG0"/>218 <reg32 offset="0x00060" name="LKDET_CFG1"/>219 <reg32 offset="0x00064" name="LKDET_CFG2"/>220 <reg32 offset="0x00068" name="TEST_CFG">221 <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>222 </reg32>223 <reg32 offset="0x0006C" name="CAL_CFG0"/>224 <reg32 offset="0x00070" name="CAL_CFG1"/>225 <reg32 offset="0x00074" name="CAL_CFG2"/>226 <reg32 offset="0x00078" name="CAL_CFG3"/>227 <reg32 offset="0x0007C" name="CAL_CFG4"/>228 <reg32 offset="0x00080" name="CAL_CFG5"/>229 <reg32 offset="0x00084" name="CAL_CFG6"/>230 <reg32 offset="0x00088" name="CAL_CFG7"/>231 <reg32 offset="0x0008C" name="CAL_CFG8"/>232 <reg32 offset="0x00090" name="CAL_CFG9"/>233 <reg32 offset="0x00094" name="CAL_CFG10"/>234 <reg32 offset="0x00098" name="CAL_CFG11"/>235 <reg32 offset="0x0009C" name="EFUSE_CFG"/>236 <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>237</domain>238 239</database>240