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1/*2 * Copyright 2018 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#include "head.h"23#include "base.h"24#include "core.h"25#include "curs.h"26#include "ovly.h"27#include "crc.h"28 29#include <nvif/class.h>30#include <nvif/event.h>31#include <nvif/cl0046.h>32 33#include <drm/drm_atomic.h>34#include <drm/drm_atomic_helper.h>35#include <drm/drm_edid.h>36#include <drm/drm_vblank.h>37#include "nouveau_connector.h"38 39void40nv50_head_flush_clr(struct nv50_head *head,41 struct nv50_head_atom *asyh, bool flush)42{43 union nv50_head_atom_mask clr = {44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),45 };46 if (clr.crc) nv50_crc_atomic_clr(head);47 if (clr.olut) head->func->olut_clr(head);48 if (clr.core) head->func->core_clr(head);49 if (clr.curs) head->func->curs_clr(head);50}51 52void53nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)54{55 if (asyh->set.curs ) head->func->curs_set(head, asyh);56 if (asyh->set.olut ) {57 asyh->olut.offset = nv50_lut_load(&head->olut,58 asyh->olut.buffer,59 asyh->state.gamma_lut,60 asyh->olut.load);61 head->func->olut_set(head, asyh);62 }63}64 65void66nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)67{68 if (asyh->set.view ) head->func->view (head, asyh);69 if (asyh->set.mode ) head->func->mode (head, asyh);70 if (asyh->set.core ) head->func->core_set(head, asyh);71 if (asyh->set.base ) head->func->base (head, asyh);72 if (asyh->set.ovly ) head->func->ovly (head, asyh);73 if (asyh->set.dither ) head->func->dither (head, asyh);74 if (asyh->set.procamp) head->func->procamp (head, asyh);75 if (asyh->set.crc ) nv50_crc_atomic_set (head, asyh);76 if (asyh->set.or ) head->func->or (head, asyh);77}78 79static void80nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,81 struct nv50_head_atom *asyh,82 struct nouveau_conn_atom *asyc)83{84 const int vib = asyc->procamp.color_vibrance - 100;85 const int hue = asyc->procamp.vibrant_hue - 90;86 const int adj = (vib > 0) ? 50 : 0;87 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;88 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;89 asyh->set.procamp = true;90}91 92static void93nv50_head_atomic_check_dither(struct nv50_head_atom *armh,94 struct nv50_head_atom *asyh,95 struct nouveau_conn_atom *asyc)96{97 u32 mode = 0x00;98 99 if (asyc->dither.mode) {100 if (asyc->dither.mode == DITHERING_MODE_AUTO) {101 if (asyh->base.depth > asyh->or.bpc * 3)102 mode = DITHERING_MODE_DYNAMIC2X2;103 } else {104 mode = asyc->dither.mode;105 }106 107 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {108 if (asyh->or.bpc >= 8)109 mode |= DITHERING_DEPTH_8BPC;110 } else {111 mode |= asyc->dither.depth;112 }113 }114 115 asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);116 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);117 asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);118 asyh->set.dither = true;119}120 121static void122nv50_head_atomic_check_view(struct nv50_head_atom *armh,123 struct nv50_head_atom *asyh,124 struct nouveau_conn_atom *asyc)125{126 struct drm_connector *connector = asyc->state.connector;127 struct drm_display_mode *omode = &asyh->state.adjusted_mode;128 struct drm_display_mode *umode = &asyh->state.mode;129 int mode = asyc->scaler.mode;130 int umode_vdisplay, omode_hdisplay, omode_vdisplay;131 132 if (!asyc->scaler.full) {133 if (mode == DRM_MODE_SCALE_NONE)134 omode = umode;135 } else {136 /* Non-EDID LVDS/eDP mode. */137 mode = DRM_MODE_SCALE_FULLSCREEN;138 }139 140 /* For the user-specified mode, we must ignore doublescan and141 * the like, but honor frame packing.142 */143 umode_vdisplay = umode->vdisplay;144 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)145 umode_vdisplay += umode->vtotal;146 asyh->view.iW = umode->hdisplay;147 asyh->view.iH = umode_vdisplay;148 /* For the output mode, we can just use the stock helper. */149 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);150 asyh->view.oW = omode_hdisplay;151 asyh->view.oH = omode_vdisplay;152 153 /* Add overscan compensation if necessary, will keep the aspect154 * ratio the same as the backend mode unless overridden by the155 * user setting both hborder and vborder properties.156 */157 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||158 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&159 connector->display_info.is_hdmi))) {160 u32 bX = asyc->scaler.underscan.hborder;161 u32 bY = asyc->scaler.underscan.vborder;162 u32 r = (asyh->view.oH << 19) / asyh->view.oW;163 164 if (bX) {165 asyh->view.oW -= (bX * 2);166 if (bY) asyh->view.oH -= (bY * 2);167 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;168 } else {169 asyh->view.oW -= (asyh->view.oW >> 4) + 32;170 if (bY) asyh->view.oH -= (bY * 2);171 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;172 }173 }174 175 /* Handle CENTER/ASPECT scaling, taking into account the areas176 * removed already for overscan compensation.177 */178 switch (mode) {179 case DRM_MODE_SCALE_CENTER:180 /* NOTE: This will cause scaling when the input is181 * larger than the output.182 */183 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);184 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);185 break;186 case DRM_MODE_SCALE_ASPECT:187 /* Determine whether the scaling should be on width or on188 * height. This is done by comparing the aspect ratios of the189 * sizes. If the output AR is larger than input AR, that means190 * we want to change the width (letterboxed on the191 * left/right), otherwise on the height (letterboxed on the192 * top/bottom).193 *194 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR195 * screen will have letterboxes on the left/right. However a196 * 16:9 (1.777) AR image on that same screen will have197 * letterboxes on the top/bottom.198 *199 * inputAR = iW / iH; outputAR = oW / oH200 * outputAR > inputAR is equivalent to oW * iH > iW * oH201 */202 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {203 /* Recompute output width, i.e. left/right letterbox */204 u32 r = (asyh->view.iW << 19) / asyh->view.iH;205 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;206 } else {207 /* Recompute output height, i.e. top/bottom letterbox */208 u32 r = (asyh->view.iH << 19) / asyh->view.iW;209 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;210 }211 break;212 default:213 break;214 }215 216 asyh->set.view = true;217}218 219static int220nv50_head_atomic_check_lut(struct nv50_head *head,221 struct nv50_head_atom *asyh)222{223 struct drm_device *dev = head->base.base.dev;224 struct drm_crtc *crtc = &head->base.base;225 struct nv50_disp *disp = nv50_disp(dev);226 struct nouveau_drm *drm = nouveau_drm(dev);227 struct drm_property_blob *olut = asyh->state.gamma_lut,228 *ilut = asyh->state.degamma_lut;229 int size;230 231 /* Ensure that the ilut is valid */232 if (ilut) {233 size = drm_color_lut_size(ilut);234 if (!head->func->ilut_check(size)) {235 NV_ATOMIC(drm, "Invalid size %d for degamma on [CRTC:%d:%s]\n",236 size, crtc->base.id, crtc->name);237 return -EINVAL;238 }239 }240 241 /* Determine whether core output LUT should be enabled. */242 if (olut) {243 /* Check if any window(s) have stolen the core output LUT244 * to as an input LUT for legacy gamma + I8 colour format.245 */246 if (asyh->wndw.olut) {247 /* If any window has stolen the core output LUT,248 * all of them must.249 */250 if (asyh->wndw.olut != asyh->wndw.mask)251 return -EINVAL;252 olut = NULL;253 }254 }255 256 if (!olut) {257 if (!head->func->olut_identity) {258 asyh->olut.handle = 0;259 return 0;260 }261 size = 0;262 } else {263 size = drm_color_lut_size(olut);264 }265 266 if (!head->func->olut(head, asyh, size)) {267 NV_ATOMIC(drm, "Invalid size %d for gamma on [CRTC:%d:%s]\n",268 size, crtc->base.id, crtc->name);269 return -EINVAL;270 }271 asyh->olut.handle = disp->core->chan.vram.handle;272 asyh->olut.buffer = !asyh->olut.buffer;273 274 return 0;275}276 277static void278nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)279{280 struct drm_display_mode *mode = &asyh->state.adjusted_mode;281 struct nv50_head_mode *m = &asyh->mode;282 u32 blankus;283 284 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);285 286 /*287 * DRM modes are defined in terms of a repeating interval288 * starting with the active display area. The hardware modes289 * are defined in terms of a repeating interval starting one290 * unit (pixel or line) into the sync pulse. So, add bias.291 */292 293 m->h.active = mode->crtc_htotal;294 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;295 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;296 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;297 298 m->v.active = mode->crtc_vtotal;299 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;300 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;301 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;302 303 /*XXX: Safe underestimate, even "0" works */304 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;305 blankus *= 1000;306 blankus /= mode->crtc_clock;307 m->v.blankus = blankus;308 309 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {310 m->v.blank2e = m->v.active + m->v.blanke;311 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;312 m->v.active = (m->v.active * 2) + 1;313 m->interlace = true;314 } else {315 m->v.blank2e = 0;316 m->v.blank2s = 1;317 m->interlace = false;318 }319 m->clock = mode->crtc_clock;320 321 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);322 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);323 asyh->set.or = head->func->or != NULL;324 asyh->set.mode = true;325}326 327static int328nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)329{330 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,331 crtc);332 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,333 crtc);334 struct nouveau_drm *drm = nouveau_drm(crtc->dev);335 struct nv50_head *head = nv50_head(crtc);336 struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state);337 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);338 struct nouveau_conn_atom *asyc = NULL;339 struct drm_connector_state *conns;340 struct drm_connector *conn;341 int i, ret;342 bool check_lut = asyh->state.color_mgmt_changed ||343 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw));344 345 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);346 347 if (check_lut) {348 ret = nv50_head_atomic_check_lut(head, asyh);349 if (ret)350 return ret;351 }352 353 if (asyh->state.active) {354 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {355 if (conns->crtc == crtc) {356 asyc = nouveau_conn_atom(conns);357 break;358 }359 }360 361 if (armh->state.active) {362 if (asyc) {363 if (asyh->state.mode_changed)364 asyc->set.scaler = true;365 if (armh->base.depth != asyh->base.depth)366 asyc->set.dither = true;367 }368 } else {369 if (asyc)370 asyc->set.mask = ~0;371 asyh->set.mask = ~0;372 asyh->set.or = head->func->or != NULL;373 }374 375 if (asyh->state.mode_changed || asyh->state.connectors_changed)376 nv50_head_atomic_check_mode(head, asyh);377 378 if (check_lut)379 asyh->olut.visible = asyh->olut.handle != 0;380 381 if (asyc) {382 if (asyc->set.scaler)383 nv50_head_atomic_check_view(armh, asyh, asyc);384 if (asyc->set.dither)385 nv50_head_atomic_check_dither(armh, asyh, asyc);386 if (asyc->set.procamp)387 nv50_head_atomic_check_procamp(armh, asyh, asyc);388 }389 390 if (head->func->core_calc) {391 head->func->core_calc(head, asyh);392 if (!asyh->core.visible)393 asyh->olut.visible = false;394 }395 396 asyh->set.base = armh->base.cpp != asyh->base.cpp;397 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;398 } else {399 asyh->olut.visible = false;400 asyh->core.visible = false;401 asyh->curs.visible = false;402 asyh->base.cpp = 0;403 asyh->ovly.cpp = 0;404 }405 406 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {407 if (asyh->core.visible) {408 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))409 asyh->set.core = true;410 } else411 if (armh->core.visible) {412 asyh->clr.core = true;413 }414 415 if (asyh->curs.visible) {416 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))417 asyh->set.curs = true;418 } else419 if (armh->curs.visible) {420 asyh->clr.curs = true;421 }422 423 if (asyh->olut.visible) {424 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))425 asyh->set.olut = true;426 } else427 if (armh->olut.visible) {428 asyh->clr.olut = true;429 }430 } else {431 asyh->clr.olut = armh->olut.visible;432 asyh->clr.core = armh->core.visible;433 asyh->clr.curs = armh->curs.visible;434 asyh->set.olut = asyh->olut.visible;435 asyh->set.core = asyh->core.visible;436 asyh->set.curs = asyh->curs.visible;437 }438 439 ret = nv50_crc_atomic_check_head(head, asyh, armh);440 if (ret)441 return ret;442 443 if (asyh->clr.mask || asyh->set.mask)444 nv50_atom(asyh->state.state)->lock_core = true;445 return 0;446}447 448static const struct drm_crtc_helper_funcs449nv50_head_help = {450 .atomic_check = nv50_head_atomic_check,451 .get_scanout_position = nouveau_display_scanoutpos,452};453 454static void455nv50_head_atomic_destroy_state(struct drm_crtc *crtc,456 struct drm_crtc_state *state)457{458 struct nv50_head_atom *asyh = nv50_head_atom(state);459 __drm_atomic_helper_crtc_destroy_state(&asyh->state);460 kfree(asyh);461}462 463static struct drm_crtc_state *464nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)465{466 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);467 struct nv50_head_atom *asyh;468 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))469 return NULL;470 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);471 asyh->wndw = armh->wndw;472 asyh->view = armh->view;473 asyh->mode = armh->mode;474 asyh->olut = armh->olut;475 asyh->core = armh->core;476 asyh->curs = armh->curs;477 asyh->base = armh->base;478 asyh->ovly = armh->ovly;479 asyh->dither = armh->dither;480 asyh->procamp = armh->procamp;481 asyh->crc = armh->crc;482 asyh->or = armh->or;483 asyh->dp = armh->dp;484 asyh->clr.mask = 0;485 asyh->set.mask = 0;486 return &asyh->state;487}488 489static void490nv50_head_reset(struct drm_crtc *crtc)491{492 struct nv50_head_atom *asyh;493 494 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))495 return;496 497 if (crtc->state)498 nv50_head_atomic_destroy_state(crtc, crtc->state);499 500 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);501}502 503static int504nv50_head_late_register(struct drm_crtc *crtc)505{506 return nv50_head_crc_late_register(nv50_head(crtc));507}508 509static void510nv50_head_destroy(struct drm_crtc *crtc)511{512 struct nv50_head *head = nv50_head(crtc);513 514 nvif_event_dtor(&head->base.vblank);515 nvif_head_dtor(&head->base.head);516 nv50_lut_fini(&head->olut);517 drm_crtc_cleanup(crtc);518 kfree(head);519}520 521static const struct drm_crtc_funcs522nv50_head_func = {523 .reset = nv50_head_reset,524 .destroy = nv50_head_destroy,525 .set_config = drm_atomic_helper_set_config,526 .page_flip = drm_atomic_helper_page_flip,527 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,528 .atomic_destroy_state = nv50_head_atomic_destroy_state,529 .enable_vblank = nouveau_display_vblank_enable,530 .disable_vblank = nouveau_display_vblank_disable,531 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,532 .late_register = nv50_head_late_register,533};534 535static const struct drm_crtc_funcs536nvd9_head_func = {537 .reset = nv50_head_reset,538 .destroy = nv50_head_destroy,539 .set_config = drm_atomic_helper_set_config,540 .page_flip = drm_atomic_helper_page_flip,541 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,542 .atomic_destroy_state = nv50_head_atomic_destroy_state,543 .enable_vblank = nouveau_display_vblank_enable,544 .disable_vblank = nouveau_display_vblank_disable,545 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,546 .verify_crc_source = nv50_crc_verify_source,547 .get_crc_sources = nv50_crc_get_sources,548 .set_crc_source = nv50_crc_set_source,549 .late_register = nv50_head_late_register,550};551 552static int553nv50_head_vblank_handler(struct nvif_event *event, void *repv, u32 repc)554{555 struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank);556 557 if (drm_crtc_handle_vblank(&nv_crtc->base))558 nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));559 560 return NVIF_EVENT_KEEP;561}562 563struct nv50_head *564nv50_head_create(struct drm_device *dev, int index)565{566 struct nouveau_drm *drm = nouveau_drm(dev);567 struct nv50_disp *disp = nv50_disp(dev);568 struct nv50_head *head;569 struct nv50_wndw *base, *ovly, *curs;570 struct nouveau_crtc *nv_crtc;571 struct drm_crtc *crtc;572 const struct drm_crtc_funcs *funcs;573 int ret;574 575 head = kzalloc(sizeof(*head), GFP_KERNEL);576 if (!head)577 return ERR_PTR(-ENOMEM);578 579 head->func = disp->core->func->head;580 head->base.index = index;581 582 if (disp->disp->object.oclass < GF110_DISP)583 funcs = &nv50_head_func;584 else585 funcs = &nvd9_head_func;586 587 if (disp->disp->object.oclass < GV100_DISP) {588 ret = nv50_base_new(drm, head->base.index, &base);589 ret = nv50_ovly_new(drm, head->base.index, &ovly);590 } else {591 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,592 head->base.index * 2 + 0, &base);593 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,594 head->base.index * 2 + 1, &ovly);595 }596 if (ret == 0)597 ret = nv50_curs_new(drm, head->base.index, &curs);598 if (ret) {599 kfree(head);600 return ERR_PTR(ret);601 }602 603 nv_crtc = &head->base;604 crtc = &nv_crtc->base;605 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,606 funcs, "head-%d", head->base.index);607 drm_crtc_helper_add(crtc, &nv50_head_help);608 /* Keep the legacy gamma size at 256 to avoid compatibility issues */609 drm_mode_crtc_set_gamma_size(crtc, 256);610 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,611 disp->disp->object.oclass >= GF110_DISP,612 head->func->olut_size);613 614 if (head->func->olut_set) {615 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);616 if (ret) {617 nv50_head_destroy(crtc);618 return ERR_PTR(ret);619 }620 }621 622 ret = nvif_head_ctor(disp->disp, head->base.base.name, head->base.index, &head->base.head);623 if (ret)624 return ERR_PTR(ret);625 626 ret = nvif_head_vblank_event_ctor(&head->base.head, "kmsVbl", nv50_head_vblank_handler,627 false, &nv_crtc->vblank);628 if (ret)629 return ERR_PTR(ret);630 631 return head;632}633