68 lines · c
1/* SPDX-License-Identifier: MIT */2#ifndef __NVIF_CL0002_H__3#define __NVIF_CL0002_H__4 5struct nv_dma_v0 {6 __u8 version;7#define NV_DMA_V0_TARGET_VM 0x008#define NV_DMA_V0_TARGET_VRAM 0x019#define NV_DMA_V0_TARGET_PCI 0x0210#define NV_DMA_V0_TARGET_PCI_US 0x0311#define NV_DMA_V0_TARGET_AGP 0x0412 __u8 target;13#define NV_DMA_V0_ACCESS_VM 0x0014#define NV_DMA_V0_ACCESS_RD 0x0115#define NV_DMA_V0_ACCESS_WR 0x0216#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)17 __u8 access;18 __u8 pad03[5];19 __u64 start;20 __u64 limit;21 /* ... chipset-specific class data */22};23 24struct nv50_dma_v0 {25 __u8 version;26#define NV50_DMA_V0_PRIV_VM 0x0027#define NV50_DMA_V0_PRIV_US 0x0128#define NV50_DMA_V0_PRIV__S 0x0229 __u8 priv;30#define NV50_DMA_V0_PART_VM 0x0031#define NV50_DMA_V0_PART_256 0x0132#define NV50_DMA_V0_PART_1KB 0x0233 __u8 part;34#define NV50_DMA_V0_COMP_NONE 0x0035#define NV50_DMA_V0_COMP_1 0x0136#define NV50_DMA_V0_COMP_2 0x0237#define NV50_DMA_V0_COMP_VM 0x0338 __u8 comp;39#define NV50_DMA_V0_KIND_PITCH 0x0040#define NV50_DMA_V0_KIND_VM 0x7f41 __u8 kind;42 __u8 pad05[3];43};44 45struct gf100_dma_v0 {46 __u8 version;47#define GF100_DMA_V0_PRIV_VM 0x0048#define GF100_DMA_V0_PRIV_US 0x0149#define GF100_DMA_V0_PRIV__S 0x0250 __u8 priv;51#define GF100_DMA_V0_KIND_PITCH 0x0052#define GF100_DMA_V0_KIND_VM 0xff53 __u8 kind;54 __u8 pad03[5];55};56 57struct gf119_dma_v0 {58 __u8 version;59#define GF119_DMA_V0_PAGE_LP 0x0060#define GF119_DMA_V0_PAGE_SP 0x0161 __u8 page;62#define GF119_DMA_V0_KIND_PITCH 0x0063#define GF119_DMA_V0_KIND_VM 0xff64 __u8 kind;65 __u8 pad03[5];66};67#endif68