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1/* SPDX-License-Identifier: MIT */2#ifndef __NVBIOS_PLL_H__3#define __NVBIOS_PLL_H__4/*XXX: kill me */5struct nvkm_pll_vals {6 union {7 struct {8#ifdef __BIG_ENDIAN9 uint8_t N1, M1, N2, M2;10#else11 uint8_t M1, N1, M2, N2;12#endif13 };14 struct {15 uint16_t NM1, NM2;16 } __attribute__((packed));17 };18 int log2P;19 20 int refclk;21};22 23/* these match types in pll limits table version 0x40,24 * nvkm uses them on all chipsets internally where a25 * specific pll needs to be referenced, but the exact26 * register isn't known.27 */28enum nvbios_pll_type {29 PLL_CORE = 0x01,30 PLL_SHADER = 0x02,31 PLL_UNK03 = 0x03,32 PLL_MEMORY = 0x04,33 PLL_VDEC = 0x05,34 PLL_UNK40 = 0x40,35 PLL_UNK41 = 0x41,36 PLL_UNK42 = 0x42,37 PLL_VPLL0 = 0x80,38 PLL_VPLL1 = 0x81,39 PLL_VPLL2 = 0x82,40 PLL_VPLL3 = 0x83,41 PLL_MAX = 0xff42};43 44struct nvbios_pll {45 enum nvbios_pll_type type;46 u32 reg;47 u32 refclk;48 49 u8 min_p;50 u8 max_p;51 u8 bias_p;52 53 /*54 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p55 * value) is no different to 6 (at least for vplls) so allowing the MNP56 * calc to use 7 causes the generated clock to be out by a factor of 2.57 * however, max_log2p cannot be fixed-up during parsing as the58 * unmodified max_log2p value is still needed for setting mplls, hence59 * an additional max_usable_log2p member60 */61 u8 max_p_usable;62 63 struct {64 u32 min_freq;65 u32 max_freq;66 u32 min_inputfreq;67 u32 max_inputfreq;68 u8 min_m;69 u8 max_m;70 u8 min_n;71 u8 max_n;72 } vco1, vco2;73};74 75int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);76#endif77