860 lines · c
1/* SPDX-License-Identifier: MIT */2 3#define NV04_PFB_BOOT_0 0x001000004# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x000000035# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x000000006# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x000000017# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x000000028# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x000000039# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x0000000410# define NV04_PFB_BOOT_0_RAM_TYPE 0x0000002811# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x0000000012# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x0000000813# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x0000001014# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x0000001815# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x0000002016# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x0000002817# define NV04_PFB_BOOT_0_UMA_ENABLE 0x0000010018# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f00019#define NV04_PFB_DEBUG_0 0x0010008020# define NV04_PFB_DEBUG_0_PAGE_MODE 0x0000000121# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x0000001022# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f0023# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x0000400024# define NV04_PFB_DEBUG_0_SAFE_MODE 0x0000800025# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x0001000026# define NV04_PFB_DEBUG_0_CASOE 0x0010000027# define NV04_PFB_DEBUG_0_CKE_INVERT 0x1000000028# define NV04_PFB_DEBUG_0_REFINC 0x2000000029# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x4000000030#define NV04_PFB_CFG0 0x0010020031# define NV04_PFB_CFG0_SCRAMBLE 0x2000000032#define NV04_PFB_CFG1 0x0010020433#define NV04_PFB_FIFO_DATA 0x0010020c34# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff0000035# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 2036#define NV10_PFB_REFCTRL 0x0010021037# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)38#define NV04_PFB_PAD 0x0010021c39# define NV04_PFB_PAD_CKE_NORMAL (1 << 0)40#define NV10_PFB_TILE(i) (0x00100240 + (i*16))41#define NV10_PFB_TILE__SIZE 842#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))43#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))44#define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16))45#define NV04_PFB_REF 0x001002d046# define NV04_PFB_REF_CMD_REFRESH (1 << 0)47#define NV04_PFB_PRE 0x001002d448# define NV04_PFB_PRE_CMD_PRECHARGE (1 << 0)49#define NV20_PFB_ZCOMP(i) (0x00100300 + 4*(i))50# define NV20_PFB_ZCOMP_MODE_32 (4 << 24)51# define NV20_PFB_ZCOMP_EN (1 << 31)52# define NV25_PFB_ZCOMP_MODE_16 (1 << 20)53# define NV25_PFB_ZCOMP_MODE_32 (2 << 20)54#define NV10_PFB_CLOSE_PAGE2 0x0010033c55#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))56#define NV40_PFB_TILE(i) (0x00100600 + (i*16))57#define NV40_PFB_TILE__SIZE_0 1258#define NV40_PFB_TILE__SIZE_1 1559#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))60#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))61#define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16))62#define NV40_PFB_UNK_800 0x0010080063 64#define NV_PEXTDEV_BOOT_0 0x0010100065#define NV_PEXTDEV_BOOT_0_RAMCFG 0x0000003c66# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12)67#define NV_PEXTDEV_BOOT_3 0x0010100c68 69#define NV_RAMIN 0x0070000070 71#define NV_RAMHT_HANDLE_OFFSET 072#define NV_RAMHT_CONTEXT_OFFSET 473# define NV_RAMHT_CONTEXT_VALID (1<<31)74# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 2475# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 1676# define NV_RAMHT_CONTEXT_ENGINE_SW 077# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 178# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 079# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 2380# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 2081# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 082 83/* Some object classes we care about in the drm */84#define NV_CLASS_DMA_FROM_MEMORY 0x0000000285#define NV_CLASS_DMA_TO_MEMORY 0x0000000386#define NV_CLASS_NULL 0x0000003087#define NV_CLASS_DMA_IN_MEMORY 0x0000003D88 89#define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE))90#define NV03_USER__SIZE 1691#define NV10_USER__SIZE 3292#define NV03_USER_SIZE 0x0001000093#define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE))94#define NV03_USER_DMA_PUT__SIZE 1695#define NV10_USER_DMA_PUT__SIZE 3296#define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE))97#define NV03_USER_DMA_GET__SIZE 1698#define NV10_USER_DMA_GET__SIZE 3299#define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE))100#define NV03_USER_REF_CNT__SIZE 16101#define NV10_USER_REF_CNT__SIZE 32102 103#define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE))104#define NV40_USER_SIZE 0x00001000105#define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE))106#define NV40_USER_DMA_PUT__SIZE 32107#define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE))108#define NV40_USER_DMA_GET__SIZE 32109#define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE))110#define NV40_USER_REF_CNT__SIZE 32111 112#define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE))113#define NV50_USER_SIZE 0x00002000114#define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE))115#define NV50_USER_DMA_PUT__SIZE 128116#define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE))117#define NV50_USER_DMA_GET__SIZE 128118#define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE))119#define NV50_USER_REF_CNT__SIZE 128120 121#define NV03_FIFO_SIZE 0x8000UL122 123#define NV03_PMC_BOOT_0 0x00000000124#define NV03_PMC_BOOT_1 0x00000004125#define NV03_PMC_INTR_0 0x00000100126# define NV_PMC_INTR_0_PFIFO_PENDING (1<<8)127# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)128# define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21)129# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)130# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)131# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26)132# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)133#define NV03_PMC_INTR_EN_0 0x00000140134# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<<0)135#define NV03_PMC_ENABLE 0x00000200136# define NV_PMC_ENABLE_PFIFO (1<<8)137# define NV_PMC_ENABLE_PGRAPH (1<<12)138/* Disabling the below bit breaks newer (G7X only?) mobile chipsets,139 * the card will hang early on in the X init process.140 */141# define NV_PMC_ENABLE_UNK13 (1<<13)142#define NV40_PMC_GRAPH_UNITS 0x00001540143#define NV40_PMC_BACKLIGHT 0x000015f0144# define NV40_PMC_BACKLIGHT_MASK 0x001f0000145#define NV40_PMC_1700 0x00001700146#define NV40_PMC_1704 0x00001704147#define NV40_PMC_1708 0x00001708148#define NV40_PMC_170C 0x0000170C149 150/* probably PMC ? */151#define NV50_PUNK_BAR0_PRAMIN 0x00001700152#define NV50_PUNK_BAR_CFG_BASE 0x00001704153#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30)154#define NV50_PUNK_BAR1_CTXDMA 0x00001708155#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31)156#define NV50_PUNK_BAR3_CTXDMA 0x0000170C157#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31)158#define NV50_PUNK_UNK1710 0x00001710159 160#define NV04_PBUS_PCI_NV_1 0x00001804161#define NV04_PBUS_PCI_NV_19 0x0000184C162#define NV04_PBUS_PCI_NV_20 0x00001850163# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)164# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)165 166#define NV04_PTIMER_INTR_0 0x00009100167#define NV04_PTIMER_INTR_EN_0 0x00009140168#define NV04_PTIMER_NUMERATOR 0x00009200169#define NV04_PTIMER_DENOMINATOR 0x00009210170#define NV04_PTIMER_TIME_0 0x00009400171#define NV04_PTIMER_TIME_1 0x00009410172#define NV04_PTIMER_ALARM_0 0x00009420173 174#define NV04_PGRAPH_DEBUG_0 0x00400080175#define NV04_PGRAPH_DEBUG_1 0x00400084176#define NV04_PGRAPH_DEBUG_2 0x00400088177#define NV04_PGRAPH_DEBUG_3 0x0040008c178#define NV10_PGRAPH_DEBUG_4 0x00400090179#define NV03_PGRAPH_INTR 0x00400100180#define NV03_PGRAPH_NSTATUS 0x00400104181# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11)182# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12)183# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13)184# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14)185# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23)186# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24)187# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25)188# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26)189#define NV03_PGRAPH_NSOURCE 0x00400108190# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0)191# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1)192# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2)193# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3)194# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4)195# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5)196# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6)197# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7)198# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8)199# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9)200# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10)201# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11)202# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12)203# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13)204# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14)205# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15)206# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16)207# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17)208# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18)209#define NV03_PGRAPH_INTR_EN 0x00400140210#define NV40_PGRAPH_INTR_EN 0x0040013C211# define NV_PGRAPH_INTR_NOTIFY (1<<0)212# define NV_PGRAPH_INTR_MISSING_HW (1<<4)213# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)214# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)215# define NV_PGRAPH_INTR_ERROR (1<<20)216#define NV10_PGRAPH_CTX_CONTROL 0x00400144217#define NV10_PGRAPH_CTX_USER 0x00400148218#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i))219#define NV04_PGRAPH_CTX_SWITCH1 0x00400160220#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \221 + 0x4*(i) + 0x20*(j))222#define NV04_PGRAPH_CTX_SWITCH2 0x00400164223#define NV04_PGRAPH_CTX_SWITCH3 0x00400168224#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C225#define NV04_PGRAPH_CTX_CONTROL 0x00400170226#define NV04_PGRAPH_CTX_USER 0x00400174227#define NV04_PGRAPH_CTX_CACHE1 0x00400180228#define NV03_PGRAPH_CTX_CONTROL 0x00400190229#define NV03_PGRAPH_CTX_USER 0x00400194230#define NV04_PGRAPH_CTX_CACHE2 0x004001A0231#define NV04_PGRAPH_CTX_CACHE3 0x004001C0232#define NV04_PGRAPH_CTX_CACHE4 0x004001E0233#define NV40_PGRAPH_CTXCTL_0304 0x00400304234#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001235#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308236#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000237#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24238#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff239#define NV40_PGRAPH_CTXCTL_0310 0x00400310240#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020241#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040242#define NV40_PGRAPH_CTXCTL_030C 0x0040030c243#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324244#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328245#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c246#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000247#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF248#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330249#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff250#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c251#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000252#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff253#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330254#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff255#define NV03_PGRAPH_ABS_X_RAM 0x00400400256#define NV03_PGRAPH_ABS_Y_RAM 0x00400480257#define NV03_PGRAPH_X_MISC 0x00400500258#define NV03_PGRAPH_Y_MISC 0x00400504259#define NV04_PGRAPH_VALID1 0x00400508260#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C261#define NV04_PGRAPH_MISC24_0 0x00400510262#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514263#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518264#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C265#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520266#define NV03_PGRAPH_CLIPX_0 0x00400524267#define NV03_PGRAPH_CLIPX_1 0x00400528268#define NV03_PGRAPH_CLIPY_0 0x0040052C269#define NV03_PGRAPH_CLIPY_1 0x00400530270#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534271#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538272#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C273#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540274#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544275#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548276#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560277#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564278#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568279#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C280#define NV04_PGRAPH_MISC24_1 0x00400570281#define NV04_PGRAPH_MISC24_2 0x00400574282#define NV04_PGRAPH_VALID2 0x00400578283#define NV04_PGRAPH_PASSTHRU_0 0x0040057C284#define NV04_PGRAPH_PASSTHRU_1 0x00400580285#define NV04_PGRAPH_PASSTHRU_2 0x00400584286#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588287#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C288#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590289#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594290#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598291#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C292#define NV04_PGRAPH_FORMAT_0 0x004005A8293#define NV04_PGRAPH_FORMAT_1 0x004005AC294#define NV04_PGRAPH_FILTER_0 0x004005B0295#define NV04_PGRAPH_FILTER_1 0x004005B4296#define NV03_PGRAPH_MONO_COLOR0 0x00400600297#define NV04_PGRAPH_ROP3 0x00400604298#define NV04_PGRAPH_BETA_AND 0x00400608299#define NV04_PGRAPH_BETA_PREMULT 0x0040060C300#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610301#define NV04_PGRAPH_FORMATS 0x00400618302#define NV10_PGRAPH_DEBUG_2 0x00400620303#define NV04_PGRAPH_BOFFSET0 0x00400640304#define NV04_PGRAPH_BOFFSET1 0x00400644305#define NV04_PGRAPH_BOFFSET2 0x00400648306#define NV04_PGRAPH_BOFFSET3 0x0040064C307#define NV04_PGRAPH_BOFFSET4 0x00400650308#define NV04_PGRAPH_BOFFSET5 0x00400654309#define NV04_PGRAPH_BBASE0 0x00400658310#define NV04_PGRAPH_BBASE1 0x0040065C311#define NV04_PGRAPH_BBASE2 0x00400660312#define NV04_PGRAPH_BBASE3 0x00400664313#define NV04_PGRAPH_BBASE4 0x00400668314#define NV04_PGRAPH_BBASE5 0x0040066C315#define NV04_PGRAPH_BPITCH0 0x00400670316#define NV04_PGRAPH_BPITCH1 0x00400674317#define NV04_PGRAPH_BPITCH2 0x00400678318#define NV04_PGRAPH_BPITCH3 0x0040067C319#define NV04_PGRAPH_BPITCH4 0x00400680320#define NV04_PGRAPH_BLIMIT0 0x00400684321#define NV04_PGRAPH_BLIMIT1 0x00400688322#define NV04_PGRAPH_BLIMIT2 0x0040068C323#define NV04_PGRAPH_BLIMIT3 0x00400690324#define NV04_PGRAPH_BLIMIT4 0x00400694325#define NV04_PGRAPH_BLIMIT5 0x00400698326#define NV04_PGRAPH_BSWIZZLE2 0x0040069C327#define NV04_PGRAPH_BSWIZZLE5 0x004006A0328#define NV03_PGRAPH_STATUS 0x004006B0329#define NV04_PGRAPH_STATUS 0x00400700330# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000331#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704332#define NV04_PGRAPH_TRAPPED_DATA 0x00400708333#define NV04_PGRAPH_SURFACE 0x0040070C334#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C335#define NV04_PGRAPH_STATE 0x00400710336#define NV10_PGRAPH_SURFACE 0x00400710337#define NV04_PGRAPH_NOTIFY 0x00400714338#define NV10_PGRAPH_STATE 0x00400714339#define NV10_PGRAPH_NOTIFY 0x00400718340 341#define NV04_PGRAPH_FIFO 0x00400720342 343#define NV04_PGRAPH_BPIXEL 0x00400724344#define NV10_PGRAPH_RDI_INDEX 0x00400750345#define NV04_PGRAPH_FFINTFC_ST2 0x00400754346#define NV10_PGRAPH_RDI_DATA 0x00400754347#define NV04_PGRAPH_DMA_PITCH 0x00400760348#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760349#define NV04_PGRAPH_DVD_COLORFMT 0x00400764350#define NV10_PGRAPH_FFINTFC_ST2 0x00400764351#define NV04_PGRAPH_SCALED_FORMAT 0x00400768352#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768353#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c354#define NV10_PGRAPH_DMA_PITCH 0x00400770355#define NV10_PGRAPH_DVD_COLORFMT 0x00400774356#define NV10_PGRAPH_SCALED_FORMAT 0x00400778357#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780358#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784359#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788360#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001361#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002362#define NV04_PGRAPH_PATT_COLOR0 0x00400800363#define NV04_PGRAPH_PATT_COLOR1 0x00400804364#define NV04_PGRAPH_PATTERN 0x00400808365#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810366#define NV04_PGRAPH_CHROMA 0x00400814367#define NV04_PGRAPH_CONTROL0 0x00400818368#define NV04_PGRAPH_CONTROL1 0x0040081C369#define NV04_PGRAPH_CONTROL2 0x00400820370#define NV04_PGRAPH_BLEND 0x00400824371#define NV04_PGRAPH_STORED_FMT 0x00400830372#define NV04_PGRAPH_PATT_COLORRAM 0x00400900373#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16))374#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16))375#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16))376#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16))377#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i))378#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))379#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))380#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))381#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))382#define NV04_PGRAPH_U_RAM 0x00400D00383#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16))384#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16))385#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16))386#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16))387#define NV04_PGRAPH_V_RAM 0x00400D40388#define NV04_PGRAPH_W_RAM 0x00400D80389#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40390#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44391#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48392#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C393#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50394#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54395#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58396#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C397#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60398#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64399#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68400#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C401#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00402#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20403#define NV10_PGRAPH_XFMODE0 0x00400F40404#define NV10_PGRAPH_XFMODE1 0x00400F44405#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48406#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C407#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50408#define NV10_PGRAPH_PIPE_DATA 0x00400F54409#define NV04_PGRAPH_DMA_START_0 0x00401000410#define NV04_PGRAPH_DMA_START_1 0x00401004411#define NV04_PGRAPH_DMA_LENGTH 0x00401008412#define NV04_PGRAPH_DMA_MISC 0x0040100C413#define NV04_PGRAPH_DMA_DATA_0 0x00401020414#define NV04_PGRAPH_DMA_DATA_1 0x00401024415#define NV04_PGRAPH_DMA_RM 0x00401030416#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040417#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044418#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048419#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C420#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050421#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054422#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058423#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C424#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060425#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080426#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084427#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088428#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C429#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090430#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094431#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098432#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C433#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0434#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16))435#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16))436#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16))437#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16))438 439 440/* It's a guess that this works on NV03. Confirmed on NV04, though */441#define NV04_PFIFO_DELAY_0 0x00002040442#define NV04_PFIFO_DMA_TIMESLICE 0x00002044443#define NV04_PFIFO_NEXT_CHANNEL 0x00002050444#define NV03_PFIFO_INTR_0 0x00002100445#define NV03_PFIFO_INTR_EN_0 0x00002140446# define NV_PFIFO_INTR_CACHE_ERROR (1<<0)447# define NV_PFIFO_INTR_RUNOUT (1<<4)448# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8)449# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)450# define NV_PFIFO_INTR_DMA_PT (1<<16)451# define NV_PFIFO_INTR_SEMAPHORE (1<<20)452# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)453#define NV03_PFIFO_RAMHT 0x00002210454#define NV03_PFIFO_RAMFC 0x00002214455#define NV03_PFIFO_RAMRO 0x00002218456#define NV40_PFIFO_RAMFC 0x00002220457#define NV03_PFIFO_CACHES 0x00002500458#define NV04_PFIFO_MODE 0x00002504459#define NV04_PFIFO_DMA 0x00002508460#define NV04_PFIFO_SIZE 0x0000250c461#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)462#define NV50_PFIFO_CTX_TABLE__SIZE 128463#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31)464#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30)465#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF466#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF467#define NV03_PFIFO_CACHE0_PUSH0 0x00003000468#define NV03_PFIFO_CACHE0_PULL0 0x00003040469#define NV04_PFIFO_CACHE0_PULL0 0x00003050470#define NV04_PFIFO_CACHE0_PULL1 0x00003054471#define NV03_PFIFO_CACHE1_PUSH0 0x00003200472#define NV03_PFIFO_CACHE1_PUSH1 0x00003204473#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8)474#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16)475#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f476#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f477#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f478#define NV03_PFIFO_CACHE1_PUT 0x00003210479#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220480#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224481# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000482# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008483# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010484# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018485# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020486# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028487# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030488# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038489# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040490# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048491# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050492# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058493# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060494# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068495# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070496# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078497# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080498# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088499# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090500# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098501# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0502# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8503# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0504# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8505# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0506# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8507# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0508# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8509# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0510# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8511# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0512# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8513# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000514# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000515# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000516# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000517# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000518# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000519# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000520# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000521# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000522# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000523# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000524# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000525# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000526# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000527# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000528# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000529# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000530# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000531# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000532# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000533# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000534# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000535# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000536# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000537# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000538# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000539# define NV_PFIFO_CACHE1_ENDIAN 0x80000000540# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF541# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000542#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228543#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c544#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230545#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240546#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244547#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248548#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C549#define NV03_PFIFO_CACHE1_PULL0 0x00003240550#define NV04_PFIFO_CACHE1_PULL0 0x00003250551# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010552# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000553#define NV03_PFIFO_CACHE1_PULL1 0x00003250554#define NV04_PFIFO_CACHE1_PULL1 0x00003254555#define NV04_PFIFO_CACHE1_HASH 0x00003258556#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260557#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264558#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268559#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C560#define NV03_PFIFO_CACHE1_GET 0x00003270561#define NV04_PFIFO_CACHE1_ENGINE 0x00003280562#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0563#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0564#define NV40_PFIFO_UNK32E4 0x000032E4565#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))566#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))567#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))568#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))569 570#define NV_CRTC0_INTSTAT 0x00600100571#define NV_CRTC0_INTEN 0x00600140572#define NV_CRTC1_INTSTAT 0x00602100573#define NV_CRTC1_INTEN 0x00602140574# define NV_CRTC_INTR_VBLANK (1<<0)575 576#define NV04_PRAMIN 0x00700000577 578/* Fifo commands. These are not regs, neither masks */579#define NV03_FIFO_CMD_JUMP 0x20000000580#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc581#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))582 583/* This is a partial import from rules-ng, a few things may be duplicated.584 * Eventually we should completely import everything from rules-ng.585 * For the moment check rules-ng for docs.586 */587 588#define NV50_PMC 0x00000000589#define NV50_PMC__LEN 0x1590#define NV50_PMC__ESIZE 0x2000591# define NV50_PMC_BOOT_0 0x00000000592# define NV50_PMC_BOOT_0_REVISION 0x000000ff593# define NV50_PMC_BOOT_0_REVISION__SHIFT 0594# define NV50_PMC_BOOT_0_ARCH 0x0ff00000595# define NV50_PMC_BOOT_0_ARCH__SHIFT 20596# define NV50_PMC_INTR_0 0x00000100597# define NV50_PMC_INTR_0_PFIFO (1<<8)598# define NV50_PMC_INTR_0_PGRAPH (1<<12)599# define NV50_PMC_INTR_0_PTIMER (1<<20)600# define NV50_PMC_INTR_0_HOTPLUG (1<<21)601# define NV50_PMC_INTR_0_DISPLAY (1<<26)602# define NV50_PMC_INTR_EN_0 0x00000140603# define NV50_PMC_INTR_EN_0_MASTER (1<<0)604# define NV50_PMC_INTR_EN_0_MASTER_DISABLED (0<<0)605# define NV50_PMC_INTR_EN_0_MASTER_ENABLED (1<<0)606# define NV50_PMC_ENABLE 0x00000200607# define NV50_PMC_ENABLE_PFIFO (1<<8)608# define NV50_PMC_ENABLE_PGRAPH (1<<12)609 610#define NV50_PCONNECTOR 0x0000e000611#define NV50_PCONNECTOR__LEN 0x1612#define NV50_PCONNECTOR__ESIZE 0x1000613# define NV50_PCONNECTOR_HOTPLUG_INTR 0x0000e050614# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0 (1<<0)615# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1 (1<<1)616# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2 (1<<2)617# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3 (1<<3)618# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 (1<<16)619# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 (1<<17)620# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2 (1<<18)621# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3 (1<<19)622# define NV50_PCONNECTOR_HOTPLUG_CTRL 0x0000e054623# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 (1<<0)624# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 (1<<1)625# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2 (1<<2)626# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3 (1<<3)627# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 (1<<16)628# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 (1<<17)629# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2 (1<<18)630# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3 (1<<19)631# define NV50_PCONNECTOR_HOTPLUG_STATE 0x0000e104632# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 (1<<2)633# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 (1<<6)634# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 (1<<10)635# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 (1<<14)636# define NV50_PCONNECTOR_I2C_PORT_0 0x0000e138637# define NV50_PCONNECTOR_I2C_PORT_1 0x0000e150638# define NV50_PCONNECTOR_I2C_PORT_2 0x0000e168639# define NV50_PCONNECTOR_I2C_PORT_3 0x0000e180640# define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240641# define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258642 643#define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0)644#define NV50_AUXCH_DATA_OUT__SIZE 4645#define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0)646#define NV50_AUXCH_DATA_IN__SIZE 4647#define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0)648#define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4)649#define NV50_AUXCH_CTRL_LINKSTAT 0x01000000650#define NV50_AUXCH_CTRL_LINKSTAT_NOT_READY 0x00000000651#define NV50_AUXCH_CTRL_LINKSTAT_READY 0x01000000652#define NV50_AUXCH_CTRL_LINKEN 0x00100000653#define NV50_AUXCH_CTRL_LINKEN_DISABLED 0x00000000654#define NV50_AUXCH_CTRL_LINKEN_ENABLED 0x00100000655#define NV50_AUXCH_CTRL_EXEC 0x00010000656#define NV50_AUXCH_CTRL_EXEC_COMPLETE 0x00000000657#define NV50_AUXCH_CTRL_EXEC_IN_PROCESS 0x00010000658#define NV50_AUXCH_CTRL_CMD 0x0000f000659#define NV50_AUXCH_CTRL_CMD_SHIFT 12660#define NV50_AUXCH_CTRL_LEN 0x0000000f661#define NV50_AUXCH_CTRL_LEN_SHIFT 0662#define NV50_AUXCH_STAT(i) ((i) * 0x50 + 0x0000e4e8)663#define NV50_AUXCH_STAT_STATE 0x10000000664#define NV50_AUXCH_STAT_STATE_NOT_READY 0x00000000665#define NV50_AUXCH_STAT_STATE_READY 0x10000000666#define NV50_AUXCH_STAT_REPLY 0x000f0000667#define NV50_AUXCH_STAT_REPLY_AUX 0x00030000668#define NV50_AUXCH_STAT_REPLY_AUX_ACK 0x00000000669#define NV50_AUXCH_STAT_REPLY_AUX_NACK 0x00010000670#define NV50_AUXCH_STAT_REPLY_AUX_DEFER 0x00020000671#define NV50_AUXCH_STAT_REPLY_I2C 0x000c0000672#define NV50_AUXCH_STAT_REPLY_I2C_ACK 0x00000000673#define NV50_AUXCH_STAT_REPLY_I2C_NACK 0x00040000674#define NV50_AUXCH_STAT_REPLY_I2C_DEFER 0x00080000675#define NV50_AUXCH_STAT_COUNT 0x0000001f676 677#define NV50_PBUS 0x00088000678#define NV50_PBUS__LEN 0x1679#define NV50_PBUS__ESIZE 0x1000680# define NV50_PBUS_PCI_ID 0x00088000681# define NV50_PBUS_PCI_ID_VENDOR_ID 0x0000ffff682# define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT 0683# define NV50_PBUS_PCI_ID_DEVICE_ID 0xffff0000684# define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT 16685 686#define NV50_PFB 0x00100000687#define NV50_PFB__LEN 0x1688#define NV50_PFB__ESIZE 0x1000689 690#define NV50_PEXTDEV 0x00101000691#define NV50_PEXTDEV__LEN 0x1692#define NV50_PEXTDEV__ESIZE 0x1000693 694#define NV50_PROM 0x00300000695#define NV50_PROM__LEN 0x1696#define NV50_PROM__ESIZE 0x10000697 698#define NV50_PGRAPH 0x00400000699#define NV50_PGRAPH__LEN 0x1700#define NV50_PGRAPH__ESIZE 0x10000701 702#define NV50_PDISPLAY 0x00610000703#define NV50_PDISPLAY_OBJECTS 0x00610010704#define NV50_PDISPLAY_INTR_0 0x00610020705#define NV50_PDISPLAY_INTR_1 0x00610024706#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC 0x0000000c707#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_SHIFT 2708#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(n) (1 << ((n) + 2))709#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0 0x00000004710#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1 0x00000008711#define NV50_PDISPLAY_INTR_1_CLK_UNK10 0x00000010712#define NV50_PDISPLAY_INTR_1_CLK_UNK20 0x00000020713#define NV50_PDISPLAY_INTR_1_CLK_UNK40 0x00000040714#define NV50_PDISPLAY_INTR_EN_0 0x00610028715#define NV50_PDISPLAY_INTR_EN_1 0x0061002c716#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC 0x0000000c717#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(n) (1 << ((n) + 2))718#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_0 0x00000004719#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_1 0x00000008720#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 0x00000010721#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 0x00000020722#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK40 0x00000040723#define NV50_PDISPLAY_UNK30_CTRL 0x00610030724#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0 0x00000200725#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1 0x00000400726#define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000727#define NV50_PDISPLAY_TRAPPED_ADDR(i) ((i) * 0x08 + 0x00610080)728#define NV50_PDISPLAY_TRAPPED_DATA(i) ((i) * 0x08 + 0x00610084)729#define NV50_PDISPLAY_EVO_CTRL(i) ((i) * 0x10 + 0x00610200)730#define NV50_PDISPLAY_EVO_CTRL_DMA 0x00000010731#define NV50_PDISPLAY_EVO_CTRL_DMA_DISABLED 0x00000000732#define NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED 0x00000010733#define NV50_PDISPLAY_EVO_DMA_CB(i) ((i) * 0x10 + 0x00610204)734#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION 0x00000002735#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM 0x00000000736#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_SYSTEM 0x00000002737#define NV50_PDISPLAY_EVO_DMA_CB_VALID 0x00000001738#define NV50_PDISPLAY_EVO_UNK2(i) ((i) * 0x10 + 0x00610208)739#define NV50_PDISPLAY_EVO_HASH_TAG(i) ((i) * 0x10 + 0x0061020c)740 741#define NV50_PDISPLAY_CURSOR 0x00610270742#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270)743#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON 0x00000001744#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS 0x00030000745#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE 0x00010000746 747#define NV50_PDISPLAY_PIO_CTRL 0x00610300748#define NV50_PDISPLAY_PIO_CTRL_PENDING 0x80000000749#define NV50_PDISPLAY_PIO_CTRL_MTHD 0x00001ffc750#define NV50_PDISPLAY_PIO_CTRL_ENABLED 0x00000001751#define NV50_PDISPLAY_PIO_DATA 0x00610304752 753#define NV50_PDISPLAY_CRTC_P(i, r) ((i) * 0x540 + NV50_PDISPLAY_CRTC_##r)754#define NV50_PDISPLAY_CRTC_C(i, r) (4 + (i) * 0x540 + NV50_PDISPLAY_CRTC_##r)755#define NV50_PDISPLAY_CRTC_UNK_0A18 /* mthd 0x0900 */ 0x00610a18756#define NV50_PDISPLAY_CRTC_CLUT_MODE 0x00610a24757#define NV50_PDISPLAY_CRTC_INTERLACE 0x00610a48758#define NV50_PDISPLAY_CRTC_SCALE_CTRL 0x00610a50759#define NV50_PDISPLAY_CRTC_CURSOR_CTRL 0x00610a58760#define NV50_PDISPLAY_CRTC_UNK0A78 /* mthd 0x0904 */ 0x00610a78761#define NV50_PDISPLAY_CRTC_UNK0AB8 0x00610ab8762#define NV50_PDISPLAY_CRTC_DEPTH 0x00610ac8763#define NV50_PDISPLAY_CRTC_CLOCK 0x00610ad0764#define NV50_PDISPLAY_CRTC_COLOR_CTRL 0x00610ae0765#define NV50_PDISPLAY_CRTC_SYNC_START_TO_BLANK_END 0x00610ae8766#define NV50_PDISPLAY_CRTC_MODE_UNK1 0x00610af0767#define NV50_PDISPLAY_CRTC_DISPLAY_TOTAL 0x00610af8768#define NV50_PDISPLAY_CRTC_SYNC_DURATION 0x00610b00769#define NV50_PDISPLAY_CRTC_MODE_UNK2 0x00610b08770#define NV50_PDISPLAY_CRTC_UNK_0B10 /* mthd 0x0828 */ 0x00610b10771#define NV50_PDISPLAY_CRTC_FB_SIZE 0x00610b18772#define NV50_PDISPLAY_CRTC_FB_PITCH 0x00610b20773#define NV50_PDISPLAY_CRTC_FB_PITCH_LINEAR 0x00100000774#define NV50_PDISPLAY_CRTC_FB_POS 0x00610b28775#define NV50_PDISPLAY_CRTC_SCALE_CENTER_OFFSET 0x00610b38776#define NV50_PDISPLAY_CRTC_REAL_RES 0x00610b40777#define NV50_PDISPLAY_CRTC_SCALE_RES1 0x00610b48778#define NV50_PDISPLAY_CRTC_SCALE_RES2 0x00610b50779 780#define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8)781#define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8)782#define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8)783#define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8)784#define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8)785#define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8)786#define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8)787#define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8)788#define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8)789#define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8)790 791#define NV50_PDISPLAY_CRTC_CLK 0x00614000792#define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100)793#define NV50_PDISPLAY_CRTC_CLK_CTRL1_CONNECTED 0x00000600794#define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104)795#define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108)796#define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200)797 798#define NV50_PDISPLAY_DAC_CLK 0x00614000799#define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280)800 801#define NV50_PDISPLAY_SOR_CLK 0x00614000802#define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300)803 804#define NV50_PDISPLAY_VGACRTC(r) ((r) + 0x619400)805 806#define NV50_PDISPLAY_DAC 0x0061a000807#define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800)808#define NV50_PDISPLAY_DAC_DPMS_CTRL_HSYNC_OFF 0x00000001809#define NV50_PDISPLAY_DAC_DPMS_CTRL_VSYNC_OFF 0x00000004810#define NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED 0x00000010811#define NV50_PDISPLAY_DAC_DPMS_CTRL_OFF 0x00000040812#define NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING 0x80000000813#define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800)814#define NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE 0x00100000815#define NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT 0x38000000816#define NV50_PDISPLAY_DAC_LOAD_CTRL_DONE 0x80000000817#define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800)818#define NV50_PDISPLAY_DAC_CLK_CTRL1_CONNECTED 0x00000600819 820#define NV50_PDISPLAY_SOR 0x0061c000821#define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800)822#define NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING 0x80000000823#define NV50_PDISPLAY_SOR_DPMS_CTRL_ON 0x00000001824#define NV50_PDISPLAY_SOR_CLK_CTRL1(i) (0x0061c008 + (i) * 0x800)825#define NV50_PDISPLAY_SOR_CLK_CTRL1_CONNECTED 0x00000600826#define NV50_PDISPLAY_SOR_DPMS_STATE(i) (0x0061c030 + (i) * 0x800)827#define NV50_PDISPLAY_SOR_DPMS_STATE_ACTIVE 0x00030000828#define NV50_PDISPLAY_SOR_DPMS_STATE_BLANKED 0x00080000829#define NV50_PDISPLAY_SOR_DPMS_STATE_WAIT 0x10000000830#define NV50_PDISP_SOR_PWM_DIV(i) (0x0061c080 + (i) * 0x800)831#define NV50_PDISP_SOR_PWM_CTL(i) (0x0061c084 + (i) * 0x800)832#define NV50_PDISP_SOR_PWM_CTL_NEW 0x80000000833#define NVA3_PDISP_SOR_PWM_CTL_UNK 0x40000000834#define NV50_PDISP_SOR_PWM_CTL_VAL 0x000007ff835#define NVA3_PDISP_SOR_PWM_CTL_VAL 0x00ffffff836#define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)837#define NV50_SOR_DP_CTRL_ENABLED 0x00000001838#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000839#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000840#define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000841#define NV50_SOR_DP_CTRL_LANE_1_ENABLED 0x00020000842#define NV50_SOR_DP_CTRL_LANE_2_ENABLED 0x00040000843#define NV50_SOR_DP_CTRL_LANE_3_ENABLED 0x00080000844#define NV50_SOR_DP_CTRL_TRAINING_PATTERN 0x0f000000845#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000846#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000847#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000848#define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80)849#define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80)850#define NV50_SOR_DP_SCFG(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80)851#define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80)852 853#define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)854#define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)855#define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004)856 857#define NV50_PDISPLAY_CURSOR_USER 0x00647000858#define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080)859#define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084)860