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1/* fuc microcode for copy engine on gt215- chipsets2 *3 * Copyright 2011 Red Hat Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: Ben Skeggs24 */25 26#ifdef GT21527.section #gt215_ce_data28#else29.section #gf100_ce_data30#endif31 32ctx_object: .b32 033#ifdef GT21534ctx_dma:35ctx_dma_query: .b32 036ctx_dma_src: .b32 037ctx_dma_dst: .b32 038#endif39.equ #ctx_dma_count 340ctx_query_address_high: .b32 041ctx_query_address_low: .b32 042ctx_query_counter: .b32 043ctx_src_address_high: .b32 044ctx_src_address_low: .b32 045ctx_src_pitch: .b32 046ctx_src_tile_mode: .b32 047ctx_src_xsize: .b32 048ctx_src_ysize: .b32 049ctx_src_zsize: .b32 050ctx_src_zoff: .b32 051ctx_src_xoff: .b32 052ctx_src_yoff: .b32 053ctx_src_cpp: .b32 054ctx_dst_address_high: .b32 055ctx_dst_address_low: .b32 056ctx_dst_pitch: .b32 057ctx_dst_tile_mode: .b32 058ctx_dst_xsize: .b32 059ctx_dst_ysize: .b32 060ctx_dst_zsize: .b32 061ctx_dst_zoff: .b32 062ctx_dst_xoff: .b32 063ctx_dst_yoff: .b32 064ctx_dst_cpp: .b32 065ctx_format: .b32 066ctx_swz_const0: .b32 067ctx_swz_const1: .b32 068ctx_xcnt: .b32 069ctx_ycnt: .b32 070.align 25671 72dispatch_table:73// mthd 0x0000, NAME74.b16 0x000 175.b32 #ctx_object ~0xffffffff76// mthd 0x0100, NOP77.b16 0x040 178.b32 0x00010000 + #cmd_nop ~0xffffffff79// mthd 0x0140, PM_TRIGGER80.b16 0x050 181.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff82#ifdef GT21583// mthd 0x0180-0x018c, DMA_84.b16 0x060 #ctx_dma_count85dispatch_dma:86.b32 0x00010000 + #cmd_dma ~0xffffffff87.b32 0x00010000 + #cmd_dma ~0xffffffff88.b32 0x00010000 + #cmd_dma ~0xffffffff89#endif90// mthd 0x0200-0x0218, SRC_TILE91.b16 0x80 792.b32 #ctx_src_tile_mode ~0x00000fff93.b32 #ctx_src_xsize ~0x0007ffff94.b32 #ctx_src_ysize ~0x00001fff95.b32 #ctx_src_zsize ~0x000007ff96.b32 #ctx_src_zoff ~0x00000fff97.b32 #ctx_src_xoff ~0x0007ffff98.b32 #ctx_src_yoff ~0x00001fff99// mthd 0x0220-0x0238, DST_TILE100.b16 0x88 7101.b32 #ctx_dst_tile_mode ~0x00000fff102.b32 #ctx_dst_xsize ~0x0007ffff103.b32 #ctx_dst_ysize ~0x00001fff104.b32 #ctx_dst_zsize ~0x000007ff105.b32 #ctx_dst_zoff ~0x00000fff106.b32 #ctx_dst_xoff ~0x0007ffff107.b32 #ctx_dst_yoff ~0x00001fff108// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH109.b16 0xc0 2110.b32 0x00010000 + #cmd_exec ~0xffffffff111.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff112// mthd 0x030c-0x0340, various stuff113.b16 0xc3 14114.b32 #ctx_src_address_high ~0x000000ff115.b32 #ctx_src_address_low ~0xffffffff116.b32 #ctx_dst_address_high ~0x000000ff117.b32 #ctx_dst_address_low ~0xffffffff118.b32 #ctx_src_pitch ~0x0007ffff119.b32 #ctx_dst_pitch ~0x0007ffff120.b32 #ctx_xcnt ~0x0000ffff121.b32 #ctx_ycnt ~0x00001fff122.b32 #ctx_format ~0x0333ffff123.b32 #ctx_swz_const0 ~0xffffffff124.b32 #ctx_swz_const1 ~0xffffffff125.b32 #ctx_query_address_high ~0x000000ff126.b32 #ctx_query_address_low ~0xffffffff127.b32 #ctx_query_counter ~0xffffffff128.b16 0x800 0129 130#ifdef GT215131.section #gt215_ce_code132#else133.section #gf100_ce_code134#endif135 136main:137 clear b32 $r0138 mov $sp $r0139 140 // setup i0 handler and route fifo and ctxswitch to it141 mov $r1 #ih142 mov $iv0 $r1143 mov $r1 0x400144 movw $r2 0xfff3145 sethi $r2 0146 iowr I[$r1 + 0x300] $r2147 148 // enable interrupts149 or $r2 0xc150 iowr I[$r1] $r2151 bset $flags ie0152 153 // enable fifo access and context switching154 mov $r1 0x1200155 mov $r2 3156 iowr I[$r1] $r2157 158 // sleep forever, waking for interrupts159 bset $flags $p0160 spin:161 sleep $p0162 bra #spin163 164// i0 handler165ih:166 iord $r1 I[$r0 + 0x200]167 168 and $r2 $r1 0x00000008169 bra e #ih_no_chsw170 call #chsw171 ih_no_chsw:172 and $r2 $r1 0x00000004173 bra e #ih_no_cmd174 call #dispatch175 176 ih_no_cmd:177 and $r1 $r1 0x0000000c178 iowr I[$r0 + 0x100] $r1179 iret180 181// $p1 direction (0 = unload, 1 = load)182// $r3 channel183swctx:184 mov $r4 0x7700185 mov $xtargets $r4186#ifdef GT215187 // target 7 hardcoded to ctx dma object188 mov $xdbase $r0189#else190 // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1191 mov $r4 0x2100192 iord $r4 I[$r4 + 0]193 and $r4 1194 shl b32 $r4 4195 add b32 $r4 0x30196 197 // channel is in vram198 mov $r15 0x61c199 shl b32 $r15 6200 mov $r5 0x114201 iowrs I[$r15] $r5202 203 // read 16-byte PCOPYn info, containing context pointer, from channel204 shl b32 $r5 $r3 4205 add b32 $r5 2206 mov $xdbase $r5207 mov $r5 $sp208 // get a chunk of stack space, aligned to 256 byte boundary209 sub b32 $r5 0x100210 mov $r6 0xff211 not b32 $r6212 and $r5 $r6213 sethi $r5 0x00020000214 xdld $r4 $r5215 xdwait216 sethi $r5 0217 218 // set context pointer, from within channel VM219 mov $r14 0220 iowrs I[$r15] $r14221 ld b32 $r4 D[$r5 + 0]222 shr b32 $r4 8223 ld b32 $r6 D[$r5 + 4]224 shl b32 $r6 24225 or $r4 $r6226 mov $xdbase $r4227#endif228 // 256-byte context, at start of data segment229 mov b32 $r4 $r0230 sethi $r4 0x60000231 232 // swap!233 bra $p1 #swctx_load234 xdst $r0 $r4235 bra #swctx_done236 swctx_load:237 xdld $r0 $r4238 swctx_done:239 xdwait240 ret241 242chsw:243 // read current channel244 mov $r2 0x1400245 iord $r3 I[$r2]246 247 // if it's active, unload it and return248 xbit $r15 $r3 0x1e249 bra e #chsw_no_unload250 bclr $flags $p1251 call #swctx252 bclr $r3 0x1e253 iowr I[$r2] $r3254 mov $r4 1255 iowr I[$r2 + 0x200] $r4256 ret257 258 // read next channel259 chsw_no_unload:260 iord $r3 I[$r2 + 0x100]261 262 // is there a channel waiting to be loaded?263 xbit $r13 $r3 0x1e264 bra e #chsw_finish_load265 bset $flags $p1266 call #swctx267#ifdef GT215268 // load dma objects back into TARGET regs269 mov $r5 #ctx_dma270 mov $r6 #ctx_dma_count271 chsw_load_ctx_dma:272 ld b32 $r7 D[$r5 + $r6 * 4]273 add b32 $r8 $r6 0x180274 shl b32 $r8 8275 iowr I[$r8] $r7276 sub b32 $r6 1277 bra nc #chsw_load_ctx_dma278#endif279 chsw_finish_load:280 mov $r3 2281 iowr I[$r2 + 0x200] $r3282 ret283 284dispatch:285 // read incoming fifo command286 mov $r3 0x1900287 iord $r2 I[$r3 + 0x100]288 iord $r3 I[$r3 + 0x000]289 and $r4 $r2 0x7ff290 // $r2 will be used to store exception data291 shl b32 $r2 0x10292 293 // lookup method in the dispatch table, ILLEGAL_MTHD if not found294 mov $r5 #dispatch_table295 clear b32 $r6296 clear b32 $r7297 dispatch_loop:298 ld b16 $r6 D[$r5 + 0]299 ld b16 $r7 D[$r5 + 2]300 add b32 $r5 4301 cmpu b32 $r4 $r6302 bra c #dispatch_illegal_mthd303 add b32 $r7 $r6304 cmpu b32 $r4 $r7305 bra c #dispatch_valid_mthd306 sub b32 $r7 $r6307 shl b32 $r7 3308 add b32 $r5 $r7309 bra #dispatch_loop310 311 // ensure no bits set in reserved fields, INVALID_BITFIELD312 dispatch_valid_mthd:313 sub b32 $r4 $r6314 shl b32 $r4 3315 add b32 $r4 $r5316 ld b32 $r5 D[$r4 + 4]317 and $r5 $r3318 cmpu b32 $r5 0319 bra ne #dispatch_invalid_bitfield320 321 // depending on dispatch flags: execute method, or save data as state322 ld b16 $r5 D[$r4 + 0]323 ld b16 $r6 D[$r4 + 2]324 cmpu b32 $r6 0325 bra ne #dispatch_cmd326 st b32 D[$r5] $r3327 bra #dispatch_done328 dispatch_cmd:329 bclr $flags $p1330 call $r5331 bra $p1 #dispatch_error332 bra #dispatch_done333 334 dispatch_invalid_bitfield:335 or $r2 2336 dispatch_illegal_mthd:337 or $r2 1338 339 // store exception data in SCRATCH0/SCRATCH1, signal hostirq340 dispatch_error:341 mov $r4 0x1000342 iowr I[$r4 + 0x000] $r2343 iowr I[$r4 + 0x100] $r3344 mov $r2 0x40345 iowr I[$r0] $r2346 hostirq_wait:347 iord $r2 I[$r0 + 0x200]348 and $r2 0x40349 cmpu b32 $r2 0350 bra ne #hostirq_wait351 352 dispatch_done:353 mov $r2 0x1d00354 mov $r3 1355 iowr I[$r2] $r3356 ret357 358// No-operation359//360// Inputs:361// $r1: irqh state362// $r2: hostirq state363// $r3: data364// $r4: dispatch table entry365// Outputs:366// $r1: irqh state367// $p1: set on error368// $r2: hostirq state369// $r3: data370cmd_nop:371 ret372 373// PM_TRIGGER374//375// Inputs:376// $r1: irqh state377// $r2: hostirq state378// $r3: data379// $r4: dispatch table entry380// Outputs:381// $r1: irqh state382// $p1: set on error383// $r2: hostirq state384// $r3: data385cmd_pm_trigger:386 mov $r2 0x2200387 clear b32 $r3388 sethi $r3 0x20000389 iowr I[$r2] $r3390 ret391 392#ifdef GT215393// SET_DMA_* method handler394//395// Inputs:396// $r1: irqh state397// $r2: hostirq state398// $r3: data399// $r4: dispatch table entry400// Outputs:401// $r1: irqh state402// $p1: set on error403// $r2: hostirq state404// $r3: data405cmd_dma:406 sub b32 $r4 #dispatch_dma407 shr b32 $r4 1408 bset $r3 0x1e409 st b32 D[$r4 + #ctx_dma] $r3410 add b32 $r4 0x600411 shl b32 $r4 6412 iowr I[$r4] $r3413 ret414#endif415 416// Calculates the hw swizzle mask and adjusts the surface's xcnt to match417//418cmd_exec_set_format:419 // zero out a chunk of the stack to store the swizzle into420 add $sp -0x10421 st b32 D[$sp + 0x00] $r0422 st b32 D[$sp + 0x04] $r0423 st b32 D[$sp + 0x08] $r0424 st b32 D[$sp + 0x0c] $r0425 426 // extract cpp, src_ncomp and dst_ncomp from FORMAT427 ld b32 $r4 D[$r0 + #ctx_format]428 extr $r5 $r4 16:17429 add b32 $r5 1430 extr $r6 $r4 20:21431 add b32 $r6 1432 extr $r7 $r4 24:25433 add b32 $r7 1434 435 // convert FORMAT swizzle mask to hw swizzle mask436 bclr $flags $p2437 clear b32 $r8438 clear b32 $r9439 ncomp_loop:440 and $r10 $r4 0xf441 shr b32 $r4 4442 clear b32 $r11443 bpc_loop:444 cmpu b8 $r10 4445 bra nc #cmp_c0446 mulu $r12 $r10 $r5447 add b32 $r12 $r11448 bset $flags $p2449 bra #bpc_next450 cmp_c0:451 bra ne #cmp_c1452 mov $r12 0x10453 add b32 $r12 $r11454 bra #bpc_next455 cmp_c1:456 cmpu b8 $r10 6457 bra nc #cmp_zero458 mov $r12 0x14459 add b32 $r12 $r11460 bra #bpc_next461 cmp_zero:462 mov $r12 0x80463 bpc_next:464 st b8 D[$sp + $r8] $r12465 add b32 $r8 1466 add b32 $r11 1467 cmpu b32 $r11 $r5468 bra c #bpc_loop469 add b32 $r9 1470 cmpu b32 $r9 $r7471 bra c #ncomp_loop472 473 // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)474 mulu $r6 $r5475 st b32 D[$r0 + #ctx_src_cpp] $r6476 ld b32 $r8 D[$r0 + #ctx_xcnt]477 mulu $r6 $r8478 bra $p2 #dst_xcnt479 clear b32 $r6480 481 dst_xcnt:482 mulu $r7 $r5483 st b32 D[$r0 + #ctx_dst_cpp] $r7484 mulu $r7 $r8485 486 mov $r5 0x810487 shl b32 $r5 6488 iowr I[$r5 + 0x000] $r6489 iowr I[$r5 + 0x100] $r7490 add b32 $r5 0x800491 ld b32 $r6 D[$r0 + #ctx_dst_cpp]492 sub b32 $r6 1493 shl b32 $r6 8494 ld b32 $r7 D[$r0 + #ctx_src_cpp]495 sub b32 $r7 1496 or $r6 $r7497 iowr I[$r5 + 0x000] $r6498 add b32 $r5 0x100499 ld b32 $r6 D[$sp + 0x00]500 iowr I[$r5 + 0x000] $r6501 ld b32 $r6 D[$sp + 0x04]502 iowr I[$r5 + 0x100] $r6503 ld b32 $r6 D[$sp + 0x08]504 iowr I[$r5 + 0x200] $r6505 ld b32 $r6 D[$sp + 0x0c]506 iowr I[$r5 + 0x300] $r6507 add b32 $r5 0x400508 ld b32 $r6 D[$r0 + #ctx_swz_const0]509 iowr I[$r5 + 0x000] $r6510 ld b32 $r6 D[$r0 + #ctx_swz_const1]511 iowr I[$r5 + 0x100] $r6512 add $sp 0x10513 ret514 515// Setup to handle a tiled surface516//517// Calculates a number of parameters the hardware requires in order518// to correctly handle tiling.519//520// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE):521// nTx = round_up(w * cpp, 1 << Tp) >> Tp522// nTy = round_up(h, 1 << Th) >> Th523// Txo = (x * cpp) & ((1 << Tp) - 1)524// Tx = (x * cpp) >> Tp525// Tyo = y & ((1 << Th) - 1)526// Ty = y >> Th527// Tzo = z & ((1 << Td) - 1)528// Tz = z >> Td529//530// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo531// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp;532//533// Inputs:534// $r4: hw command (0x104800)535// $r5: ctx offset adjustment for src/dst selection536// $p2: set if dst surface537//538cmd_exec_set_surface_tiled:539 // translate TILE_MODE into Tp, Th, Td shift values540 ld b32 $r7 D[$r5 + #ctx_src_tile_mode]541 extr $r9 $r7 8:11542 extr $r8 $r7 4:7543#ifdef GT215544 add b32 $r8 2545#else546 add b32 $r8 3547#endif548 extr $r7 $r7 0:3549 cmp b32 $r7 0xe550 bra ne #xtile64551 mov $r7 4552 bra #xtileok553 xtile64:554 xbit $r7 $flags $p2555 add b32 $r7 17556 bset $r4 $r7557 mov $r7 6558 xtileok:559 560 // Op = (x * cpp) & ((1 << Tp) - 1)561 // Tx = (x * cpp) >> Tp562 ld b32 $r10 D[$r5 + #ctx_src_xoff]563 ld b32 $r11 D[$r5 + #ctx_src_cpp]564 mulu $r10 $r11565 mov $r11 1566 shl b32 $r11 $r7567 sub b32 $r11 1568 and $r12 $r10 $r11569 shr b32 $r10 $r7570 571 // Tyo = y & ((1 << Th) - 1)572 // Ty = y >> Th573 ld b32 $r13 D[$r5 + #ctx_src_yoff]574 mov $r14 1575 shl b32 $r14 $r8576 sub b32 $r14 1577 and $r11 $r13 $r14578 shr b32 $r13 $r8579 580 // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo)581 add b32 $r14 1582 shl b32 $r15 $r14 12583 sub b32 $r14 $r11584 or $r15 $r14585 xbit $r6 $flags $p2586 add b32 $r6 0x208587 shl b32 $r6 8588 iowr I[$r6 + 0x000] $r15589 590 // Op += Tyo << Tp591 shl b32 $r11 $r7592 add b32 $r12 $r11593 594 // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)595 ld b32 $r15 D[$r5 + #ctx_src_xsize]596 ld b32 $r11 D[$r5 + #ctx_src_cpp]597 mulu $r15 $r11598 mov $r11 1599 shl b32 $r11 $r7600 sub b32 $r11 1601 add b32 $r15 $r11602 shr b32 $r15 $r7603 push $r15604 605 // nTy = (h + ((1 << Th) - 1)) >> Th606 ld b32 $r15 D[$r5 + #ctx_src_ysize]607 mov $r11 1608 shl b32 $r11 $r8609 sub b32 $r11 1610 add b32 $r15 $r11611 shr b32 $r15 $r8612 push $r15613 614 // Tys = Tp + Th615 // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td616 add b32 $r7 $r8617 sub b32 $r8 2618 mov $r11 1619 shl b32 $r11 $r8620 shl b32 $r11 $r9621 622 // Tzo = z & ((1 << Td) - 1)623 // Tz = z >> Td624 // Op += Tzo << Tys625 // Ts = Tys + Td626 ld b32 $r8 D[$r5 + #ctx_src_zoff]627 mov $r14 1628 shl b32 $r14 $r9629 sub b32 $r14 1630 and $r15 $r8 $r14631 shl b32 $r15 $r7632 add b32 $r12 $r15633 add b32 $r7 $r9634 shr b32 $r8 $r9635 636 // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts637 pop $r15638 pop $r9639 mulu $r13 $r9640 add b32 $r10 $r13641 mulu $r8 $r9642 mulu $r8 $r15643 add b32 $r10 $r8644 shl b32 $r10 $r7645 646 // PITCH = (nTx - 1) << Ts647 sub b32 $r9 1648 shl b32 $r9 $r7649 iowr I[$r6 + 0x200] $r9650 651 // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff652 // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16653 ld b32 $r7 D[$r5 + #ctx_src_address_low]654 ld b32 $r8 D[$r5 + #ctx_src_address_high]655 add b32 $r10 $r12656 add b32 $r7 $r10657 adc b32 $r8 0658 shl b32 $r8 16659 or $r8 $r11660 sub b32 $r6 0x600661 iowr I[$r6 + 0x000] $r7662 add b32 $r6 0x400663 iowr I[$r6 + 0x000] $r8664 ret665 666// Setup to handle a linear surface667//668// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting669//670cmd_exec_set_surface_linear:671 xbit $r6 $flags $p2672 add b32 $r6 0x202673 shl b32 $r6 8674 ld b32 $r7 D[$r5 + #ctx_src_address_low]675 iowr I[$r6 + 0x000] $r7676 add b32 $r6 0x400677 ld b32 $r7 D[$r5 + #ctx_src_address_high]678 shl b32 $r7 16679 iowr I[$r6 + 0x000] $r7680 add b32 $r6 0x400681 ld b32 $r7 D[$r5 + #ctx_src_pitch]682 iowr I[$r6 + 0x000] $r7683 ret684 685// wait for regs to be available for use686cmd_exec_wait:687 push $r0688 push $r1689 mov $r0 0x800690 shl b32 $r0 6691 loop:692 iord $r1 I[$r0]693 and $r1 1694 bra ne #loop695 pop $r1696 pop $r0697 ret698 699cmd_exec_query:700 // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }701 xbit $r4 $r3 13702 bra ne #query_counter703 call #cmd_exec_wait704 mov $r4 0x80c705 shl b32 $r4 6706 ld b32 $r5 D[$r0 + #ctx_query_address_low]707 add b32 $r5 4708 iowr I[$r4 + 0x000] $r5709 iowr I[$r4 + 0x100] $r0710 mov $r5 0xc711 iowr I[$r4 + 0x200] $r5712 add b32 $r4 0x400713 ld b32 $r5 D[$r0 + #ctx_query_address_high]714 shl b32 $r5 16715 iowr I[$r4 + 0x000] $r5716 add b32 $r4 0x500717 mov $r5 0x00000b00718 sethi $r5 0x00010000719 iowr I[$r4 + 0x000] $r5720 mov $r5 0x00004040721 shl b32 $r5 1722 sethi $r5 0x80800000723 iowr I[$r4 + 0x100] $r5724 mov $r5 0x00001110725 sethi $r5 0x13120000726 iowr I[$r4 + 0x200] $r5727 mov $r5 0x00001514728 sethi $r5 0x17160000729 iowr I[$r4 + 0x300] $r5730 mov $r5 0x00002601731 sethi $r5 0x00010000732 mov $r4 0x800733 shl b32 $r4 6734 iowr I[$r4 + 0x000] $r5735 736 // write COUNTER737 query_counter:738 call #cmd_exec_wait739 mov $r4 0x80c740 shl b32 $r4 6741 ld b32 $r5 D[$r0 + #ctx_query_address_low]742 iowr I[$r4 + 0x000] $r5743 iowr I[$r4 + 0x100] $r0744 mov $r5 0x4745 iowr I[$r4 + 0x200] $r5746 add b32 $r4 0x400747 ld b32 $r5 D[$r0 + #ctx_query_address_high]748 shl b32 $r5 16749 iowr I[$r4 + 0x000] $r5750 add b32 $r4 0x500751 mov $r5 0x00000300752 iowr I[$r4 + 0x000] $r5753 mov $r5 0x00001110754 sethi $r5 0x13120000755 iowr I[$r4 + 0x100] $r5756 ld b32 $r5 D[$r0 + #ctx_query_counter]757 add b32 $r4 0x500758 iowr I[$r4 + 0x000] $r5759 mov $r5 0x00002601760 sethi $r5 0x00010000761 mov $r4 0x800762 shl b32 $r4 6763 iowr I[$r4 + 0x000] $r5764 ret765 766// Execute a copy operation767//768// Inputs:769// $r1: irqh state770// $r2: hostirq state771// $r3: data772// 000002000 QUERY_SHORT773// 000001000 QUERY774// 000000100 DST_LINEAR775// 000000010 SRC_LINEAR776// 000000001 FORMAT777// $r4: dispatch table entry778// Outputs:779// $r1: irqh state780// $p1: set on error781// $r2: hostirq state782// $r3: data783cmd_exec:784 call #cmd_exec_wait785 786 // if format requested, call function to calculate it, otherwise787 // fill in cpp/xcnt for both surfaces as if (cpp == 1)788 xbit $r15 $r3 0789 bra e #cmd_exec_no_format790 call #cmd_exec_set_format791 mov $r4 0x200792 bra #cmd_exec_init_src_surface793 cmd_exec_no_format:794 mov $r6 0x810795 shl b32 $r6 6796 mov $r7 1797 st b32 D[$r0 + #ctx_src_cpp] $r7798 st b32 D[$r0 + #ctx_dst_cpp] $r7799 ld b32 $r7 D[$r0 + #ctx_xcnt]800 iowr I[$r6 + 0x000] $r7801 iowr I[$r6 + 0x100] $r7802 clear b32 $r4803 804 cmd_exec_init_src_surface:805 bclr $flags $p2806 clear b32 $r5807 xbit $r15 $r3 4808 bra e #src_tiled809 call #cmd_exec_set_surface_linear810 bra #cmd_exec_init_dst_surface811 src_tiled:812 call #cmd_exec_set_surface_tiled813 bset $r4 7814 815 cmd_exec_init_dst_surface:816 bset $flags $p2817 mov $r5 #ctx_dst_address_high - #ctx_src_address_high818 xbit $r15 $r3 8819 bra e #dst_tiled820 call #cmd_exec_set_surface_linear821 bra #cmd_exec_kick822 dst_tiled:823 call #cmd_exec_set_surface_tiled824 bset $r4 8825 826 cmd_exec_kick:827 mov $r5 0x800828 shl b32 $r5 6829 ld b32 $r6 D[$r0 + #ctx_ycnt]830 iowr I[$r5 + 0x100] $r6831 mov $r6 0x0041832 // SRC_TARGET = 1, DST_TARGET = 2833 sethi $r6 0x44000000834 or $r4 $r6835 iowr I[$r5] $r4836 837 // if requested, queue up a QUERY write after the copy has completed838 xbit $r15 $r3 12839 bra e #cmd_exec_done840 call #cmd_exec_query841 842 cmd_exec_done:843 ret844 845// Flush write cache846//847// Inputs:848// $r1: irqh state849// $r2: hostirq state850// $r3: data851// $r4: dispatch table entry852// Outputs:853// $r1: irqh state854// $p1: set on error855// $r2: hostirq state856// $r3: data857cmd_wrcache_flush:858 mov $r2 0x2200859 clear b32 $r3860 sethi $r3 0x10000861 iowr I[$r2] $r3862 ret863 864.align 0x100865