103 lines · c
1/* SPDX-License-Identifier: MIT */2#ifndef __NVKM_DISP_DP_H__3#define __NVKM_DISP_DP_H__4#include "outp.h"5 6int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *,7 struct nvkm_outp **);8void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *);9void nvkm_dp_enable(struct nvkm_outp *, bool auxpwr);10 11/* DPCD Receiver Capabilities */12#define DPCD_RC00_DPCD_REV 0x0000013#define DPCD_RC01_MAX_LINK_RATE 0x0000114#define DPCD_RC02 0x0000215#define DPCD_RC02_ENHANCED_FRAME_CAP 0x8016#define DPCD_RC02_TPS3_SUPPORTED 0x4017#define DPCD_RC02_MAX_LANE_COUNT 0x1f18#define DPCD_RC03 0x0000319#define DPCD_RC03_TPS4_SUPPORTED 0x8020#define DPCD_RC03_MAX_DOWNSPREAD 0x0121#define DPCD_RC0E 0x0000e22#define DPCD_RC0E_AUX_RD_INTERVAL 0x7f23#define DPCD_RC10_SUPPORTED_LINK_RATES(i) 0x0001024#define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE 1625 26/* DPCD Link Configuration */27#define DPCD_LC00_LINK_BW_SET 0x0010028#define DPCD_LC01 0x0010129#define DPCD_LC01_ENHANCED_FRAME_EN 0x8030#define DPCD_LC01_LANE_COUNT_SET 0x1f31#define DPCD_LC02 0x0010232#define DPCD_LC02_TRAINING_PATTERN_SET 0x0f33#define DPCD_LC02_SCRAMBLING_DISABLE 0x2034#define DPCD_LC03(l) ((l) + 0x00103)35#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x2036#define DPCD_LC03_PRE_EMPHASIS_SET 0x1837#define DPCD_LC03_MAX_SWING_REACHED 0x0438#define DPCD_LC03_VOLTAGE_SWING_SET 0x0339#define DPCD_LC0F 0x0010f40#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x4041#define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x3042#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x0443#define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x0344#define DPCD_LC10 0x0011045#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x4046#define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x3047#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x0448#define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x0349#define DPCD_LC15_LINK_RATE_SET 0x0011550#define DPCD_LC15_LINK_RATE_SET_MASK 0x0751 52/* DPCD Link/Sink Status */53#define DPCD_LS02 0x0020254#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x4055#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x2056#define DPCD_LS02_LANE1_CR_DONE 0x1057#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x0458#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x0259#define DPCD_LS02_LANE0_CR_DONE 0x0160#define DPCD_LS03 0x0020361#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x4062#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x2063#define DPCD_LS03_LANE3_CR_DONE 0x1064#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x0465#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x0266#define DPCD_LS03_LANE2_CR_DONE 0x0167#define DPCD_LS04 0x0020468#define DPCD_LS04_LINK_STATUS_UPDATED 0x8069#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x4070#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x0171#define DPCD_LS06 0x0020672#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc073#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x3074#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c75#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x0376#define DPCD_LS07 0x0020777#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc078#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x3079#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c80#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x0381#define DPCD_LS0C 0x0020c82#define DPCD_LS0C_LANE3_POST_CURSOR2 0xc083#define DPCD_LS0C_LANE2_POST_CURSOR2 0x3084#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c85#define DPCD_LS0C_LANE0_POST_CURSOR2 0x0386 87/* DPCD Sink Control */88#define DPCD_SC00 0x0060089#define DPCD_SC00_SET_POWER 0x0390#define DPCD_SC00_SET_POWER_D0 0x0191#define DPCD_SC00_SET_POWER_D3 0x0392 93#define DPCD_LTTPR_REV 0xf000094#define DPCD_LTTPR_MODE 0xf000395#define DPCD_LTTPR_MODE_TRANSPARENT 0x5596#define DPCD_LTTPR_MODE_NON_TRANSPARENT 0xaa97#define DPCD_LTTPR_PATTERN_SET(i) ((i - 1) * 0x50 + 0xf0010)98#define DPCD_LTTPR_LANE0_SET(i) ((i - 1) * 0x50 + 0xf0011)99#define DPCD_LTTPR_AUX_RD_INTERVAL(i) ((i - 1) * 0x50 + 0xf0020)100#define DPCD_LTTPR_LANE0_1_STATUS(i) ((i - 1) * 0x50 + 0xf0030)101#define DPCD_LTTPR_LANE0_1_ADJUST(i) ((i - 1) * 0x50 + 0xf0033)102#endif103