134 lines · c
1/* SPDX-License-Identifier: MIT */2#ifndef __NV04_FIFO_REGS_H__3#define __NV04_FIFO_REGS_H__4 5#define NV04_PFIFO_DELAY_0 0x000020406#define NV04_PFIFO_DMA_TIMESLICE 0x000020447#define NV04_PFIFO_NEXT_CHANNEL 0x000020508#define NV03_PFIFO_INTR_0 0x000021009#define NV03_PFIFO_INTR_EN_0 0x0000214010# define NV_PFIFO_INTR_CACHE_ERROR (1<<0)11# define NV_PFIFO_INTR_RUNOUT (1<<4)12# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8)13# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)14# define NV_PFIFO_INTR_DMA_PT (1<<16)15# define NV_PFIFO_INTR_SEMAPHORE (1<<20)16# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)17#define NV03_PFIFO_RAMHT 0x0000221018#define NV03_PFIFO_RAMFC 0x0000221419#define NV03_PFIFO_RAMRO 0x0000221820#define NV40_PFIFO_RAMFC 0x0000222021#define NV03_PFIFO_CACHES 0x0000250022#define NV04_PFIFO_MODE 0x0000250423#define NV04_PFIFO_DMA 0x0000250824#define NV04_PFIFO_SIZE 0x0000250c25#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)26#define NV50_PFIFO_CTX_TABLE__SIZE 12827#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31)28#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30)29#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF30#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF31#define NV03_PFIFO_CACHE0_PUSH0 0x0000300032#define NV03_PFIFO_CACHE0_PULL0 0x0000304033#define NV04_PFIFO_CACHE0_PULL0 0x0000305034#define NV04_PFIFO_CACHE0_PULL1 0x0000305435#define NV03_PFIFO_CACHE1_PUSH0 0x0000320036#define NV03_PFIFO_CACHE1_PUSH1 0x0000320437#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8)38#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16)39#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f40#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f41#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f42#define NV03_PFIFO_CACHE1_PUT 0x0000321043#define NV04_PFIFO_CACHE1_DMA_PUSH 0x0000322044#define NV04_PFIFO_CACHE1_DMA_FETCH 0x0000322445# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x0000000046# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x0000000847# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x0000001048# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x0000001849# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x0000002050# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x0000002851# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x0000003052# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x0000003853# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x0000004054# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x0000004855# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000005056# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000005857# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000006058# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000006859# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000007060# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000007861# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x0000008062# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x0000008863# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x0000009064# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x0000009865# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A066# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A867# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B068# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B869# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C070# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C871# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D072# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D873# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E074# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E875# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F076# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F877# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E00078# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x0000000079# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x0000200080# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x0000400081# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x0000600082# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x0000800083# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A00084# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C00085# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E00086# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F000087# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x0000000088# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x0001000089# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x0002000090# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x0003000091# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x0004000092# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x0005000093# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x0006000094# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x0007000095# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x0008000096# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x0009000097# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A000098# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B000099# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000100# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000101# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000102# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000103# define NV_PFIFO_CACHE1_ENDIAN 0x80000000104# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF105# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000106#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228107#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c108#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230109#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240110#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244111#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248112#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C113#define NV03_PFIFO_CACHE1_PULL0 0x00003240114#define NV04_PFIFO_CACHE1_PULL0 0x00003250115# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010116# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000117#define NV03_PFIFO_CACHE1_PULL1 0x00003250118#define NV04_PFIFO_CACHE1_PULL1 0x00003254119#define NV04_PFIFO_CACHE1_HASH 0x00003258120#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260121#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264122#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268123#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C124#define NV03_PFIFO_CACHE1_GET 0x00003270125#define NV04_PFIFO_CACHE1_ENGINE 0x00003280126#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0127#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0128#define NV40_PFIFO_UNK32E4 0x000032E4129#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))130#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))131#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))132#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))133#endif134