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1/*2 * Copyright 2013 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Ben Skeggs <bskeggs@redhat.com>23 */24#include "gf100.h"25#include "gk104.h"26#include "ctxgf100.h"27 28#include <nvif/class.h>29 30/*******************************************************************************31 * PGRAPH register lists32 ******************************************************************************/33 34const struct gf100_gr_init35gk104_gr_init_main_0[] = {36 { 0x400080, 1, 0x04, 0x003083c2 },37 { 0x400088, 1, 0x04, 0x0001ffe7 },38 { 0x40008c, 1, 0x04, 0x00000000 },39 { 0x400090, 1, 0x04, 0x00000030 },40 { 0x40013c, 1, 0x04, 0x003901f7 },41 { 0x400140, 1, 0x04, 0x00000100 },42 { 0x400144, 1, 0x04, 0x00000000 },43 { 0x400148, 1, 0x04, 0x00000110 },44 { 0x400138, 1, 0x04, 0x00000000 },45 { 0x400130, 2, 0x04, 0x00000000 },46 { 0x400124, 1, 0x04, 0x00000002 },47 {}48};49 50static const struct gf100_gr_init51gk104_gr_init_ds_0[] = {52 { 0x405844, 1, 0x04, 0x00ffffff },53 { 0x405850, 1, 0x04, 0x00000000 },54 { 0x405900, 1, 0x04, 0x0000ff34 },55 { 0x405908, 1, 0x04, 0x00000000 },56 { 0x405928, 2, 0x04, 0x00000000 },57 {}58};59 60static const struct gf100_gr_init61gk104_gr_init_sked_0[] = {62 { 0x407010, 1, 0x04, 0x00000000 },63 {}64};65 66static const struct gf100_gr_init67gk104_gr_init_cwd_0[] = {68 { 0x405b50, 1, 0x04, 0x00000000 },69 {}70};71 72static const struct gf100_gr_init73gk104_gr_init_gpc_unk_1[] = {74 { 0x418d00, 1, 0x04, 0x00000000 },75 { 0x418d28, 2, 0x04, 0x00000000 },76 { 0x418f00, 1, 0x04, 0x00000000 },77 { 0x418f08, 1, 0x04, 0x00000000 },78 { 0x418f20, 2, 0x04, 0x00000000 },79 { 0x418e00, 1, 0x04, 0x00000060 },80 { 0x418e08, 1, 0x04, 0x00000000 },81 { 0x418e1c, 2, 0x04, 0x00000000 },82 {}83};84 85const struct gf100_gr_init86gk104_gr_init_gpc_unk_2[] = {87 { 0x418884, 1, 0x04, 0x00000000 },88 {}89};90 91const struct gf100_gr_init92gk104_gr_init_tpccs_0[] = {93 { 0x419d0c, 1, 0x04, 0x00000000 },94 { 0x419d10, 1, 0x04, 0x00000014 },95 {}96};97 98const struct gf100_gr_init99gk104_gr_init_pe_0[] = {100 { 0x41980c, 1, 0x04, 0x00000010 },101 { 0x419844, 1, 0x04, 0x00000000 },102 { 0x419850, 1, 0x04, 0x00000004 },103 { 0x419854, 2, 0x04, 0x00000000 },104 {}105};106 107static const struct gf100_gr_init108gk104_gr_init_l1c_0[] = {109 { 0x419c98, 1, 0x04, 0x00000000 },110 { 0x419ca8, 1, 0x04, 0x00000000 },111 { 0x419cb0, 1, 0x04, 0x01000000 },112 { 0x419cb4, 1, 0x04, 0x00000000 },113 { 0x419cb8, 1, 0x04, 0x00b08bea },114 { 0x419c84, 1, 0x04, 0x00010384 },115 { 0x419cbc, 1, 0x04, 0x28137646 },116 { 0x419cc0, 2, 0x04, 0x00000000 },117 { 0x419c80, 1, 0x04, 0x00020232 },118 {}119};120 121static const struct gf100_gr_init122gk104_gr_init_sm_0[] = {123 { 0x419e00, 1, 0x04, 0x00000000 },124 { 0x419ea0, 1, 0x04, 0x00000000 },125 { 0x419ee4, 1, 0x04, 0x00000000 },126 { 0x419ea4, 1, 0x04, 0x00000100 },127 { 0x419ea8, 1, 0x04, 0x00000000 },128 { 0x419eb4, 4, 0x04, 0x00000000 },129 { 0x419edc, 1, 0x04, 0x00000000 },130 { 0x419f00, 1, 0x04, 0x00000000 },131 { 0x419f74, 1, 0x04, 0x00000555 },132 {}133};134 135const struct gf100_gr_init136gk104_gr_init_be_0[] = {137 { 0x40880c, 1, 0x04, 0x00000000 },138 { 0x408850, 1, 0x04, 0x00000004 },139 { 0x408910, 9, 0x04, 0x00000000 },140 { 0x408950, 1, 0x04, 0x00000000 },141 { 0x408954, 1, 0x04, 0x0000ffff },142 { 0x408958, 1, 0x04, 0x00000034 },143 { 0x408984, 1, 0x04, 0x00000000 },144 { 0x408988, 1, 0x04, 0x08040201 },145 { 0x40898c, 1, 0x04, 0x80402010 },146 {}147};148 149const struct gf100_gr_pack150gk104_gr_pack_mmio[] = {151 { gk104_gr_init_main_0 },152 { gf100_gr_init_fe_0 },153 { gf100_gr_init_pri_0 },154 { gf100_gr_init_rstr2d_0 },155 { gf119_gr_init_pd_0 },156 { gk104_gr_init_ds_0 },157 { gf100_gr_init_scc_0 },158 { gk104_gr_init_sked_0 },159 { gk104_gr_init_cwd_0 },160 { gf119_gr_init_prop_0 },161 { gf108_gr_init_gpc_unk_0 },162 { gf100_gr_init_setup_0 },163 { gf100_gr_init_crstr_0 },164 { gf108_gr_init_setup_1 },165 { gf100_gr_init_zcull_0 },166 { gf119_gr_init_gpm_0 },167 { gk104_gr_init_gpc_unk_1 },168 { gf100_gr_init_gcc_0 },169 { gk104_gr_init_gpc_unk_2 },170 { gk104_gr_init_tpccs_0 },171 { gf119_gr_init_tex_0 },172 { gk104_gr_init_pe_0 },173 { gk104_gr_init_l1c_0 },174 { gf100_gr_init_mpc_0 },175 { gk104_gr_init_sm_0 },176 { gf117_gr_init_pes_0 },177 { gf117_gr_init_wwdx_0 },178 { gf117_gr_init_cbm_0 },179 { gk104_gr_init_be_0 },180 { gf100_gr_init_fe_1 },181 {}182};183 184const struct nvkm_therm_clkgate_init185gk104_clkgate_blcg_init_main_0[] = {186 { 0x4041f0, 1, 0x00004046 },187 { 0x409890, 1, 0x00000045 },188 { 0x4098b0, 1, 0x0000007f },189 {}190};191 192const struct nvkm_therm_clkgate_init193gk104_clkgate_blcg_init_rstr2d_0[] = {194 { 0x4078c0, 1, 0x00000042 },195 {}196};197 198const struct nvkm_therm_clkgate_init199gk104_clkgate_blcg_init_unk_0[] = {200 { 0x406000, 1, 0x00004044 },201 { 0x405860, 1, 0x00004042 },202 { 0x40590c, 1, 0x00004042 },203 {}204};205 206const struct nvkm_therm_clkgate_init207gk104_clkgate_blcg_init_gcc_0[] = {208 { 0x408040, 1, 0x00004044 },209 {}210};211 212const struct nvkm_therm_clkgate_init213gk104_clkgate_blcg_init_sked_0[] = {214 { 0x407000, 1, 0x00004044 },215 {}216};217 218const struct nvkm_therm_clkgate_init219gk104_clkgate_blcg_init_unk_1[] = {220 { 0x405bf0, 1, 0x00004044 },221 {}222};223 224const struct nvkm_therm_clkgate_init225gk104_clkgate_blcg_init_gpc_ctxctl_0[] = {226 { 0x41a890, 1, 0x00000042 },227 { 0x41a8b0, 1, 0x0000007f },228 {}229};230 231const struct nvkm_therm_clkgate_init232gk104_clkgate_blcg_init_gpc_unk_0[] = {233 { 0x418500, 1, 0x00004042 },234 { 0x418608, 1, 0x00004042 },235 { 0x418688, 1, 0x00004042 },236 { 0x418718, 1, 0x00000042 },237 {}238};239 240const struct nvkm_therm_clkgate_init241gk104_clkgate_blcg_init_gpc_esetup_0[] = {242 { 0x418828, 1, 0x00000044 },243 {}244};245 246const struct nvkm_therm_clkgate_init247gk104_clkgate_blcg_init_gpc_tpbus_0[] = {248 { 0x418bbc, 1, 0x00004042 },249 {}250};251 252const struct nvkm_therm_clkgate_init253gk104_clkgate_blcg_init_gpc_zcull_0[] = {254 { 0x418970, 1, 0x00004042 },255 {}256};257 258const struct nvkm_therm_clkgate_init259gk104_clkgate_blcg_init_gpc_tpconf_0[] = {260 { 0x418c70, 1, 0x00004042 },261 {}262};263 264const struct nvkm_therm_clkgate_init265gk104_clkgate_blcg_init_gpc_unk_1[] = {266 { 0x418cf0, 1, 0x00004042 },267 { 0x418d70, 1, 0x00004042 },268 { 0x418f0c, 1, 0x00004042 },269 { 0x418e0c, 1, 0x00004042 },270 {}271};272 273const struct nvkm_therm_clkgate_init274gk104_clkgate_blcg_init_gpc_gcc_0[] = {275 { 0x419020, 1, 0x00004042 },276 { 0x419038, 1, 0x00000042 },277 {}278};279 280const struct nvkm_therm_clkgate_init281gk104_clkgate_blcg_init_gpc_ffb_0[] = {282 { 0x418898, 1, 0x00000042 },283 {}284};285 286const struct nvkm_therm_clkgate_init287gk104_clkgate_blcg_init_gpc_tex_0[] = {288 { 0x419a40, 9, 0x00004042 },289 { 0x419acc, 1, 0x00004047 },290 {}291};292 293const struct nvkm_therm_clkgate_init294gk104_clkgate_blcg_init_gpc_poly_0[] = {295 { 0x419868, 1, 0x00000042 },296 {}297};298 299const struct nvkm_therm_clkgate_init300gk104_clkgate_blcg_init_gpc_l1c_0[] = {301 { 0x419ccc, 3, 0x00000042 },302 {}303};304 305const struct nvkm_therm_clkgate_init306gk104_clkgate_blcg_init_gpc_unk_2[] = {307 { 0x419c70, 1, 0x00004045 },308 {}309};310 311const struct nvkm_therm_clkgate_init312gk104_clkgate_blcg_init_gpc_mp_0[] = {313 { 0x419fd0, 1, 0x00004043 },314 { 0x419fd8, 1, 0x00004049 },315 { 0x419fe0, 2, 0x00004042 },316 { 0x419ff0, 1, 0x00004046 },317 { 0x419ff8, 1, 0x00004042 },318 {}319};320 321const struct nvkm_therm_clkgate_init322gk104_clkgate_blcg_init_gpc_ppc_0[] = {323 { 0x41be28, 1, 0x00000042 },324 { 0x41bfe8, 1, 0x00004042 },325 { 0x41bed0, 1, 0x00004042 },326 {}327};328 329const struct nvkm_therm_clkgate_init330gk104_clkgate_blcg_init_rop_zrop_0[] = {331 { 0x408810, 2, 0x00004042 },332 {}333};334 335const struct nvkm_therm_clkgate_init336gk104_clkgate_blcg_init_rop_0[] = {337 { 0x408a80, 6, 0x00004042 },338 {}339};340 341const struct nvkm_therm_clkgate_init342gk104_clkgate_blcg_init_rop_crop_0[] = {343 { 0x4089a8, 1, 0x00004042 },344 { 0x4089b0, 1, 0x00000042 },345 { 0x4089b8, 1, 0x00004042 },346 {}347};348 349const struct nvkm_therm_clkgate_init350gk104_clkgate_blcg_init_pxbar_0[] = {351 { 0x13c820, 1, 0x0001007f },352 { 0x13cbe0, 1, 0x00000042 },353 {}354};355 356static const struct nvkm_therm_clkgate_pack357gk104_clkgate_pack[] = {358 { gk104_clkgate_blcg_init_main_0 },359 { gk104_clkgate_blcg_init_rstr2d_0 },360 { gk104_clkgate_blcg_init_unk_0 },361 { gk104_clkgate_blcg_init_gcc_0 },362 { gk104_clkgate_blcg_init_sked_0 },363 { gk104_clkgate_blcg_init_unk_1 },364 { gk104_clkgate_blcg_init_gpc_ctxctl_0 },365 { gk104_clkgate_blcg_init_gpc_unk_0 },366 { gk104_clkgate_blcg_init_gpc_esetup_0 },367 { gk104_clkgate_blcg_init_gpc_tpbus_0 },368 { gk104_clkgate_blcg_init_gpc_zcull_0 },369 { gk104_clkgate_blcg_init_gpc_tpconf_0 },370 { gk104_clkgate_blcg_init_gpc_unk_1 },371 { gk104_clkgate_blcg_init_gpc_gcc_0 },372 { gk104_clkgate_blcg_init_gpc_ffb_0 },373 { gk104_clkgate_blcg_init_gpc_tex_0 },374 { gk104_clkgate_blcg_init_gpc_poly_0 },375 { gk104_clkgate_blcg_init_gpc_l1c_0 },376 { gk104_clkgate_blcg_init_gpc_unk_2 },377 { gk104_clkgate_blcg_init_gpc_mp_0 },378 { gk104_clkgate_blcg_init_gpc_ppc_0 },379 { gk104_clkgate_blcg_init_rop_zrop_0 },380 { gk104_clkgate_blcg_init_rop_0 },381 { gk104_clkgate_blcg_init_rop_crop_0 },382 { gk104_clkgate_blcg_init_pxbar_0 },383 {}384};385 386/*******************************************************************************387 * PGRAPH engine/subdev functions388 ******************************************************************************/389 390void391gk104_gr_init_sked_hww_esr(struct gf100_gr *gr)392{393 nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000);394}395 396static void397gk104_gr_init_fecs_exceptions(struct gf100_gr *gr)398{399 struct nvkm_device *device = gr->base.engine.subdev.device;400 nvkm_wr32(device, 0x409ffc, 0x00000000);401 nvkm_wr32(device, 0x409c14, 0x00003e3e);402 nvkm_wr32(device, 0x409c24, 0x000f0001);403}404 405void406gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)407{408 struct nvkm_device *device = gr->base.engine.subdev.device;409 const u32 fbp_count = nvkm_rd32(device, 0x120074);410 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */411 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */412}413 414void415gk104_gr_init_ppc_exceptions(struct gf100_gr *gr)416{417 struct nvkm_device *device = gr->base.engine.subdev.device;418 int gpc, ppc;419 420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {421 for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {422 if (!(gr->ppc_mask[gpc] & (1 << ppc)))423 continue;424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);425 }426 }427}428 429void430gk104_gr_init_vsc_stream_master(struct gf100_gr *gr)431{432 struct nvkm_device *device = gr->base.engine.subdev.device;433 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);434}435 436#include "fuc/hubgk104.fuc3.h"437 438static struct gf100_gr_ucode439gk104_gr_fecs_ucode = {440 .code.data = gk104_grhub_code,441 .code.size = sizeof(gk104_grhub_code),442 .data.data = gk104_grhub_data,443 .data.size = sizeof(gk104_grhub_data),444};445 446#include "fuc/gpcgk104.fuc3.h"447 448static struct gf100_gr_ucode449gk104_gr_gpccs_ucode = {450 .code.data = gk104_grgpc_code,451 .code.size = sizeof(gk104_grgpc_code),452 .data.data = gk104_grgpc_data,453 .data.size = sizeof(gk104_grgpc_data),454};455 456static const struct gf100_gr_func457gk104_gr = {458 .oneinit_tiles = gf100_gr_oneinit_tiles,459 .oneinit_sm_id = gf100_gr_oneinit_sm_id,460 .init = gf100_gr_init,461 .init_gpc_mmu = gf100_gr_init_gpc_mmu,462 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,463 .init_zcull = gf117_gr_init_zcull,464 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,465 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,466 .init_fecs_exceptions = gk104_gr_init_fecs_exceptions,467 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,468 .init_419cc0 = gf100_gr_init_419cc0,469 .init_419eb4 = gf100_gr_init_419eb4,470 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,471 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,472 .init_shader_exceptions = gf100_gr_init_shader_exceptions,473 .init_rop_exceptions = gf100_gr_init_rop_exceptions,474 .init_exception2 = gf100_gr_init_exception2,475 .init_400054 = gf100_gr_init_400054,476 .trap_mp = gf100_gr_trap_mp,477 .mmio = gk104_gr_pack_mmio,478 .fecs.ucode = &gk104_gr_fecs_ucode,479 .fecs.reset = gf100_gr_fecs_reset,480 .gpccs.ucode = &gk104_gr_gpccs_ucode,481 .rops = gf100_gr_rops,482 .ppc_nr = 1,483 .grctx = &gk104_grctx,484 .clkgate_pack = gk104_clkgate_pack,485 .zbc = &gf100_gr_zbc,486 .sclass = {487 { -1, -1, FERMI_TWOD_A },488 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },489 { -1, -1, KEPLER_A, &gf100_fermi },490 { -1, -1, KEPLER_COMPUTE_A },491 {}492 }493};494 495static const struct gf100_gr_fwif496gk104_gr_fwif[] = {497 { -1, gf100_gr_load, &gk104_gr },498 { -1, gf100_gr_nofw, &gk104_gr },499 {}500};501 502int503gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)504{505 return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr);506}507