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1// SPDX-License-Identifier: MIT2#include "nv20.h"3#include "regs.h"4 5#include <core/gpuobj.h>6#include <engine/fifo.h>7#include <engine/fifo/chan.h>8 9/*******************************************************************************10 * PGRAPH context11 ******************************************************************************/12 13static const struct nvkm_object_func14nv2a_gr_chan = {15 .dtor = nv20_gr_chan_dtor,16 .init = nv20_gr_chan_init,17 .fini = nv20_gr_chan_fini,18};19 20static int21nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,22 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)23{24 struct nv20_gr *gr = nv20_gr(base);25 struct nv20_gr_chan *chan;26 int ret, i;27 28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))29 return -ENOMEM;30 nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object);31 chan->gr = gr;32 chan->chid = fifoch->id;33 *pobject = &chan->object;34 35 ret = nvkm_memory_new(gr->base.engine.subdev.device,36 NVKM_MEM_TARGET_INST, 0x36b0, 16, true,37 &chan->inst);38 if (ret)39 return ret;40 41 nvkm_kmap(chan->inst);42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);46 nvkm_wo32(chan->inst, 0x047c, 0x00000101);47 nvkm_wo32(chan->inst, 0x0490, 0x00000111);48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);49 for (i = 0x04d4; i <= 0x04e0; i += 4)50 nvkm_wo32(chan->inst, i, 0x00030303);51 for (i = 0x04f4; i <= 0x0500; i += 4)52 nvkm_wo32(chan->inst, i, 0x00080000);53 for (i = 0x050c; i <= 0x0518; i += 4)54 nvkm_wo32(chan->inst, i, 0x01012000);55 for (i = 0x051c; i <= 0x0528; i += 4)56 nvkm_wo32(chan->inst, i, 0x000105b8);57 for (i = 0x052c; i <= 0x0538; i += 4)58 nvkm_wo32(chan->inst, i, 0x00080008);59 for (i = 0x055c; i <= 0x0598; i += 4)60 nvkm_wo32(chan->inst, i, 0x07ff0000);61 nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);62 nvkm_wo32(chan->inst, 0x05fc, 0x00000001);63 nvkm_wo32(chan->inst, 0x0604, 0x00004000);64 nvkm_wo32(chan->inst, 0x0610, 0x00000001);65 nvkm_wo32(chan->inst, 0x0618, 0x00040000);66 nvkm_wo32(chan->inst, 0x061c, 0x00010000);67 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */68 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);69 nvkm_wo32(chan->inst, (i + 4), 0x0436086c);70 nvkm_wo32(chan->inst, (i + 8), 0x000c001b);71 }72 nvkm_wo32(chan->inst, 0x269c, 0x3f800000);73 nvkm_wo32(chan->inst, 0x26b0, 0x3f800000);74 nvkm_wo32(chan->inst, 0x26dc, 0x40000000);75 nvkm_wo32(chan->inst, 0x26e0, 0x3f800000);76 nvkm_wo32(chan->inst, 0x26e4, 0x3f000000);77 nvkm_wo32(chan->inst, 0x26ec, 0x40000000);78 nvkm_wo32(chan->inst, 0x26f0, 0x3f800000);79 nvkm_wo32(chan->inst, 0x26f8, 0xbf800000);80 nvkm_wo32(chan->inst, 0x2700, 0xbf800000);81 nvkm_wo32(chan->inst, 0x3024, 0x000fe000);82 nvkm_wo32(chan->inst, 0x30a0, 0x000003f8);83 nvkm_wo32(chan->inst, 0x33fc, 0x002fe000);84 for (i = 0x341c; i <= 0x3438; i += 4)85 nvkm_wo32(chan->inst, i, 0x001c527c);86 nvkm_done(chan->inst);87 return 0;88}89 90/*******************************************************************************91 * PGRAPH engine/subdev functions92 ******************************************************************************/93 94static const struct nvkm_gr_func95nv2a_gr = {96 .dtor = nv20_gr_dtor,97 .oneinit = nv20_gr_oneinit,98 .init = nv20_gr_init,99 .intr = nv20_gr_intr,100 .tile = nv20_gr_tile,101 .chan_new = nv2a_gr_chan_new,102 .sclass = {103 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */104 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */105 { -1, -1, 0x0030, &nv04_gr_object }, /* null */106 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */107 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */108 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */109 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */110 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */111 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */112 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */113 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */114 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */115 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */116 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */117 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */118 {}119 }120};121 122int123nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)124{125 return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr);126}127