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1/*2 * Copyright 2019 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#include "gf100.h"23#include "ctxgf100.h"24 25#include <subdev/gsp.h>26 27#include <nvif/class.h>28 29void30tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)31{32 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);33}34 35void36tu102_gr_init_fs(struct gf100_gr *gr)37{38 struct nvkm_device *device = gr->base.engine.subdev.device;39 int sm;40 41 gp100_grctx_generate_smid_config(gr);42 gk104_grctx_generate_gpc_tpc_nr(gr);43 44 for (sm = 0; sm < gr->sm_nr; sm++) {45 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc);46 47 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm);48 }49 50 gm200_grctx_generate_dist_skip_table(gr);51 gf100_gr_init_num_tpc_per_gpc(gr, true, true);52}53 54void55tu102_gr_init_zcull(struct gf100_gr *gr)56{57 struct nvkm_device *device = gr->base.engine.subdev.device;58 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);59 const u8 tile_nr = gr->func->gpc_nr * gr->func->tpc_nr;60 u8 bank[GPC_MAX] = {}, gpc, i, j;61 u32 data;62 63 for (i = 0; i < tile_nr; i += 8) {64 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {65 data |= bank[gr->tile[i + j]] << (j * 4);66 bank[gr->tile[i + j]]++;67 }68 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);69 }70 71 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {72 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),73 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);74 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |75 gr->tpc_total);76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);77 }78 79 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);80}81 82static void83tu102_gr_init_gpc_mmu(struct gf100_gr *gr)84{85 struct nvkm_device *device = gr->base.engine.subdev.device;86 87 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);88 nvkm_wr32(device, 0x418890, 0x00000000);89 nvkm_wr32(device, 0x418894, 0x00000000);90 91 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));92 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));93 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));94}95 96static const struct gf100_gr_func97tu102_gr = {98 .oneinit_tiles = gm200_gr_oneinit_tiles,99 .oneinit_sm_id = gv100_gr_oneinit_sm_id,100 .init = gf100_gr_init,101 .init_419bd8 = gv100_gr_init_419bd8,102 .init_gpc_mmu = tu102_gr_init_gpc_mmu,103 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,104 .init_zcull = tu102_gr_init_zcull,105 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,106 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,107 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,108 .init_fs = tu102_gr_init_fs,109 .init_fecs_exceptions = tu102_gr_init_fecs_exceptions,110 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,111 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,112 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,113 .init_504430 = gv100_gr_init_504430,114 .init_shader_exceptions = gv100_gr_init_shader_exceptions,115 .init_rop_exceptions = gf100_gr_init_rop_exceptions,116 .init_exception2 = gf100_gr_init_exception2,117 .init_4188a4 = gv100_gr_init_4188a4,118 .trap_mp = gv100_gr_trap_mp,119 .fecs.reset = gf100_gr_fecs_reset,120 .rops = gm200_gr_rops,121 .gpc_nr = 6,122 .tpc_nr = 6,123 .ppc_nr = 3,124 .grctx = &tu102_grctx,125 .zbc = &gp102_gr_zbc,126 .sclass = {127 { -1, -1, FERMI_TWOD_A },128 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },129 { -1, -1, TURING_A, &gf100_fermi },130 { -1, -1, TURING_COMPUTE_A },131 {}132 }133};134 135MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin");136MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin");137MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin");138MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin");139MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin");140MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin");141MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin");142MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin");143MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin");144MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin");145MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin");146MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin");147MODULE_FIRMWARE("nvidia/tu102/gr/sw_veid_bundle_init.bin");148 149MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin");150MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin");151MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin");152MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin");153MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin");154MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin");155MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin");156MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin");157MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin");158MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin");159MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin");160MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin");161MODULE_FIRMWARE("nvidia/tu104/gr/sw_veid_bundle_init.bin");162 163MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin");164MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin");165MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin");166MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin");167MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin");168MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin");169MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin");170MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin");171MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin");172MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");173MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");174MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");175MODULE_FIRMWARE("nvidia/tu106/gr/sw_veid_bundle_init.bin");176 177MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");178MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");179MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");180MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");181MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");182MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");183MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");184MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");185MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");186MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");187MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");188MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");189MODULE_FIRMWARE("nvidia/tu117/gr/sw_veid_bundle_init.bin");190 191MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");192MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");193MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");194MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");195MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");196MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");197MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");198MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");199MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");200MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");201MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");202MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");203MODULE_FIRMWARE("nvidia/tu116/gr/sw_veid_bundle_init.bin");204 205int206tu102_gr_av_to_init_veid(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)207{208 return gk20a_gr_av_to_init_(blob, 64, 0x00100000, ppack);209}210 211static const struct gf100_gr_fwif212tu102_gr_fwif[] = {213 { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },214 { -1, gm200_gr_nofw },215 {}216};217 218int219tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)220{221 if (nvkm_gsp_rm(device->gsp))222 return r535_gr_new(&tu102_gr, device, type, inst, pgr);223 224 return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);225}226