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1/*2 * Copyright 2019 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#include <core/subdev.h>23#include <nvfw/acr.h>24 25void26wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)27{28 nvkm_debug(subdev, "wprHeader\n");29 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);30 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);31 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);32 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);33 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);34}35 36void37wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)38{39 nvkm_debug(subdev, "wprHeader\n");40 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);41 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);42 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);43 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);44 nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version);45 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);46}47 48static void49wpr_generic_header_dump(struct nvkm_subdev *subdev, const struct wpr_generic_header *hdr)50{51 nvkm_debug(subdev, "wprGenericHeader\n");52 nvkm_debug(subdev, "\tidentifier : %04x\n", hdr->identifier);53 nvkm_debug(subdev, "\tversion : %04x\n", hdr->version);54 nvkm_debug(subdev, "\tsize : %08x\n", hdr->size);55}56 57void58wpr_header_v2_dump(struct nvkm_subdev *subdev, const struct wpr_header_v2 *hdr)59{60 wpr_generic_header_dump(subdev, &hdr->hdr);61 wpr_header_v1_dump(subdev, &hdr->wpr);62}63 64void65lsb_header_v2_dump(struct nvkm_subdev *subdev, struct lsb_header_v2 *hdr)66{67 wpr_generic_header_dump(subdev, &hdr->hdr);68 nvkm_debug(subdev, "lsbHeader\n");69 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);70 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);71 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);72 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);73 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);74 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);75 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);76 nvkm_debug(subdev, "\treserved0 : %08x\n", hdr->rsvd0);77 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);78 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);79 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);80 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);81 nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", hdr->app_imem_offset);82 nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", hdr->app_dmem_offset);83 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);84 nvkm_debug(subdev, "\tmonitorCodeOff: 0x%x\n", hdr->monitor_code_offset);85 nvkm_debug(subdev, "\tmonitorDataOff: 0x%x\n", hdr->monitor_data_offset);86 nvkm_debug(subdev, "\tmanifestOffset: 0x%x\n", hdr->manifest_offset);87}88 89static void90lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr)91{92 nvkm_debug(subdev, "lsbHeader\n");93 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);94 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);95 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);96 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);97 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);98 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);99 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);100 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);101 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);102 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);103 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);104 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);105}106 107void108lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)109{110 lsb_header_tail_dump(subdev, &hdr->tail);111}112 113void114lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)115{116 lsb_header_tail_dump(subdev, &hdr->tail);117}118 119void120flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)121{122 int i;123 124 nvkm_debug(subdev, "acrDesc\n");125 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);126 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);127 nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n",128 hdr->mmu_mem_range);129 nvkm_debug(subdev, "\tnoRegions : %d\n",130 hdr->regions.no_regions);131 132 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {133 nvkm_debug(subdev, "\tregion[%d] :\n", i);134 nvkm_debug(subdev, "\t startAddr : 0x%x\n",135 hdr->regions.region_props[i].start_addr);136 nvkm_debug(subdev, "\t endAddr : 0x%x\n",137 hdr->regions.region_props[i].end_addr);138 nvkm_debug(subdev, "\t regionId : %d\n",139 hdr->regions.region_props[i].region_id);140 nvkm_debug(subdev, "\t readMask : 0x%x\n",141 hdr->regions.region_props[i].read_mask);142 nvkm_debug(subdev, "\t writeMask : 0x%x\n",143 hdr->regions.region_props[i].write_mask);144 nvkm_debug(subdev, "\t clientMask : 0x%x\n",145 hdr->regions.region_props[i].client_mask);146 }147 148 nvkm_debug(subdev, "\tucodeBlobSize: %d\n",149 hdr->ucode_blob_size);150 nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",151 hdr->ucode_blob_base);152 nvkm_debug(subdev, "\tvprEnabled : %d\n",153 hdr->vpr_desc.vpr_enabled);154 nvkm_debug(subdev, "\tvprStart : 0x%x\n",155 hdr->vpr_desc.vpr_start);156 nvkm_debug(subdev, "\tvprEnd : 0x%x\n",157 hdr->vpr_desc.vpr_end);158 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",159 hdr->vpr_desc.hdcp_policies);160}161 162void163flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)164{165 int i;166 167 nvkm_debug(subdev, "acrDesc\n");168 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);169 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);170 nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n",171 hdr->mmu_memory_range);172 nvkm_debug(subdev, "\tnoRegions : %d\n",173 hdr->regions.no_regions);174 175 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {176 nvkm_debug(subdev, "\tregion[%d] :\n", i);177 nvkm_debug(subdev, "\t startAddr : 0x%x\n",178 hdr->regions.region_props[i].start_addr);179 nvkm_debug(subdev, "\t endAddr : 0x%x\n",180 hdr->regions.region_props[i].end_addr);181 nvkm_debug(subdev, "\t regionId : %d\n",182 hdr->regions.region_props[i].region_id);183 nvkm_debug(subdev, "\t readMask : 0x%x\n",184 hdr->regions.region_props[i].read_mask);185 nvkm_debug(subdev, "\t writeMask : 0x%x\n",186 hdr->regions.region_props[i].write_mask);187 nvkm_debug(subdev, "\t clientMask : 0x%x\n",188 hdr->regions.region_props[i].client_mask);189 nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n",190 hdr->regions.region_props[i].shadow_mem_start_addr);191 }192 193 nvkm_debug(subdev, "\tucodeBlobSize : %d\n",194 hdr->ucode_blob_size);195 nvkm_debug(subdev, "\tucodeBlobBase : 0x%llx\n",196 hdr->ucode_blob_base);197 nvkm_debug(subdev, "\tvprEnabled : %d\n",198 hdr->vpr_desc.vpr_enabled);199 nvkm_debug(subdev, "\tvprStart : 0x%x\n",200 hdr->vpr_desc.vpr_start);201 nvkm_debug(subdev, "\tvprEnd : 0x%x\n",202 hdr->vpr_desc.vpr_end);203 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",204 hdr->vpr_desc.hdcp_policies);205}206