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1/*2 * Copyright 2019 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#include "priv.h"23 24#include <core/firmware.h>25#include <core/memory.h>26#include <subdev/mmu.h>27#include <subdev/pmu.h>28 29#include <nvfw/acr.h>30#include <nvfw/flcn.h>31 32int33gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)34{35 struct nvkm_subdev *subdev = &acr->subdev;36 37 acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end);38 39 if ((acr->wpr_end - acr->wpr_start) < wpr_size) {40 nvkm_error(subdev, "WPR image too big for WPR!\n");41 return -ENOSPC;42 }43 44 return nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,45 wpr_size, 0, true, &acr->wpr);46}47 48static int49gm20b_acr_hsfw_load_bld(struct nvkm_falcon_fw *fw)50{51 struct flcn_bl_dmem_desc hsdesc = {52 .ctx_dma = FALCON_DMAIDX_VIRT,53 .code_dma_base = fw->vma->addr >> 8,54 .non_sec_code_off = fw->nmem_base,55 .non_sec_code_size = fw->nmem_size,56 .sec_code_off = fw->imem_base,57 .sec_code_size = fw->imem_size,58 .code_entry_point = 0,59 .data_dma_base = (fw->vma->addr + fw->dmem_base_img) >> 8,60 .data_size = fw->dmem_size,61 };62 63 flcn_bl_dmem_desc_dump(fw->falcon->user, &hsdesc);64 65 return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);66}67 68 69static int70gm20b_acr_load_setup(struct nvkm_falcon_fw *fw)71{72 struct flcn_acr_desc *desc = (void *)&fw->fw.img[fw->dmem_base_img];73 struct nvkm_acr *acr = fw->falcon->owner->device->acr;74 75 desc->ucode_blob_base = nvkm_memory_addr(acr->wpr);76 desc->ucode_blob_size = nvkm_memory_size(acr->wpr);77 flcn_acr_desc_dump(&acr->subdev, desc);78 return 0;79}80 81const struct nvkm_falcon_fw_func82gm20b_acr_load_0 = {83 .signature = gm200_flcn_fw_signature,84 .reset = gm200_flcn_fw_reset,85 .setup = gm20b_acr_load_setup,86 .load = gm200_flcn_fw_load,87 .load_bld = gm20b_acr_hsfw_load_bld,88 .boot = gm200_flcn_fw_boot,89};90 91#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)92MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");93MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");94#endif95 96static const struct nvkm_acr_hsf_fwif97gm20b_acr_load_fwif[] = {98 { 0, gm200_acr_hsfw_ctor, &gm20b_acr_load_0, NVKM_ACR_HSF_PMU, 0, 0x10 },99 {}100};101 102static const struct nvkm_acr_func103gm20b_acr = {104 .load = gm20b_acr_load_fwif,105 .wpr_parse = gm200_acr_wpr_parse,106 .wpr_layout = gm200_acr_wpr_layout,107 .wpr_alloc = gm20b_acr_wpr_alloc,108 .wpr_build = gm200_acr_wpr_build,109 .wpr_patch = gm200_acr_wpr_patch,110 .wpr_check = gm200_acr_wpr_check,111 .init = gm200_acr_init,112};113 114int115gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)116{117 struct nvkm_subdev *subdev = &acr->subdev;118 const struct nvkm_acr_hsf_fwif *hsfwif;119 120 hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",121 acr, "acr/bl", "acr/ucode_load", "load");122 if (IS_ERR(hsfwif))123 return PTR_ERR(hsfwif);124 125 return 0;126}127 128static const struct nvkm_acr_fwif129gm20b_acr_fwif[] = {130 { 0, gm20b_acr_load, &gm20b_acr },131 { -1, gm200_acr_nofw, &gm200_acr },132 {}133};134 135int136gm20b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,137 struct nvkm_acr **pacr)138{139 return nvkm_acr_new_(gm20b_acr_fwif, device, type, inst, pacr);140}141